JPH08251558A - Display control circuit - Google Patents

Abstract

PURPOSE: To suppress the rise in the price of a system by managing with a small-capacity line buffer memory even when a horizontal compressing function is provided. CONSTITUTION: Display data (dot pattern data and attribute data on a foreground color, a background color, and a flashing process) extracted from a teletext broadcasting signal are written in a display memory 30 through a display memory control part 200. The display data in the display memory 30 are read out by the display memory control part 200, which operates in specific timing, in synchronism with a television main body, the write speed and read speed are controlled to send the data to a line buffer memory 100 which compresses the data horizontally, and the output of this memory 100 is inputted to an RGB decoder 40 and converted into an R, G, and a B signal, a Y signal, a television/character switching signal (Ys), and a television half-tone signal (YM).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a teletext receiving system for decoding a teletext signal superimposed on a vertical blanking period of a video signal, and is particularly suitable for displaying a teletext screen in a reduced size. The present invention relates to a display control circuit.

[0002]

2. Description of the Related Art A teletext system superimposes teletext program data consisting of characters and figures during a predetermined horizontal scanning period in a vertical blanking period of a video signal and transmits the data, and the receiver desires the receiver. A communication system in which program data of a program is extracted from a vertical blanking period of a video signal and written in an image memory so that a desired teletext program can be viewed.

When displaying a teletext screen, the contents of the television broadcast cannot be viewed at the same time, and therefore, they are described in JP-A-2-54688, JP-A-3-190389, and JP-A-4-200194. As described above, a means for temporally compressing teletext display information in the horizontal direction is provided, and the teletext screen compressed by this compression means is displayed together with the television broadcast screen.

FIG. 2 is a block diagram showing an example of a conventional circuit for temporally compressing teletext display information in the horizontal direction.
Further, FIG. 3 is a conversion image diagram of display data by the RGB decoder 40.

In the teletext receiving system, the teletext signal multiplexed in the vertical blanking period of the video signal is extracted. From the extracted character multiplex signals, the signal of the program desired by the receiver is introduced into the character multiplex signal processing unit (not shown). Here, the program data of the teletext program is converted into display data composed of dot pattern data, foreground color, background color, and attribute data such as flushing processing.
This display data is stored in a control circuit (CP not shown).
Under the control of U), the data is input to the display memory control unit 20 via the data line 10, and further the display memory control unit 2
It is written in the display memory 30 via 0. The display data stored in the display memory 30 is read by the display memory control unit 20 which operates in synchronization with the television main body at a predetermined timing, and is sent to the RGB decoder 40 for screen display. As shown in FIG. 3, the RGB decoder 40 converts the display data into a color data signal (R (red)).
Signal, G (green) signal, B (blue) signal, Y (luminance) signal), television / character switching signal (Ys), and television halftone signal (YM). Here, the color data signal is assumed to be a binary R signal, G signal, B signal, and Y signal.

The display data converted by the decoder is sent to the line buffer memory 50. The line buffer memory 50 handles data to be displayed line by line, and the data output from this is written in the color memory 60 as R, G, and B signals. In the line buffer memory 50, writing speed / reading speed is controlled, and horizontal compression processing is possible. The signal read from the color memory 60 is input to the D / A converter 70, converted into analog R, G, B signals, and output to the display unit of the television body (not shown).

As described above, if the teletext data is compressed horizontally in the line buffer memory 50,
Other television broadcast programs being received can be simultaneously viewed on the screen.

However, as shown in FIG. 3, the line buffer memory 50 for performing horizontal time compression is as follows.
The signals for time compression are R, G, B, Y and Y.
Six systems (6 bits) of s and YM are required. For this reason, the capacity of the line buffer memory 50 is increased, and in particular, when the line buffer memory is incorporated in the IC circuit, the gate scale becomes large and the cost of the IC becomes high.

[0009]

As described above, when the display control circuit of the conventional teletext receiving system is provided with the horizontal compression function of the teletext screen, the capacity of the line buffer memory is increased, In particular, when the circuit is constructed as an IC circuit, the gate scale becomes large, and as a result, there is a problem that the price of the IC becomes high.

Therefore, it is an object of the present invention to provide a display control circuit capable of suppressing an increase in system cost even though the capacity of the line buffer memory is small even if it has a horizontal compression function.

[0011]

According to the present invention, a dot pattern data before being supplied to the RGB decoding means and attribute data such as a foreground color, a background color and a flushing process are provided in the preceding stage of the RGB decoding means. There is provided a means for temporally compressing the 4-bit data to be generated in the horizontal direction in advance.

[0012]

According to the above means, the line buffer memory, which conventionally required 6 bits, can be reduced to a 4-bit line buffer memory. That is, 2/3 of the conventional
The line buffer memory with the capacity of enables the horizontal time compression of the teletext screen.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1A, display data (dot pattern data, foreground color,
Attribute data such as background color and flushing processing) is input to the display memory control unit 200 via the data line 10 and further written to the display memory 30 via the display memory control unit 200. The above display data is from the character multiplexed signal multiplexed in the vertical blanking period of the video signal,
The signal of the program desired by the receiver is extracted by a character multiplex signal processing unit (not shown), and the program data of the character broadcasting program is decoded into attribute data such as dot pattern data, foreground color, background color, and flushing processing. is there.

The display data stored in the display memory 30 is read by the display memory control unit 200 which operates in synchronization with the television main body at a predetermined timing and is sent to the line buffer memory 100. In this line buffer memory 100, the writing speed / reading speed is controlled, and the data compression processing in the horizontal direction is possible by increasing the reading speed with respect to the writing speed.

The data read from the line buffer memory 100 is input to the RGB decoder 40, and the RGB
Converted to a signal. As described with reference to FIG. 4, the RGB decoder 40 displays the display data (dot pattern data,
Foreground color, background color and attribute data) color data signals (R (red) signal, G (green) signal, B (blue) signal, Y (luminance) signal), TV / character switching signal (Ys), TV half Convert to tone signal (YM). Next, the color data signals (R, G, B, Y) are input to the color memory 60 and at least 2 bits each of R, G, and
It is converted and output as a B signal, and converted to an analog RGB signal and output to the D / A converter 70.

In the above embodiment, the function of compressing the screen of the teletext program in the horizontal direction is the line buffer memory 100.
However, here, dot pattern data (binary), foreground color (binary), background color (binary) are used.
And a total of 4 bits of attribute data (binary) are handled. For this reason, it is not necessary to process 6 bits as in the conventional case, and it can be realized by a memory having a capacity of 2/3 that of the conventional case.

FIG. 1B shows the display memory control unit 20.
A specific configuration of 0 is shown. Display data from the CPU is written in the display memory 30 via the memory access circuit 201 and the selection circuit 202. Further, the display memory 30
The display data read from is read via the selection circuit 202 and the display data read circuit 203 and supplied to the line buffer memory 100.

The line buffer memory 100 provided in the next stage performs a process of temporarily accumulating data for one line (one horizontal display period) and then reading the data in the next line. The circuit 203 is
It is not necessary to regularly and continuously read out in full synchronization with the display timing of the display means such as the final television. In other words, it means that there is a margin in the reading process. Therefore, the selection circuit 202 is set to give priority to the operation of the memory access circuit 201 over the operation of the display data read circuit 203 during the read margin period.

As a result, the working memory and data memory of the CPU can also be used as the display memory 30 so that the CPU can frequently access the display memory 30 for purposes other than display, and the display memory 30 is extremely efficient. It is possible to obtain the ripple effect that the CPU can be efficiently used and the CPU can also operate efficiently.

Although the embodiment of the display control circuit in the teletext receiving system has been described, the present invention is not limited to the above-mentioned embodiment, and the data broadcasting receiving system other than the teletext and the on-screen display control circuit, etc. It can also be applied to. Further, the display control circuit of the present invention can suppress the increase in the price of the system as described above by installing the display control circuit in the television receiver in addition to suppressing the increase in the price of the IC alone. .

[0021]

As described above, according to the present invention,
Even if the horizontal compression function is provided, the capacity of the line buffer memory is small, and the increase in system price can be suppressed. In addition, the operation of the system CPU can be made efficient, and the display memory Can be used efficiently.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional display control circuit for a character multiplex broadcast signal.

FIG. 3 is a diagram showing an operation concept of the RGB decoder of FIG.

[Explanation of symbols]

100 ... Line buffer memory, 200 ... Display memory control unit, 30 ... Display memory, 40 ... RGB decoder, 60
... color memory, 70 ... D / A converter.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 7/035

Claims (7)

[Claims] 1. A character multiplex signal for obtaining first display data composed of a dot pattern, a foreground color, a background color, and attribute data by decoding a character multiplex signal superimposed on a vertical blanking period of a video signal. In a display control circuit having a processing means and a memory means for holding data, the first display data is written in the memory means, and the first display data stored in the memory means is stored. Display memory control means for reading, compression means for compressing the first display data read out from the display memory control means in the horizontal direction on a time axis, and first display data compressed by the compression means. A display control circuit comprising: an RGB decoder for decoding display data of No. 2. 2. The display control circuit according to claim 1, wherein the second display data comprises a color data signal, a television / character switching signal and a television halftone signal. 3. The color data signals are R (red) and G.
2. A (green) or B (blue) signal.
Display control circuit described. 4. The display memory control means for operating at least the memory access means for writing the first display data to the memory means, and for reading the display data stored in the memory means. It has display data reading means and selection means for deciding the priority of the operations of the memory access means and the display data reading means, and the selection means gives priority to the memory access means accessing the memory means. The display control circuit according to claim 1, wherein: 5. The display control circuit according to claim 3, wherein the control unit of the character multiplex signal processing unit also writes / reads data other than the first display data to / from the memory unit. . 6. The output of the RGB decoder is input to color memory means for outputting third display data composed of R, G, B signals of at least 2 bits, and the output of this color memory means is further input. The display control circuit according to claim 1, wherein the display control circuit is input to a digital-analog conversion means. 7. The display control circuit according to any one of claims 1 to 6, which is included in a television receiver.