JPH08242218A - Time diversity communication method and its equipment - Google Patents

Abstract

PURPOSE: To prevent the generation of data omission and incorrect data by judging the validity of decoded data and executing time diversity operation. CONSTITUTION: A transmitting side encodes an interlaced signal obtained by interlacing an n-bit delay signal string in a signal string with an input digital signal string and transmits the interlaced signal to a transmission line. A receiving side separates a delay signal and a no-delay signal from decoded data decoded by a transmission line decoder through a shift register 20 and phase convertes 24, 25 and selects and outputs a valid signal by a selector 33. A combination judging circuit 28 judges the degree of coincidence between a valid gate signal expressing the validity/invalidity of the decoded data and the separated signal and controls the switching of the selector 3 and the synchronism of the separated signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time diversity communication method, and more particularly, to a diversity communication method used for improving transmission characteristics in digital mobile communication in which data sequences are lost or erroneous due to shadowing or other causes. And its equipment.

[0002]

2. Description of the Related Art A diversity communication system sets a plurality of communication paths in which variations in received signal levels have low correlation with each other.
This is a communication system that improves transmission characteristics by selecting or combining these outputs. An example of a conventional time diversity communication system is described in Japanese Patent Publication No. 63-37540. FIG. 4 is an outline of a conventional time diversity communication system. FIG. 7 is a diagram showing time allocation of transmission / reception signals. Let the data series 90 be {a _i } (
_i is an integer), and the output data series 91 of the encoder 41 is {b
_{j} (j} is an integer) is expressed as {c _i} a received data sequence 92 outputted from the receiver. {A _i } is a data series having a clock frequency fo, and the clock frequency of {b _j } is 2 fo. {A _i } is encoded into {b _j } as follows. The data {a _i } input at that time is directly assigned to the even time slots {b _2j } of {b _j }. That is, b _2i = a _i . On the other hand, n-bit delay data {a _in } is assigned to the odd time slot {b _2i-1 } of {b _j }. That is, b _2i-1 = a _in . As described above, a ₁ is assigned and inserted in two time slots with an n-bit interval of b ₂ and b _{2n + 1} , and b
_{A n} and a _{n + 1} are respectively allocated to both sides of _{2n + 1} , b _2n and b _{2n + 2} , and data without delay and data with delay are alternately transmitted (hereinafter referred to as “interlaced signal”). . Figure 5
Is a configuration example of the encoder 41. The transmission data {a _i } input from the input terminal 60 is the same as the data that has passed through the n-bit shift register 61 and the data as it is.
Input to 2. The shift register 61 is shifted at the clock frequency fo, the selector 62 sequentially switches the input signal at 2fo, and is sent from the output terminal 64 as an interlaced signal {b _j }. In order to synchronize the transmission data and the high-speed clock, the clock frequency 2fo input from the input terminal 65 is divided by 2 in the divide-by-2 circuit 63, and the transmission clock fo is output to the output terminal 66.
Here, a conventional example will be described with reference to FIG. Input terminal 40
The transmission signal input from is encoded by the encoder 41, is then subjected to modulation such as PSK by the modulator 42, and is transmitted to the power amplifier 4
It is amplified up to the required transmission power in 3 and transmitted from the transmission antenna 44. The radio waves received by the receiving antenna 45 are detected by the receiver 46 and are expanded by the expansion circuit 48 and the clock recovery circuit 4.
7 is input. The expansion circuit 48 extracts N pieces of data assigned to each time slot from the interlaced signal and outputs them to the combining circuit 49. The synthesis circuit 49
The synthesis control circuit 50 receives a synthesis coefficient corresponding to the reception level in each time slot, synthesizes two pieces of data, and outputs a synthesized signal. The synthesized signal is discriminated and discriminated by the discrimination and judgment circuit 51, and the demodulated signal is outputted to the output terminal 52.

FIG. 6 shows the expanding circuit 48 and the synthesizing circuit 4 of FIG.
9 is a configuration example of the synthesis control circuit 50. The reception level signal indicating the reception level input from the receiver 46 to the input terminal 79 is combined into two reception level signals corresponding to the interlaced signal by the delay circuit 76 having a delay time corresponding to n bits of data. Control signal generation circuit 75
Add to. The synthesizing control signal generating circuit obtains a synthesizing coefficient according to the reception level according to a predetermined algorithm, and outputs it as a synthesizing control signal 81 to the synthesizing circuit 49.
On the other hand, the receiver detection output is input from the reception signal input terminal 78, and the signal and the signal delayed via the n-bit shift register 71 have a combination detection circuit 72 having two input terminals.
And a combining circuit 49. The combination detection circuit 72 detects the correct combination of the even and odd time slot combinations, generates a reset signal indicating this timing, and outputs to the divide-by-2 circuit 74 that divides the reproduced clock 2fo into 1/2. Output. The divide-by-2 circuit 74 divides the reproduced clock 2fo input from the input terminal 70 into two by using this reset timing, and outputs the received clock 82 synchronized with the combined circuit output signal to the combined circuit 49 and the output terminal 77. At the receive clock timing, the synthesizer circuit
The two received signals are combined based on the combined control signal 81,
The synthesis circuit output signal 83 is output to the output terminal 80. As can be seen from the above description, the circuit of this figure synthesizes the signals interlaced in the two time slots according to the respective reception levels, so that the synthesized output signal has a code lower than that of any signal before the synthesis. You can expect to have an error rate.

[0004]

The above-mentioned time diversity communication system determines the reception state from the receiver based on the reception level, and utilizes the demodulation data of the higher reception level to synthesize the reception data. However, the correctness of the received data is not necessarily determined only by the reception level, and even if the data of the maximum reception level is selected, good communication cannot always be realized. Further, due to the interruption of the radio wave by an obstacle, etc., the clock synchronization of the clock recovery circuit is lost, and there is a problem in the stability of the subsequent processing of the decoded data until bit synchronization occurs and resynchronization occurs. Further, there is a problem that the decoded data may be lost until the receiving device returns from the asynchronous state to the synchronous state.

The present invention enables highly reliable diversity communication in which the correct data of the data with delay and the data without delay separated from the interlaced signal can be selectively output by constantly judging and monitoring the validity of the received decoded data. It is an object of the present invention to provide a time diversity communication method and apparatus therefor.

Further, the present invention is a time diversity communication method in which a synchronization state is monitored by a coincidence rate of the data separated from an interlaced signal, the synchronization state is quickly pulled in at the time of non-synchronization, and a loss of synchronization is always monitored even in the synchronization state. And an apparatus thereof.

Further, according to the present invention, it is possible to absorb a momentary interruption of radio waves due to shadowing or the like, and even if clock synchronization is lost and a bit deviation occurs due to other causes, and even if there is a momentary interruption of data or illegal data. It is an object of the present invention to provide a time diversity communication method and an apparatus therefor, which are less likely to cause a loss in decoded data and can prevent generation of illegal data before switching to correct data.

[0008]

In order to achieve the above object, according to the time diversity communication method of the present invention, an input digital signal is interlaced with a current digital signal and a past digital signal in an N-bit string in units of n bits on the transmission side. The interlaced digital signal demodulated at N times the speed and transmitted and demodulated on the receiving side determines the validity of the bit string in m (m <n) bit units,
It is characterized in that a valid bit is selected based on the determination result, the speed is converted to 1 / N, and a reception digital signal is output. Then, in order to judge the effectiveness, a redundant bit for error correction processing is added in units of m bits of the interlaced digital signal.

The present invention also provides, as a time diversity receiving apparatus, a decoding means for outputting a decoded bit string and a valid / invalid judgment signal of the bit string from a received demodulated signal, a first delay means for delaying the decoded bit string, and First and second phase converters for separating an interlaced digital signal from a decoded bit string and an output bit string of delay means, selector means for selectively outputting the outputs of the first and second phase converters, and the valid / invalid signal It is characterized by comprising a second delay means for delaying the input signal and a judging means for controlling the switching of the selector means according to the input and output states of the second delay means.

Further, according to the present invention, first and second buffers are provided between the demodulation means and the first and second delay means, respectively.
And a first and second variable delay means that receives the output of the buffer as an input, and the determination circuit is configured such that when the input and output of the second delay means are valid determination signals, Detects the degree of coincidence between the output and the output of the second phase converter,
It is characterized by comprising a control circuit for adjusting the output phases of the first and second phase converters and / or the first and second variable delay means based on the degree of coincidence.

[0011]

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the time diversity communication system of the present invention. As the time allocation of the transmission / reception signal in the present invention, the same one as the conventional example will be described as an example. That is, for transmission encoding, as shown in FIG. 7, the input data sequence 90 is {a _i } ( _i is an integer), the output data sequence 91 of the encoder 41 is {b _j } ( _j is an integer), and the receiving device is {C _i } of the data sequence 92 output from the above is represented as {a _i }, and the clock frequency of {b _i } is 2 fo. In the even time slots {b _2j } of {b _j }, the data {a
_i } is directly assigned. That is, b _2i = a _i .
On the other hand, in the odd time slots {b _2i-1 } of {b _j }, n
Bit delay data {a _in } is assigned. That is, b
Let _2i-1 = a _in . As described above, a ₁ is b ₂ and b
Assigned to _{2n + 1} timeslots, both sides of b _{2n + 1} b
_2n and b _{2n + 2} are assigned a _n and a _{n + 1} , respectively, and data without delay and with delay are alternately transmitted. The configuration of the encoder 41 for such encoding can be the one shown in FIG.

First, an input terminal 1 shown in FIG. 1 which is an embodiment of the present invention and which describes the operation of the transmitting side is shown.
The transmission signal input from 0 is encoded by the encoder 41 and then input to the transmission line encoder 11. Transmission line encoder 11
In FIG. 8, the interlaced signal {b _j } is divided into m bits, and k redundant bits {P _i } are added to each m bits as shown in FIG. The output of the transmission line encoder 11 is modulated by PSK or the like by the modulator 12, amplified by the power amplifier 43 to the required transmission power, and sent out from the transmission antenna 44.

Next, the structure and operation of the receiving side will be described. In FIG. 1, the modulated wave received by the receiving antenna 45 is amplified by the low noise amplifier 13 and demodulated by the demodulator 14. The demodulated data is decoded by the transmission path decoder 15.
The transmission path decoder 15 reproduces the reception clock 2fo, performs error correction on the demodulated data using the redundant bits and outputs the decoded data, and in the error correction process, as shown in FIG. Then, a valid / invalid determination signal (hereinafter referred to as a valid gate signal) that determines whether the data is correct data is output. The two buffers 16 and 17 respectively store the decoded data and the valid gate signal at the reception / reproduction clock 2fo, and read at the reception clock of the oscillation frequency 2fo ′ of the oscillator 22 asynchronous with the reception / reproduction clock, and each of the variable shift registers. Output to 18 and 19. Buffers 16 and 17
Plays an elastic memory function. The variable shift registers 18 and 19 are shift registers that receive the data from the buffers 16 and 17 and give a delay of up to α bits to the data. It has the function of absorbing and stabilizing the bit shift operation. In addition, the variable shift register 1
Reference numerals 8 and 19 have a configuration and a function capable of sequentially switching the output from the output of the final stage to the output of the previous stage by a shift signal from the combination determination circuit 18. For example, it has a function capable of skipping and outputting subsequent data. Then, the variable shift register 18 includes the buffer 1
The data from 6 is input, delayed and the output is branched into two and sent to the phase converter 25 and the shift register 20. Also,
The variable shift register 19 receives the valid gate signal from the buffer 17, delays the valid gate signal, and sends it to the shift register 21 in the subsequent stage, and has the same configuration and function as the variable shift register 18.

The phase converter 25 has a reception clock 2f as shown in FIG.
The one-branch output of the variable shift register 18 is input at a clock fo ′ having a frequency of ½ of o ′, and only one of the adjacent data with or without the delay of the interlace signal (odd or even) is output. Which of the above data is selected by the phase converter 25 is controlled by the shift signal from the combination judging circuit 28, and the output thereof is sent to the shift register 31 and the combination judging circuit 28. In the example of the figure, the input data is latched by the D-type flip-flip, and every other bit of the input data {b _j } is latched and output. The polarity of the clock signal fo ′ of the D-type flip-flop is inverted by the EX-OR circuit according to the logical state “1” or “0” of the shift signal, so that the output data is an odd number or an even number of the received data according to the shift signal. Is output.

Next, the shift register 20 is a shift register having a delay amount of 2n bits which is shifted by the reception clock 2fo ', and gives a delay of 2n bits to one branch output of the variable shift register 18. Shift register 20
In this case, 2n-bit data of the interlaced signal is always stored in. Similarly, the shift register 21 outputs the output of the variable shift register 19 to the reception clock 2f.
It is a shift register having a delay amount of 2n bits which is shifted by o ′, and delays the effective gate signal by 2n bits.

The phase converter 24 has the same structure and function of FIG. 2 as the phase converter 25. That is, the output is either odd or even data of the output data of the shift register 20 according to the shift signal, and the received data is sent to the shift register 30 and the combination determination circuit 28.

The shift registers 30 and 31 provide a β-bit delay to the data. The output data of the phase converters 24 and 25 are input by the reception clock fo ′, and the selector 33 inputs the output data to the selector 33. "A" and "b", which are data without delay and data with delay, are delayed and transmitted. The selector 33 includes a shift register 30,
Switching is performed so as to select one of the outputs “a” and “b” of 31 and the signal string {c of 92 of FIG. 7 is output terminal 34.
_The restored demodulated output data such as _i } is transmitted.

In the above configuration, the output data "a" of the phase converter 24 and the output data "b" of the phase converter 25.
(This set of bits is written as (a, b)) has a delay time difference (in fo'clock) of n bits from each other.
The decoded data is correctly obtained, and the two data without delay and with delay of the interlaced signal are transferred to the phase converters 24 and 2.
In the operation phase (synchronous state) in which 5 correctly latches, both data should be exactly the same. Further, the output data “a” of the phase converter 24 and the output data “b” of the phase converter 25 are respectively the output “of the shift register 21”.
c "corresponds to the effective gate signal" d "of the output of the variable shift register 19 (the set of bits is written as (c, d)), and the" c "and" d "are the above" a "and" b ". "Effective
Indicates invalid. This is because whether the decoded bit "a" is correct is indicated by "c", and whether the decoded bit "b" is correct is indicated by "d". The reason why there is no phase converter on the effective gate signal side is that the effective gate signal changes in units of m bits, so that a shift of several bits can be ignored.

By the way, when the receiving device is in the above-mentioned synchronized state, the data "a" and the data "b" are the same data, and the data "a" is (fo 'clock) when viewed from the data "b". The same data n bits before,
The n−1 pieces of data subsequent to the data “a” are stored in the shift register 20. From this, in the synchronized state, the selector 33 is caused to selectively output the signal of the data “b” output through the shift register 31, and the instantaneous interruption of the data due to shadowing or the like occurs and the data “b” is abnormal. When it occurs, the abnormality is judged by the valid gate signal "d" and the selector is switched to output the normal signal "a" on the same data side. When the valid gate signal "d" detects that the data "b" has returned to normal, the data "b" is returned.
The signal is switched to the signal on the b ″ side. Here, the shift register 2
For 0, it is desirable to set the bit number 2n of the shift register 20 sufficiently large so that the data "b" returns to normal before the 2n-bit data accumulated at this time is completely output. Also, the phase converter and shift register 1 are set so that the first synchronization state is obtained when the data is normalized.
Operate 8 and 19 to adjust.

As described above, the valid gate signals (c, d) are always monitored in the synchronous state, and when one of them becomes invalid, the selector 33 selects the data "a" or "b" on the valid gate signal side. Select and output the data to prevent data loss due to shadowing. The present invention realizes time diversity based on such a principle.

The combination determining circuit 28 performs control for this purpose, and a block diagram of a specific example thereof is shown in FIG.
The operation of the combination determination circuit 28 will be described below.

The combination determination circuit 28 includes a coincidence counter 6
1, a timer 62, a synchronization determination circuit 63, and a control circuit 64. Further, whether or not the decoded data is normal (valid / invalid) and whether or not the receiving device is in the synchronous state can be determined by the state of the valid gate signal (c, d) and the degree of coincidence of the data (a, b). Therefore, with these as inputs, the shift signals of the phase converters 24 and 25, the variable shift register 18,
The shift signal for delay amount adjustment 19 and the selector signal for the selector 33 are output.

The determination of the synchronization state of the receiving device is performed by checking the coincidence of both data by the output of the EX-OR circuit 61 (exclusive OR circuit) which inputs the data "a" and "b". The control circuit 64 periodically generates a synchronization determination start pulse and starts the timer. At the same time, the coincidence counter 61 counts the number of coincidences of the data "a" and "b". When the timer 62 outputs a count end pulse after a fixed time, the coincidence counter 61 outputs the coincidence count value (count value) at that time to the synchronization determination circuit 63. The synchronization determination circuit 63 sets a predetermined numerical value, compares the coincidence number value with the numerical value, determines that the coincidence state is equal to or more than the set numerical value, and sends a synchronization signal to the control circuit. Further, the synchronization determination circuit 63 can change the set numerical value depending on whether the receiving device detects the asynchronous state from the synchronous state or the asynchronous state from the asynchronous state. The value to be detected is higher and the condition is stricter. (Hereinafter, the setting value when determining synchronization from asynchronous is “condition 1”, the setting value when determining asynchronous from synchronization is “condition 2”. And).

The control circuit 64 constantly monitors whether the data "a" and "b" are valid or invalid based on the state of the valid gate signals (c, d).
The operation of the selector 33 is controlled, and the switching of the selector 33 is controlled. The control circuit 64 uses the effective gate signal "c".
When = “invalid” is input, the determination operation of the synchronization determination circuit 63 is stopped regardless of whether the valid gate signal “d” is valid or invalid. When (c, d) = (valid, valid), the synchronization determination circuit 63 performs the synchronization determination operation to determine the degree of coincidence between the data “a” and “b”, and when asynchronous, the phase converter and variable It controls the shift of the shift register and pulls it into the synchronous state.

In the following, (1) when changing from an asynchronous state such as an initial state when the receiving device is started or a state after long-term shadowing to a synchronous state (in the case of "asynchronous-synchronous")
And (2) when the receiving device is in a short-term data loss state due to shadowing or the like during normal operation and changes from the asynchronous state to the synchronous state (in the case of "synchronous-asynchronous-synchronous")
The operation of the combination determination circuit 28 will be described separately.

(1) In the case of "asynchronous-synchronous".

In a case such as when the apparatus is started up or after a long shadowing, the variable shift register 18, the shift register 20, and the phase converters 24 and 25 are not filled with the correct data sequence, so that the combination determination circuit is used. 28 sets the selector so that the output of the shift register 31 is sent to the output terminal 34 for the time being. The same applies to the variable shift register 19 and the shift register 21 to which the valid gate signal is input, and the control circuit 64 stops the determination operation of the synchronization determination circuit 63 until (c, d) = (valid, valid). Let When (c, d) = (valid, valid), the control circuit 64 causes the synchronization determination circuit 63 to start the synchronization determination operation. When the result of the synchronization determination is asynchronous, the latch timing of the phase converters 24 and 25 is toggled for each synchronization determination in the same direction (around 1 bit for each asynchronous determination) to wait for synchronization. . In this case, condition 1 is used to determine the synchronization by checking the degree of coincidence of the data strings (a, b). Eventually, the decoded data will become normal, and the phase converters 24 and 25 will latch the input data at the timing when the input and output of the shift register 20 become the same data without delay and with delay, and the synchronization state will be entered. Once synchronization has been established, condition 2 is used to continue monitoring the degree of coincidence to see if it is asynchronous. During the operation described above, the combination determination circuit 28 selects the selector 33 so that the output of the shift register 31 is sent to the output terminal 34, and normal data is output as soon as possible in the synchronized state.

(2) In the case of "synchronous-asynchronous-synchronous".

While the combination judging circuit 28 judges that the data is synchronous, as described above, the output data of the shift register 31
The selector 33 operates so that b ″ is sent to the output terminal 34, and in this state, the synchronization determination circuit 63
Monitors whether it becomes asynchronous according to the condition 2. Here, if data loss or the like occurs due to shadowing or the like, it is determined to be asynchronous after a fixed time (after β bit period), and a signal indicating the asynchronous is sent to the control circuit 64, and the control circuit 64 outputs the selector signal. Is output, and selector 3
3 is the normal signal “a” from the shift register 30
Switch to. At the same time, the control circuit 64 counts the number of bits (clock number) of data (the signal "a" or the output of the shift register 20) by a built-in counter until the synchronization state is reached (the count number of the counter is the signal "a").
It depends on whether it is the output of the shift register 20 or the clock fo'or 2fo ', but will be described below by counting the clock 2fo'). Here, the shift registers 30, 3
The role of 1 is to prevent the random data from being output from the selector 33 until it is determined to be asynchronous according to the condition 2 (the period corresponding to β bits of the fo ′ clock described later).

The control circuit 64 stops the determination operation of the synchronization determination circuit 63 until (c, d) = (valid, valid), that is, the received data becomes valid, and (c, d) = (valid, valid). Then, the judgment operation is started. Control circuit 64
Is the synchronization determination circuit 6 for each measurement section (for each timer measurement period).
3. Check the sync signal from 3 and if it is asynchronous, phase converter 25
It is considered that the data of (1) has a phase shift, a shift signal is sent to the phase converter 25 to shift the latch timing, the data of "b" is changed, and a start pulse is sent to a timer etc. again for synchronization determination. To do. Then, when it is determined that the variable shift register 18 is asynchronous,
A shift signal is sent to 19 to change the data "b" and the effective gate signal (variable shift registers 18, 1
9 of the subsequent output data and the valid gate signal are skipped to the subsequent signals), and the synchronization determination is continued. The operations of the phase converter 25 and the shift registers 18 and 19 are sequentially repeated until they are synchronized.

If it is confirmed that synchronization is established at the 1st bit (n> l) by the synchronization signal from the synchronization determination circuit 63 after the built-in counter starts counting, the shift register 20 in the shift register 20 at this time is confirmed. The data status is shown in Fig. 10.
become that way. In the figure, the 2β bits from the right side of the shift register correspond to the time required for synchronization detection, and the central 2
The β bit corresponds to the time required for asynchronous detection (these detection periods often have different values depending on the settings of the conditions 1 and 2 for synchronous or asynchronous detection, etc. For convenience, they are assumed to be equal to each other and are set to 2β. It is desirable that the number of stages of the shift registers 30 and 31 is set to about β. After such a synchronization state is detected, the shift register 20 previously input and determined to be valid
While the data (2n−1−2β) bits on the output side of (1) are output, the synchronization determination circuit 63 continues to monitor under condition 2 whether or not it is asynchronous.

Then, during (2n-1-2β) bits,
If the synchronization is maintained, during the next (2β + 1) bits,
The operation of the synchronization determination circuit 63 is stopped. To stop the operation of the synchronization determination circuit 63, the error register (2β + 1) bits input during the synchronization-asynchronous-synchronization are output from the shift register 20 after the bit sequence of about (2n−1−2β). Therefore, during this period, the synchronization determination circuit 63 is stopped,
It is intended to keep it in sync. In addition, (2
After β + 1 bits, the correct data is the shift register 20
However, since there may be a phase shift in the (a, b) sequence at this time, the synchronization determination circuit 63 forcibly determines that it is asynchronous, and (c, d) = (valid, Confirm that it is valid) and perform synchronization establishment operation. That is,
The synchronization judgment circuit 63 sends an asynchronous signal to the phase converter 24.
Is shifted and the condition 1 is used to check the degree of coincidence of the data strings (a, b) to perform synchronization determination. Usually, since the synchronization is established again with the correct data, the condition 2 is used to continue monitoring after that whether or not it is not synchronized. After the first synchronization is established (with the fo'clock), the β-bit period is β
Since there is a possibility that an error bit remains in the shift register 31 having a bit delay amount, if the synchronization is maintained even after β bits have passed, the selector of the shift register 31 outputs the output from the output terminal 34. 33 is switched.

In the above operation, (2n
If the bit sequence of (1−2β) bits is not synchronized, this occurs when the bit sequence of (2n−1−2β) is not filled with the correct data, and thus it is like an initial operation of the receiving device. The operation of “asynchronous-synchronous” in (1) above is performed. In addition, the operation of (1) is performed in the same manner when the synchronous counter becomes asynchronous and the asynchronous counter value of the built-in counter cannot be resynchronized even after 2n.

The operation of the selector 33 when the valid gate signal is invalid while the synchronization is maintained during the above operation is as follows: (c, d) = (valid, invalid) , (At fo'clock) after β bits, the selector 33 is switched so that the output of the shift register 30 is sent to the output terminal 34. Also, (c, d)
In the case of = (invalid, valid), similarly, the selector is switched so that the output of the shift register 31 is sent to the output terminal 34 by the time after β bits.

In the selector 33, the shift register 3
The one where the output of 0 is input is the "A side", the shift register 3
The one to which the output of 1 is input is the "B side", and the control circuit 64
FIG. 11 shows a flow of the switching operation by the.

The time diversity communication method of the present invention has been described with reference to the embodiments of the two interlaced signals with and without the delay of the input digital signal, but the present invention is applied to three or more interlaced signals of the input digital signal. It goes without saying that the invention can be applied. In this case, in the receiving device, a delay means for separating and extracting the input digital signal from the interlaced signal and a delay means for the effective gate signal are added, and a selector having a corresponding structure is provided and a combination determination circuit based on the effective gate signal is provided. To switch. In the synchronization operation, the combination determination circuit determines the synchronization states of adjacent signals of a plurality of input digital signals that are sequentially delayed, and when asynchronous, prioritizes the synchronization based on the synchronization state of a specific signal set. Based on the setting of the order, the phase may be adjusted as described above and synchronized.

Further, in the above-described embodiment of the present invention, the synchronous operation of the receiving device is combined with the shift of the variable shift register, and a structure for always promptly returning to the synchronous state is adopted. Phase converter 2 by
It is also possible to synchronize by only 4 and 25 shifts (one and both shifts).
It is also possible to adopt a configuration in which 8 and 19 are omitted.

Further, in the above-described embodiment of the present invention, the receiving device is provided with the shift registers 30 and 31 to prevent the generation of the illegal data due to the delay of the switching of the selector, but the generation of the slight illegal data is prevented. It is possible to implement the present invention with a configuration in which it is allowable or the selector switching timing is tightened or the like is omitted.

[0039]

As described above, according to the time diversity communication method and the apparatus thereof of the present invention, it is generated based on the error rate of the data of the received decoded data or the status of the error correction process, not the state of the reception level. The effective gate signal determines whether the decoded data is valid or invalid, and performs time diversity by monitoring the data, so that data with no code error can always be selected and output, and highly reliable diversity communication can be realized. . Further, according to the present invention, when data is valid, it is possible to promptly pull in to a synchronized state, and also to provide a time diversity communication method and apparatus for constantly monitoring loss of synchronization even in the synchronized state. be able to. Further, according to the present invention, by providing the buffer, the variable delay means, and the third and fourth delay means on the output side, the reception clock is out of synchronization due to momentary interruption of radio waves due to shadowing or the like, and other causes. Even if a shift occurs, it can be absorbed, and even if there is a momentary break in the decoded data or an illegal data, there is little loss of the decoded data, and further, it is possible to prevent the generation of illegal data when switching to the correct data. A time diversity communication method and apparatus can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration and an operation time chart of a phase converter.

FIG. 3 is a block diagram showing a configuration of a combination determination circuit.

FIG. 4 is a block diagram showing a configuration of a conventional diversity communication system.

FIG. 5 is a block diagram showing a configuration of an encoder.

FIG. 6 is a block diagram showing configurations of an expansion circuit, a synthesis control circuit, and a synthesis circuit.

FIG. 7 is a diagram showing a configuration of time allocation of transmission / reception signals.

FIG. 8 is a diagram showing a structure of a transmission encoded data string.

FIG. 9 is a diagram showing an effective gate signal corresponding to a decoded data string.

10 is a diagram showing a data string in the shift register 20. FIG.

FIG. 11 is a diagram showing a selector switching operation.

[Explanation of symbols]

 10 Input Terminals 11 Channel Encoder 12 Modulator 13 Low Noise Amplifier 14 Demodulator 15 Channel Encoder 16, 17 Buffer 18, 19 Variable Shift Register 20, 21 Shift Register 22 Oscillator 23 2 Frequency Divider 24, 25 Phase Converter 28 combination determination circuit 30, 31 shift register 33 selector 34 output terminal 35 D-type flip-flop 36, 60 exclusive OR (EX-OR) 61 coincidence counter 62 timer 63 synchronization determination circuit 64 control circuit

Claims (9)

[Claims] 1. An n-th digital input signal is transmitted on the transmitting side.
The present digital signal and the past digital signal are interlaced in bit units by N bits and the speed is converted to N times for transmission, and the demodulated interlaced digital signal is transmitted in m (m <n) bit units on the receiving side. A time diversity communication method characterized by judging validity, selecting a valid bit based on the judgment result, converting the speed to 1 / N and outputting a received digital signal. 2. The input digital signal is transmitted to the transmitting side by n.
The present digital signal and the past digital signal are interlaced in a unit of 2 bits in a bit unit and the speed is converted to double to be transmitted, and the demodulated interlaced digital signal is transmitted in m (m <n) bit units in a bit unit. A time diversity communication method characterized in that the validity is judged, a valid bit is selected based on the judgment result, the speed is converted to ½, and a reception digital signal is output. 3. The time diversity communication method according to claim 1, wherein a redundant bit is added to the interlaced digital signal on a transmitting side in units of m bits, and the receiving side uses the redundant bit to perform the interlaced digital signal. A time diversity communication method characterized by determining the validity of a signal. 4. A decoding means for outputting a decoded bit string and a valid / invalid judgment signal of the bit string from a received demodulated signal, a first delay means for delaying the decoded bit string, and a bit string output from the decoded bit string and the delay means. First and second phase converters for separating the interlaced digital signals from the first and second selectors, selector means for selectively outputting the outputs of the first and second phase converters, and a second delay for delaying the valid / invalid signals. A time diversity receiving apparatus comprising: means and a determining means for controlling switching of the selector means according to the input and output states of the second delay means. 5. The time diversity receiving apparatus according to claim 4, wherein the determination circuit outputs the output of the first phase converter and the second transfer when the input and output signals of the second delay means are valid. A time diversity receiving apparatus, comprising: a control circuit that detects a degree of coincidence between outputs of the converters and adjusts output phases of the first and second phase converters based on the degree of coincidence. 6. The time diversity receiving device according to claim 4, wherein a first buffer, a second buffer, and the first and second buffers are provided between the demodulation means and the first and second delay means, respectively. A time diversity receiving apparatus comprising first and second variable delay means for receiving respective outputs of the above. 7. The time diversity receiving device according to claim 6, wherein said decision circuit outputs the output of the first phase converter and the second signal when the input and output signals of said second delay means are valid. And a control circuit for detecting the degree of coincidence of the outputs of the phase converters and adjusting the output phases of the first and second phase converters and the first and second variable delay means based on the degree of coincidence. A time diversity receiver characterized by: 8. The time diversity receiver according to claim 4, 5, 6 or 7, further comprising third and fourth delay means between the first and second phase converters and the selector means. A time diversity receiver characterized by the above. 9. The first, second, third and fourth delay means and the first and second variable delay means are respectively composed of shift registers, and the first and second delay means and the first and second delay means. A clock having a frequency substantially equal to the received clock frequency is supplied to the two variable delay means, and the third and fourth delay means and the first and second phase converters have approximately 1/2 of the received clock frequency.
A time diversity receiver characterized by being supplied with a frequency clock.