JPH08235875A - Multilevel information storage device and operating method thereof - Google Patents

Abstract

(57) Abstract: Multi-valued information is recorded by using one program element, that is, a switching element. The present invention provides a mask ROM for recording multi-valued information, for example, a multi-valued ROM in which a plurality of information is written, that is, a mask ROM for recording multi-valued information with a time axis taken into consideration, by utilizing the difference in time delay. Memory cell transistor T
The multi-valued information can be reproduced on the time axis by changing the delay amount of the signal by changing the resistance value connected to the gates of T2 and T3 to a resistance having values of R and R + R.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information storage device, and more particularly to a multilevel information storage device and its operating method.

[0002]

2. Description of the Related Art A semiconductor memory device as an information memory device,
For example, there is a mask ROM. This mask ROM writes information to memory cell transistors in a mask process,
It is a ROM that fixes information of "1" or "0", that is, a read-only memory. FIG. 9 is a circuit diagram showing a part of a conventional mask ROM constructed using MOS type memory cell transistors. In FIG. 9, Q
1 and Q2 are MOS type memory transistors, and the gate electrodes of these transistors Q1 and Q2 are word lines W respectively.
It is connected to L1 and WL2. The drain electrodes of the transistors Q1 and Q2 are connected to the input terminal of the sense amplifier SA connected to the Vcc power supply via the bit line BL1, and the source electrodes are grounded. Depending on the nature of the MOS transistor, whether it is an enhancement type or whether it is a depletion type by ion implantation to change the threshold value, it corresponds to data "1" and "0". With this configuration, the transistor Q1 is held at "0" and the transistor Q2 is held at "1", and its output is taken out from the sense amplifier SA.

The memory cell thus formed can write only one piece of information "0" or "1", and the number of memory cell transistors is required to correspond to the storage capacity of the mask ROM. Here, multiple information is stored in one memory cell,
If so-called multivalued information can be written, the mask R
The storage capacity of the OM can be dramatically increased.

[0004]

In a normal mask ROM, one MOS transistor can store only a value of "1" or "0". That is, only one piece of information can be obtained for each memory cell.

An object of the present invention is to provide a multilevel information storage device and an operating method thereof capable of obtaining a plurality of information from a single memory cell, in order to solve the above problems.

[0006]

The storage element of the present invention comprises:
At least one switching element, and a delay element for controlling switching of the switching element with a delay time selectively connected to a switching control terminal of the switching element, according to the content of the multivalued information,
It is characterized in that multivalued information is stored on the time axis.

The multilevel information storage device of the present invention controls switching of the switching element with at least one switching element and a switching time which is selectively connected to the switching control terminal of the switching element and has a delay time according to the content of the multilevel information. And a means for sequentially reading multi-valued information from the switching element along a time axis according to a read signal supplied to the delay element. A semiconductor memory device according to the present invention includes a plurality of memory cell transistors formed on a semiconductor substrate and memory cell transistors each having a delay time connected to a switching control terminal of each memory cell transistor and having a delay time corresponding to the contents of multi-valued information. A plurality of delay elements for controlling switching, and means for sequentially reading multi-valued information from the memory cell transistor along a time axis according to a read signal supplied to the delay element. To do.

In the semiconductor memory device of the present invention, a plurality of memory cell transistors formed on a semiconductor substrate and a switching control terminal of each of the memory cell transistors are selectively connected to a delay corresponding to the contents of multi-valued information. A plurality of delay elements for controlling the switching of the memory cell transistor with time, and means for sequentially reading multi-valued information from the memory cell transistor along a time axis according to a read signal supplied to the delay element. It is characterized by having.

In the semiconductor memory device of the present invention, a plurality of memory cell transistors formed on a semiconductor substrate and a switching control terminal of each memory cell transistor are selectively connected to a delay corresponding to the contents of multi-valued information. A plurality of delay elements for controlling the switching of the memory cell transistor with time, a plurality of word lines for supplying a read signal to the switching control terminal of each memory cell transistor via the delay element, and the delay It is characterized by further comprising means for sequentially reading out signals output from the memory cell transistors as serial multi-valued information at a predetermined timing along a time axis in accordance with a read signal supplied to the element. According to the method of operating a multi-valued information storage device of the present invention, a control signal supplied to a switching control terminal of a switching element is delayed by a time that is an integral multiple of a read clock, and a signal appearing at an output terminal of the switching element is read out. It is characterized in that multi-valued information serially arranged on the time axis is read from the switching element by serially taking out in synchronization with a clock.

According to the multilevel information storage device of the present invention, the control signal supplied to the switching control terminal of the switching element is delayed by the delay element for a predetermined time, and the signal appearing at the output terminal of the switching element is predetermined. It is possible to read multi-valued information serially arranged on the time axis from the switching element by reading out at the timing of and sequentially taking out serially.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a mask ROM according to an embodiment of the present invention.
3 is a circuit diagram showing a part of the memory cell of FIG. In FIG. 1, T1, T2, and T3 are transistors serving as memory cells for programming, and the transistors T1, T2, T3, and T4 are MOS type transistors, and their gate electrodes selectively have predetermined values. Word lines WL1, WL2, WL3, W through resistors
It is connected to L4. In the example of FIG. 1, the gate electrode of the transistor T1 is connected to the word line WL1 via a zero resistance, that is, directly to the word line WL1, the gate electrode of the transistor T2 is connected to the word line WL2 via a resistance R, and the gate electrode of the transistor T3. Is connected to the word line WL3 via resistors R1 and R2 connected in series, and the gate electrode of the transistor T4 is word-connected via the first, second and third resistors R1, R2 and R3 connected in series. Connected to line WL4. Here, the resistance values of the resistors R, R1, R2, and R3 are set to be equal. Transistors T1, T2, T3, T
The drain electrode, which is one of the four electrodes, is commonly connected to the bit line B.
It is connected to L1 and the other source electrode is grounded. The capacitors C connected in parallel to the respective resistors are stray capacitances (also referred to as stray capacitances or parasitic capacitances) formed when the resistors are formed on the semiconductor substrate. When considering the signal delay, it is necessary to consider the time constant due to the stray capacitance and the resistance, but here it is mainly treated as the delay due to the resistance.

The drain electrodes of the transistors T1 to T4 are commonly connected to the bit line BL1.
Is connected to the input terminal of a current amplification type sense amplifier SA. The power supply terminal of the sense amplifier SA is connected to the Vcc power supply, and the output terminal is connected to the input terminal of the counter 11. A clock signal described later is supplied to the counter 11.

Although only the transistors T1, T2, T3, and T4 as memory cells for programming are shown here, a large number of transistors as memory cells for programming are used according to the number of word lines and each gate is used. An electrode is selectively connected to a word line through a resistor having a predetermined value, and a drain electrode is commonly connected to a bit line BL1 to manufacture a mask ROM.

The operation of reading information from the multilevel information storage ROM having the configuration shown in FIG. 1 will be described below with reference to FIG.

The clock signal input terminal of the counter 11 is supplied with the clock signals P1, P2 and P3 shown in FIG. Here, as shown in FIG. 2B, when the address signal A synchronized with the three clocks P1 to P3 is supplied to the selected word line WL1, the transistor T1
Is turned on, and the sense amplifier SA transfers to the counter 11 as shown in FIG.
The output B shown in (c) is supplied, and the counter 11 counts the three clock signals P1, P2, and P3 supplied while the output B is LOW as three serial "1" signals, and counts them. The value is "3". In this way, the transistor T1 can obtain a 3-bit serial output “111” or a multi-value output “3” according to the read clock.

Similarly, in the selected word line WL2, as shown in FIG.
When the address signal of (b) is given, this signal is delayed by the read-out resistor R by the amount of the read clock P1, and the signal shown in FIG.
It is supplied to the gate electrode of the transistor T2 to make it conductive at the timing shown in (d). Therefore, since the transistor T2 is non-conductive at the time of the read clock P1, the drain electrode of the transistor T2 is the bit line BL1.
It remains at the potential. Therefore, as the output signal of the transistor T2, a "0" signal is obtained from the sense amplifier SA to the counter 11 as shown in FIG. At this time, the clock signal P1 is not given to the counter 11 and is not counted.

Then, at the time of the reading clock P2,
The address signal A ′ delayed by the resistor R is transferred to the transistor T
Since it is supplied to the second gate electrode, it becomes conductive. Therefore, the LOW signal is obtained by the sense amplifier SA, and the counter 1
1 counts the clock signal P2. At the time of the subsequent read clock P3, the address signal A'is still applied continuously, and the transistor T2 is conductive. Therefore, the LOW signal is obtained in the sense amplifier SA, and the third clock P3 is supplied to the counter 11 Is counted by.
As a result, the read clock P is read from the transistor T2.
A 3-bit serial output “011” is obtained according to 1 to P3. At this time, the count value of the counter 11 is "2", and the multilevel output "2" is obtained.

When the read address signal A shown in FIG. 2B is applied to the word line WL3 in synchronization with the read clock P1 and the transistor T3 is selected, this signal is as shown in FIG. 2F. Further, the resistors R1 and R2 are delayed by two read clocks P1 and P2. Therefore, at the time of the read clocks P1 and P2, the transistor T3
Remains non-conductive, the drain electrode of the transistor T3 remains at the bit line BL1 potential. Therefore, the output signal of the transistor T3 is "0" as shown in FIG.
The 0 "signal is obtained by the sense amplifier SA. Then, at the time of the read clock P3, the address signal A" delayed by the resistors R1 and R2 is applied to the gate electrode of the transistor T3, so that the transistor T3 becomes conductive. Therefore, the LOW signal is obtained by the sense amplifier SA, and the counter 1
1 counts the third clock P3. As a result,
A 3-bit serial output "001" is obtained from the transistor T3 in response to the read clocks P1 to P3.

On the other hand, when the transistor T4 is selected and the address signal A of FIG. 2B is supplied to the word line WL4, this signal A is converted into three clock signals P1 to P3 by the resistors R1, R2 and R3. Delayed for a corresponding period,
Therefore, as shown in FIG. 2H, the address signal A ′ ″ is not applied to the gate electrode of the transistor T4 during the period of the clock signals P1 to P3, and remains non-conductive. Therefore, the clock count value of the counter 11 remains zero, and the clock count value of the counter 11 is 3 as shown in FIG. 2 (i) according to the read clocks P1 to P3.
A bit serial output "000" will be obtained.

Thus, the address signal via the word line is transmitted to the transistor with a delay from the reference time by a time determined by the time constant of the resistance due to the resistance connected to the base of the transistor, and the transistor is delayed by a predetermined time. Then, it outputs an output signal that tells that it is turned on.
Therefore, as shown in FIG. 2 (j), if the read valid period of the information corresponding to the three clock signals P1 to P3 is set, the enable signal, that is, the address signal is sent from the sense amplifier SA to the counter at a predetermined timing. By supplying the clock, serial multi-valued information having contents determined by the resistance value is obtained from the memory cell transistor.

As described above, in the embodiment shown in FIG. 1, when the resistors R, R1, R2, and R3 are formed of, for example, polysilicon silicide, the resistor layer itself and other adjacent conductors forming the resistor are formed. There is a stray capacitance c between and, and actually, the stray capacitance is transmitted to the memory cell transistor with a delay of a time determined by the CR time constant of the resistors R, R1, R2, R3 and the stray capacitance c.

The overall circuit configuration for reading serial multi-valued information from the mask ROM having the configuration shown in FIG. 1 is configured as shown in the block diagram of FIG. 3, for example. In FIG. 3, the memory access signal is supplied to the input buffer 21. The output signal of the input buffer 21 is supplied to the decoder 22 and decoded, and a predetermined word line, for example, WL2, that is, the memory cell T2 is selected.

On the other hand, the output signal of the input buffer 21 is supplied to the input terminal of the sense amplifier enable signal generating circuit 23. This sense amplifier enable signal generation circuit 23
Are read clock signals P1, P2, P synchronized with the address signal A for the memory cell T2, as described above.
, For generating 3, ... The generated clock signal is supplied to the detector 24. As a result, from the detector 24, the transistor T2 shown in FIG.
It is possible to read serial multi-valued information of 1 ".
3 is a circuit diagram showing an example of a sense amplifier enable signal generation circuit 23, in which a pulse signal from the input buffer 21 is input to an input terminal 31. This input terminal 31 has M
The gate of the OS transistor 32 is connected and one end of a CR delay circuit 36 having substantially the same time constant as that connected to the gate of the transistor T2 of FIG. 1 is connected. The other end of the CR delay circuit 36 is connected to the gate of the transistor 33 of the next stage, and is also connected to one end of a CR delay circuit 37 having substantially the same time constant as that connected to the gate of the transistor T2 of FIG. Connected. CR
The other end of the delay circuit 37 is connected to the gate of the transistor 34 in the next stage. The sources of the transistors 32, 33, 34 are connected from the output terminal 35 to the input terminal of the sense amplifier 24.

In the circuit thus constructed, when a pulse signal is supplied to the input terminal 31, the transistor 3
The output P1 is immediately obtained from 2. Then, the output P2 is obtained from the transistor 33 after a lapse of a predetermined time.
Further, after a lapse of a predetermined time, the output P from the transistor 34
3 is obtained. These outputs P1, P2, P3 are supplied to the sense amplifier 24 as the above-mentioned read clock.

5 (a), (b), (c), (d),
(E) is the read clock P1, P2, P of FIG.
3 shows the relationship between the input address signal and the output signal given to the transistors T1, T2 and T3, respectively. Here, in each of the transistors T1, T2, and T3, although there is a slight decrease in the generation period of the output signal due to the waveform distortion caused by the delay of the input, the sense amplifier enable signal generation circuit 23 is shown in FIGS. In the above example, since the transistors 32, 33, and 34 corresponding to the transistors T1, T2, and T3 in FIG. 1 are used, the reading from the detector 24 is sufficiently within the output period of each of the transistors T1, T2, and T3. However, the clocks P1, P2 and P3 are respectively provided.

FIG. 5A shows read clocks P1 and P.
2 shows the effective count range of the counter 11 corresponding to P3. In FIG. 5B, since the resistor is not connected to the gate electrode of the transistor T1, a 3-bit serial signal of “111” is obtained from the detector 24. Figure 5
Since one resistor R is connected in (c), a 3-bit serial signal “011” is obtained from the detector 24, and two resistors R + R are connected in FIG. A 3-bit serial signal of 001 ″ is obtained.
It goes without saying that one resistor having a resistance value of R + R may be used instead of the two resistors R + R.

As described above, in this embodiment, when the input signal and the output signal to the transistors T1, T2, T3 are respectively detected along the time axis and viewed, they are equally divided by the read clocks P1, P2, P3. This is an ON signal generated at a predetermined timing, and by recognizing the timing, multivalued information can be recorded and read by one resistor and one transistor having different sizes.

In the embodiment of FIG. 1, a resistor is selectively connected to the gate of the programmable transistor to obtain a desired delay amount, but the delay of the signal may be obtained by the electrostatic capacitance instead of the resistor. Good.

In the description of the embodiment shown in FIG. 1, the current detection type is used as the sense amplifier SA.
Since each of the word lines WL1 to WL4 can be addressed, a voltage detection type can be used as the sense amplifier SA to detect the voltage at the drain of each of the transistors T1 to T4.

Another embodiment of the present invention will be described below with reference to FIG.

In FIG. 6, parts corresponding to those of the embodiment of FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. Figure 6
In the second embodiment, the transistor T1 has no resistor or capacitive element connected to its gate, as in the first embodiment shown in FIG. The gate of the transistor T2 is connected to the word line WL2 via the delay circuit D including the resistor R and the capacitor C. The gate of the transistor T3 is connected to the word line WL2 through the delay circuit D1 including the resistor R1 and the capacitor C1 and the delay circuit D2 including the resistor R2 and the capacitor C2 in series. Transistors T1, T2, T
The drain electrodes of 3 are commonly connected to the sense amplifier S from the bit line.
It is connected to the A input terminal.

The relationship between the input and output of the gate electrodes of the transistors T1, T2 and T3 in the embodiment of FIG. 6 is as shown in FIG. 5 as in the embodiment of FIG. Figure 2
In the same manner as described above, for example, 3-bit multivalued information arranged on the time axis can be recorded and read.

Here, an example of the structure of the gate portion of each of the transistors T1, T2 and T3 in the embodiment of FIG. 1 will be described with reference to FIG. FIG. 7A is a plan view showing the gate portion of the transistor T1. The gate electrode 63 and the word line (not shown) are formed across the source and drain regions of the transistor T1 formed on the semiconductor substrate via the gate insulating film. A long strip-shaped silicide layer 64 is formed between and. For this silicide layer 64, for example, a long and narrow polysilicon layer 65 having a shape corresponding to that of the silicide layer 64 can be formed, and this can be formed as a silicide by using a metal such as tungsten. In this case, the entire resistance value can be made extremely small by forming the silicidation layer 64 long, and its equivalent circuit is substantially connected directly between the transistor T1 and the word line WL1 in FIG. Can be equal to doing.

FIG. 7B is a plan view showing the gate portion of the transistor T2 of FIG. 1. Since the length of the silicide layer 64A is shorter than that of the example of FIG. 7A, the resistance value R is obtained. To be As described above, the silicide layer 64A
Stray capacitance c is generated between the semiconductor layer and the polysilicon layer 65 including.

FIG. 7C is a plan view showing the gate portion of the transistor T3 shown in FIG. 1. Only the polysilicon layer 65 is used without using the silicide layer 64 used in the examples of FIGS. 7A and 7B. Since it is configured by using, a high resistance value R + R can be obtained. Of course, in the case of FIG. 7C, some silicide layers 64 may be used to obtain a resistance value twice the resistance value R in the case of FIG. 7B. As described above, the stray capacitance c is generated between the polysilicon layer 65 and the semiconductor substrate.

Further, in the embodiment shown in FIG. 6, the delay circuits D, D
In both 1 and D2, the main delay element is a capacitive element,
The resistors R, R1 and R2 are all capacitive elements C, C1 and C2.
It is formed as a resistance component of the electrode incidentally when the counter electrode forming the is formed on the substrate.

An example of the structure of the gate portions of the transistors T1, T2 and T3 of the embodiment shown in FIG. 6 will be described with reference to FIG.

FIG. 8A is a partial sectional structural view of the transistor T1 shown in FIG. 6, in which the gate G1 of the transistor T1 and the metal wiring formed as the word line WL1 are directly connected.

On the other hand, a trench H1 is formed in the interlayer film I1 under the metal wiring formed as the word line WL2 and connected to the gate of the transistor T2. The hole diameter of the trench H1 is adjusted by the mask diameter, and the high dielectric material B1 is filled in the trench H1 while being in contact with the word line WL2. By doing so, the value of the capacitive element C forming the delay circuit D connected to the gate of the transistor T2 in FIG. 6 can be adjusted.

Further, a larger trench H2 is formed in the interlayer film I2 below the metal wiring formed as the word line WL3 and connected to the gate of the transistor T3. The hole diameter of the trench H2 is adjusted by the mask diameter, and the high dielectric material B2 is filled in the trench H2 while being in contact with the word line WL3. By doing so, the capacitive element C1, which constitutes the delay circuits D1 and D2 connected to the gate of the transistor T3 in FIG.
The value of C2 can be adjusted. In FIG. 8C, the capacitive element C1,
Although the example in which C2 is collectively formed in the large trench H2 is shown, it goes without saying that two trenches may be formed and the capacitive elements C1 and C2 may be separately formed in each trench.

As described above, according to the above embodiment,
It is possible to record and read multi-valued information in the same manner as in the embodiment of FIG. 1 by obtaining the delay of the signal by the capacitance instead of the resistance.

In each of the embodiments described above, multi-valued information of 3 bits is recorded in one transistor. However, the delay amount of the delay circuit connected to the gate of the transistor is read out by three clocks. 4 for 4 minutes
It is possible to record and read multi-valued information of more bits such as bits and 5 bits in one transistor.

It is obvious that the present invention can be applied to various ROM circuits as well. Further, it goes without saying that various switching elements can be used instead of the programmable transistor.

[0045]

As described above in detail, according to the present invention,
By interposing a delay circuit including a resistor or an electrostatic capacitance in a signal circuit applied to the gate of a switching element, for example, a programmable transistor, paying attention to the delay in the timing of turning on the transistor, multivalued information is recorded in one transistor. Further, it is possible to provide a multi-valued information storage device capable of reading this and an operating method thereof.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 3 is a block configuration diagram of an entire circuit including an operation circuit of the embodiment of FIG.

FIG. 4 is a circuit diagram showing an example of a sense amplifier enable signal generation circuit shown in FIG.

5 is an input / output signal waveform diagram of the embodiment shown in FIG.

FIG. 6 is a circuit configuration diagram of another embodiment of the present invention.

FIG. 7 is a plan view showing a configuration of a main part of the embodiment of FIG.

FIG. 8 is a sectional structural view of a main part of the embodiment shown in FIG.

FIG. 9 is a circuit configuration diagram showing a part of a conventional mask ROM.

[Explanation of symbols]

T1, T2, T3, T4 ... Programmable transistor, WL1, WL2, WL3, WL4 ... Word line, BL1 ... Bit line, R, R1, R2, R3 ... Delay resistance, c ... Stray capacitance, SA ... Sense amplifier, 11 ... Counter, 21 ... Input buffer, 22 ... Decoder, 23 ... Sense amplifier enable signal generating circuit, 24 ... Detector, 36, 37 ... CR time constant generating circuit, P1, P2, P3 ... Read clock, D, D1, D2 ... delay circuit, 61 ... source, 62 ... drain, 63 ... gate poly, 64, 64A ... silicide layer, 65 ... polysilicon layer, G1, G2, G3 ... gate electrode, H1, H2 ... trench, B1, B2 ... high dielectric constant Material, Q1, Q2 ... Programmable transistor.

Continuation of front page (72) Inventor Atsushi Shigematsu 1-2-1, Marunouchi, Chiyoda-ku, Tokyo Nihon Steel Pipe Co., Ltd.

Claims (18)

[Claims] 1. At least one switching element, and a delay element which is selectively connected to a switching control terminal of the switching element and controls switching of the switching element with a delay time according to the content of the multivalued information. A storage element comprising, and storing multivalued information on a time axis. 2. The switching element is a memory cell transistor formed on a semiconductor substrate, and the delay element includes a resistor formed on the semiconductor substrate and connected to the gate of the memory cell transistor. The storage element according to claim 1. 3. The memory element according to claim 2, wherein the resistor is a polysilicon layer formed on the semiconductor substrate and having a predetermined resistance value. 4. The switching element is a memory cell transistor formed on a semiconductor substrate, and the time delay element includes a capacitive element formed on the semiconductor substrate. Storage element. 5. A switching element, at least one switching element, and a delay element selectively connected to a switching control terminal of the switching element for controlling switching of the switching element with a delay time according to the content of the multivalued information. A multivalued information storage device comprising: a unit for sequentially reading out multivalued information from the switching element along a time axis according to a read signal supplied to the delay element. 6. The switching element is a memory cell transistor formed on a semiconductor substrate, and the delay element includes a resistor formed on the semiconductor substrate and connected to a gate of the memory cell transistor. The multivalued information storage device according to claim 5. 7. The multilevel information storage device according to claim 6, wherein the resistor is formed of a polysilicon layer formed on the semiconductor substrate and having a predetermined resistance value. 8. The multi-element device according to claim 5, wherein the switching element is a memory cell transistor formed on a semiconductor substrate, and the delay element includes a capacitive element formed on the semiconductor substrate. Value information storage device. 9. A plurality of memory cell transistors formed on a semiconductor substrate, and switching of the memory cell transistors is controlled with a delay time which is respectively connected to switching control terminals of the respective memory cell transistors and which corresponds to the contents of multi-valued information. A plurality of delay elements for achieving the above, and a unit for sequentially reading multi-valued information from the memory cell transistor along a time axis according to a read signal supplied to the delay element. apparatus. 10. The semiconductor memory device according to claim 9, wherein the delay element is formed on the semiconductor substrate and includes a resistor having a value corresponding to the reading time of the multivalued information. 11. The semiconductor memory device according to claim 10, wherein the resistor is made of a polysilicon layer formed on the semiconductor substrate and having a predetermined resistance value. 12. The semiconductor memory device according to claim 9, wherein the delay element includes a capacitive element formed on the semiconductor substrate and having a value corresponding to a read time of the multivalued information. 13. A plurality of memory cell transistors formed on a semiconductor substrate, and memory cell transistors each having a delay time selectively connected to a switching control terminal of each memory cell transistor and having a delay time according to the contents of multi-valued information. A plurality of delay elements for controlling switching, and means for sequentially reading multi-valued information from the memory cell transistor along a time axis according to a read signal supplied to the delay element. And semiconductor memory device. 14. A plurality of memory cell transistors formed on a semiconductor substrate, and memory cell transistors each having a delay time selectively connected to a switching control terminal of each memory cell transistor and having a delay time according to the contents of multi-valued information. A plurality of delay elements for controlling switching, a plurality of word lines for supplying a read signal to the switching control terminal of each memory cell transistor through the delay element, and a read supplied to the delay element A semiconductor memory device comprising: a unit that sequentially reads a signal output from the memory cell transistor along a time axis according to the signal as serial multi-valued information at a predetermined timing. 15. The semiconductor memory according to claim 14, wherein the reading means has a counter that counts a read clock signal according to a time width of a signal output from the transistor and its output timing. apparatus. 16. The read means includes a sense amplifier that amplifies a change in current appearing in the bit line connected to one end of the memory cell transistor in response to the output signal and supplies the amplified change to the counter. Claim 15
The semiconductor memory device according to 1. 17. The resistor formed on the semiconductor substrate and having a length corresponding to a resistance value for delaying the read signal by a time corresponding to a read time of the multivalued information. 15. The semiconductor memory device according to claim 14, further comprising: 18. A control signal supplied to a switching control terminal of a switching element is delayed by a time which is an integral multiple of a read clock, and signals appearing at an output terminal of the switching element are serially serialized in synchronization with the read clock. The multi-valued information storage device is operated by reading out the multi-valued information serially arranged on the time axis from the switching element.