JPH08235070A - Main memory management method and system - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the congestion of the network due to the transfer of page data of the consistency maintaining procedure when implementing distributed virtual shared storage on information processing devices connected by a network, and to execute the information processing device. Provided are a main memory management method and a system thereof that prevent a decrease in efficiency. [Configuration] A main memory management method in an information processing system for managing a main memory in page units, wherein a pseudo page management table 30 for managing pages in a plurality of pseudo page units is provided and a page fault occurs (S1 ), It is determined from the pseudo page management table to which of the pseudo pages the generated address belongs (S2), and when the page is accessed, the contents other than the determined pseudo page in the page are saved. Is controlled (S3). The storage control is realized by executing only the instruction for processing the determined pseudo page.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory management method and system in an information processing system for managing a main memory by a distributed virtual shared storage method.

[0002]

2. Description of the Related Art By controlling a network between a conventional main memory management device and an information processing device without having a special device, a program of the information processing device can be virtualized on a system including a plurality of information processing devices. In the distributed virtual shared storage method that realizes the sharing of main memory, the realization of coherency maintenance in the virtual shared storage is similar to the coherency maintenance of the cache memory of the parallel processing device and the page fault from the main storage management device. It is performed by receiving it as information and changing the main memory data of the program on another information processing apparatus. Commonly used cache memory coherency maintenance procedures include a write invalidation procedure and a write broadcast procedure.
(Modified, Exclusive, Shared, Invalid) procedure is used.

In the MESI procedure, all cache blocks belong to one of four states of Modified, Exclusive, Shared, and Invalid, and the state changes depending on a read or write request for each cache block. In addition, a read or write request for each cache block in a program on another information processing device is transmitted, and the state changes. A state transition diagram of the MESI procedure is shown in FIG. Initially, all the cache blocks are in the invalid state, and a read request and a write request for the cache block, and further a read request and a write request for the same cache block of another information processing device transit to another state.

In the distributed virtual shared storage method, MMU (Memo
Page fault from the (ry Management Unit) (when a page that is not registered in the page table for main memory management is accessed, or when a page that is registered in the page table but is not writable or readable is Since the state transition is caused when a prohibited access is performed), the above cache block is in page units, and the state of the MESI procedure is set in page units. So, when a state transition occurs,
Page data and control data must be transferred through a network connecting the information processing devices. Therefore, if a large amount of state transitions occur, network congestion will occur, and a lot of processing load will be placed on the processor of the information processing device.

Here, in the conventional information processing apparatus, the page size is several KB (bytes). Therefore, even when a plurality of information processing devices simultaneously access different data structures arranged in the same page of the distributed virtual shared storage, the above state transition occurs. In this way, arranging data structures that are not related to each other and can be accessed by different information processing devices in the same page causes a large loss in terms of network congestion and processor processing amount as described above. . However, when the page size is several KB, it is often difficult to arrange all the data structures on separate pages. Therefore, in the distributed virtual shared storage, it is more efficient to make the page size as small as possible in consideration of the network transfer amount and the processing amount by the processor.

[0006] Usually, in the conventional information processing apparatus, there are a fixed page size and a fixed page size defined by the hardware related to the main memory management, but the page size is variable. However, the minimum page size that can be set is often set. That is, when the above-mentioned distributed virtual shared storage is realized, if the minimum page size that can be handled by the main storage management device of such an information processing device is too large than the size of the data structure in the program to be executed, I couldn't reduce the size.

[0007]

Therefore, in an information processing apparatus having a fixed page size or a fixed minimum page size, the distributed virtual shared storage can be performed on a plurality of information processing apparatuses connected by a network. If the size of the data structure accessed by different information processing devices is very small compared to the page size and all of them cannot be placed on individual pages, the distributed virtual In data transfer etc. according to the procedure for maintaining consistency of shared memory, congestion of the network may occur or many processing may be requested to the information processing device,
There is a problem that the execution efficiency of the information processing device is reduced.

The present invention eliminates the above-mentioned conventional drawbacks, and reduces network congestion due to transfer of page data in a consistency maintaining procedure when implementing distributed virtual shared storage on information processing devices connected by a network. Provided are a main memory management method and a system thereof, which prevent deterioration of execution efficiency of an information processing device.

[0009]

In order to solve this problem, a main memory management method of the present invention is a main memory management method in an information processing system for managing a main memory in page units. If a pseudo page management table that manages in pseudo page units is provided and a page fault occurs,
From the pseudo page management table, it is determined which of the pseudo pages the generated address belongs to, and when the page is accessed, control is performed so as to save the contents in the page other than the determined pseudo page. Characterize.

Here, a page management table for managing in page units is further provided, and access to the page is performed by the page management table based on the attribute of the determined pseudo page. Further, the storage control is realized by executing only the instruction for processing the determined pseudo page when the page is accessed. Further, the saving control is performed using a hardware flag or a software exception instruction.

The main memory management method of the present invention is a main memory management method of an information processing system for managing the main memory in page units, and when the minimum manageable page size is limited, In order to output a request for processing a page fault in units of a pseudo page having a page size smaller than the page size, the actual hardware page fault is transmitted to the pseudo page management program, and the pseudo page management program pseudo When the page is set, the hardware page including the pseudo page is registered in the hardware page table, only the access instruction to the pseudo page is permitted, and the hardware page is again set in the hardware page table. It is characterized by removing from.

Here, the pseudo page management program transmits a fault to the page management system of the operating system when the pseudo page is not set. In addition, a trace flag that generates a trace exception after executing the access instruction is used to permit only the access instruction to the pseudo page. Further, to permit only the access instruction to the pseudo page, the soft exception instruction is written and executed at the instruction position next to the access instruction.

Further, the information processing system of the present invention is, in the information processing system for managing the main memory in page units, storing means for storing a pseudo page management table for managing pages in a plurality of pseudo page units and a page fault. When it occurs, a determination unit that determines which of the pseudo pages the generated address belongs to from the pseudo page management table, and a content other than the determined pseudo page in the page when the page is accessed. And a control means for controlling the storage.

Further, the information processing apparatus of the present invention is an information processing apparatus in an information processing system which is composed of a plurality of information processing apparatuses connected to each other through a communication network and manages a main memory in page units. Storage means for storing a pseudo-page management table managed in units of pseudo-pages; discrimination means for discriminating to which of the pseudo-pages the generated address belongs from the pseudo-page management table when a page fault occurs; When the page is accessed, a control unit that controls so as to save contents other than the determined pseudo page in the page is provided.

Further, the main memory management device of the present invention is an information processing system which comprises a plurality of information processing devices connected to each other by a communication network and manages the main memory in page units. A main memory management device connected between the storage means for storing a pseudo page management table for managing pages in units of a plurality of pseudo pages, and an address generated from the pseudo page management table when a page fault occurs. A determination unit that determines which of the pseudo pages belongs to, and a control unit that, when accessing the page, controls to save the contents of the page other than the determined pseudo page. Characterize.

Here, the storage means further stores a page management table managed in page units, and the control means accesses the page based on the attribute of the determined pseudo page. The management table will be used. Further, the control unit includes an instruction control unit that executes only an instruction for processing the determined pseudo page when the page is accessed. The instruction control means controls the instruction using a hardware flag or a software exception instruction.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing the flow of the main memory management method of this embodiment. Step S1 distinguishes the page fault from other faults and transmits it to the pseudo page management step, and step S2 determines whether or not the pseudo page is accessed from the address of the page fault.
When the access to the pseudo page is not set, the pseudo page management step of notifying the page management system of the fault, step S3 is an instruction for accessing the pseudo page (normally one instruction,
This is a step of permitting only one instruction) and prohibiting access to the page including the pseudo page after the next instruction.

In FIG. 1, in step S1, when a fault has occurred, the cause is checked, and if it is other than a page fault, the routine proceeds to a normal fault processing routine S4. If it is a page fault, the process proceeds to step S2a, and the address where the page fault occurs is checked. In step S2b, the existence of a pseudo page is checked for that address.

The pseudo page management is performed in the same manner as the normal page management table 20 (FIG. 2A).
Managed by 0. As shown in FIG. 2B, when the pseudo page is ¼ of the hardware page, various attributes must be managed for each pseudo page. However, the pseudo page simply divides the hardware page into four, retains the attributes, and determines whether or not to transmit the fault to the actual page management system. Since it is not / 4, the allocated physical page address is one physical page for every four pseudo pages. Therefore, in checking the pseudo page in steps S2b and S2c of FIG. 1, the physical address or the pseudo page attribute shown in the pseudo page management table is checked and the fault is transmitted to the page management system, or the step of FIG. S3
It is determined whether or not to proceed to the step of permitting access only for the instruction shown in.

Incidentally, the pseudo page management table 30 of FIG.
So, valid bit 21 and physical page number 25 are
Same as normal page management table 20, reference bit 2
2, modified bit 23 and permission 24 have data for a pseudo page that constitutes one page of hardware. That is, virtual address 0 for normal page management
The setting 26 of ˜0fff is divided into 4 to be 32 to 35. FIG. 2B shows a normal page management table 20.
There is a pseudou page 31 that is not found in. However, memory access by hardware is performed in page units according to the normal page management table 20.

The hardware page in step S3 of FIG. 1 is registered in the hardware page table (S
3a), permitting only one instruction to access the pseudo page (S3b), and prohibiting access to the page including the pseudo page after the next instruction (3).
c). In this step S3, when the pseudo page cannot be registered in the pseudo page unit when the pseudo page is registered in the hardware page management table, the peripheral page and the surrounding pseudo pages are registered in the hardware page unit. It is necessary to prevent access to the pseudo pages that may be protected by access.

<First Example of Step S3> In this embodiment, a trace instruction is used as shown in FIG. First, in step S31, the attribute of the corresponding address (above permission) is obtained from the pseudo page management table 30. Step S32
Then, the attribute bit of the hardware page including the pseudo page is set to be the same as the attribute bit of the pseudo page. In step S33, the trace bit of the status register in the user information stored in the stack or the like is turned on to execute only the instruction to access the pseudo page. After returning to the user mode, the instruction is executed to access the pseudo page in step S34.

After that, when a trace exception occurs in step S35, the fault processing starts. In the fault process, in step S36, the trace bit of the status register of the user is turned off, in step S37, all attribute bits in the hardware page including the pseudo page are obtained from the pseudo page management table 30, and step S38. Then, the strictest pseudo page attribute is selected, and the attribute of the actual hardware page is set in step S39. Then, execution of the next instruction is started.

<Second Example of Step S3> In the step of permitting only one instruction for accessing the pseudo page in step S3 of FIG. 1, it is possible to use a software exception instruction as shown in FIG. Step S of FIG.
51, S52, S57-S59. Step S3 in FIG.
1, S32, and S37 to S39.

In this case, instead of rewriting the status register of the user information stored in the stack, the value of the program counter is read in step S53,
The instruction next to the instruction indicated by the program counter is saved and rewritten as a software exception instruction. Then, when returning to the user mode, the instruction is executed to access the pseudo page in step S54.

As in step S55, when a software exception occurs in the next instruction, the software exception fault process starts. In the fault processing of the software exception, in step S56, the software exception is erased and the instruction saved earlier is written back to the same position. Thereafter, as in the case of FIG. 3, the hardware page management table including the set pseudo page is returned to the original state and the mode is returned to the user mode again. This allows only one instruction to access the pseudo page.

FIG. 6 is a diagram showing two configuration examples of the information processing system for implementing the main memory management method of this embodiment.
It is obvious that the main memory management method of this embodiment is not limited to these two configurations and can be applied to various configurations. or,
The main memory management method of this embodiment has a great effect in a system in which the main memory is distributed to a plurality of information processing devices or main memory management devices, but even if the main memory is unevenly distributed to a specific device. It can give a sufficient effect.

FIG. 6A shows an example of a system in which one information processing device 61 in the system has the page management table 20 and the pseudo page management table 30 shown in FIG. A plurality of information processing devices 61 to 63 are connected via a communication network 60 to form an information processing system. In the case of this configuration, the information processing device 61 centrally manages the main memory. FIG. 6B shows all the information processing devices 61 to 61 in the system.
64 is a main storage management device 65-68 with the communication network 60.
And each of the main memory management devices 65 to 68 has a page management table 20a to 20d and a pseudo page management table 30a to 30d. In the case of this configuration, the write invalidation procedure and the write broadcast procedure are performed as the consistency maintaining procedure between the main storage management devices 65 to 68.

In this embodiment, the access to the pseudo page is limited to only one instruction, but as described at the beginning of the embodiment, the normal access example is only followed and the present invention is not limited to this. If it is not one instruction, it is the address after the required number of instructions that is rewritten to the software exception instruction in the example of FIG. Further, the present invention may be applied to a system including a plurality of devices or an apparatus including one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0030]

As described above, when distributed virtual shared storage is realized on a plurality of information processing devices, it is possible to handle pseudo pages having a minimum page size specified by the hardware or less. Therefore, the amount of data exchange and the number of page invalidation requests due to the transfer of pages by the consistency maintaining procedure of the distributed virtual shared storage are reduced, and the congestion of the network is reduced and the processing of the information processing device is reduced. .

[Brief description of drawings]

FIG. 1 is a basic flowchart of a main memory management method of this embodiment.

FIG. 2 is a diagram showing a normal page management table and a pseudo page management table for managing pseudo pages.

FIG. 3 is a flow chart in which a trace flag is set for a pseudo page and access is permitted for only one instruction.

FIG. 4 is a state transition diagram of a consistency maintaining procedure (MESI procedure) of distributed shared storage.

FIG. 5 is a flowchart for permitting only one instruction access to a pseudo page using a software exception instruction.

FIG. 6 is a diagram showing a configuration example of an information processing system for realizing the main memory management method of the present embodiment.

Claims (20)

[Claims] 1. A main memory management method in an information processing system for managing main memory in page units, wherein a pseudo page management table for managing pages in plural pseudo page units is provided, and when a page fault occurs, From the pseudo page management table, it is determined which of the pseudo pages the generated address belongs to, and when the page is accessed, control is performed so as to save the contents of the page other than the determined pseudo page. Characteristic main memory management method. 2. A page management table for managing in page units is further provided, and access to the page is performed by the page management table based on an attribute of the determined pseudo page. The main memory management method according to item 1. 3. The storage control is realized by causing only an instruction for processing the determined pseudo page to be executed when the page is accessed. Main memory management method described. 4. The main memory management method according to claim 3, wherein the storage control is performed using a hardware flag or a software exception instruction. 5. A main memory management method for an information processing system for managing a main memory in page units, wherein a pseudo page size smaller than the page size is set when a manageable minimum page size is limited. In order to output the processing request for page fault in page units,
The actually generated hardware page fault is transmitted to the pseudo page management program, and when the pseudo page is set, the pseudo page management program stores the hardware page including the pseudo page in the hardware page table. A main memory management method characterized by registering to the pseudo page, permitting only an access instruction to the pseudo page, and again removing the hardware page from the page table of the hardware. 6. The main memory management method according to claim 5, wherein the pseudo page management program transmits a fault to the page management system of the operating system when the pseudo page is not set. 7. The main memory management method according to claim 5, wherein a trace flag for generating a trace exception after executing the access instruction is used to permit only the access instruction to the pseudo page. 8. The main memory management method according to claim 5, wherein only the access instruction to the pseudo page is permitted, but a soft exception instruction is written and executed at an instruction position next to the access instruction. 9. An information processing system for managing a main memory in page units, a storage unit for storing a pseudo page management table for managing pages in a plurality of pseudo page units, and the pseudo page when a page fault occurs. Determination means for determining which one of the pseudo pages the generated address belongs to from the management table; and control means for controlling so as to save the contents of the page other than the determined pseudo page when accessing the page. An information processing system comprising: 10. The storage unit further stores a page management table managed in page units, and the control unit controls the page management based on an attribute of the determined pseudo page for access to the page. The information processing system according to claim 9, which is implemented by a table. 11. The control unit includes an instruction control unit that executes only an instruction for processing the determined pseudo page when the page is accessed. Information processing system described. 12. The information processing system according to claim 11, wherein the instruction control unit controls the instruction using a hardware flag or a software exception instruction. 13. An information processing device in an information processing system, comprising a plurality of information processing devices connected to each other via a communication network, for managing a main memory in page units, wherein the page is managed in a plurality of pseudo page units. Storage means for storing a management table; determination means for determining which of the pseudo pages the generated address belongs to from the pseudo page management table when a page fault occurs; An information processing apparatus, comprising: a control unit that controls so as to save contents other than the determined pseudo page in the page. 14. The storage unit further stores a page management table managed in page units, and the control unit controls access to the page based on an attribute of the determined pseudo page. The information processing apparatus according to claim 13, wherein the information processing apparatus is implemented by a table. 15. The control means comprises instruction control means for executing only an instruction for processing the determined pseudo page when the page is accessed. The information processing device described. 16. The information processing apparatus according to claim 15, wherein the instruction control unit controls the instruction using a hardware flag or a software exception instruction. 17. An information processing system, comprising a plurality of information processing devices connected to each other via a communication network, for managing a main memory on a page-by-page basis. A main memory management device connected between the communication network and the information processing device. And a storage means for storing a pseudo page management table for managing pages in units of a plurality of pseudo pages, and to which of the pseudo pages the generated address from the pseudo page management table belongs when a page fault occurs. A main storage management device comprising: a determination unit that determines whether or not the page is accessed, and a control unit that controls the content other than the determined pseudo page in the page to be stored when the page is accessed. 18. The page management table further stores a page management table managed on a page-by-page basis, and the control unit manages the page management based on an attribute of the determined pseudo page. 18. The main memory management device according to claim 17, which is implemented by a table. 19. The control unit includes an instruction control unit that executes only an instruction for processing the determined pseudo page when the page is accessed. The main memory management device described. 20. The main memory management device according to claim 19, wherein said instruction control means controls an instruction using a hardware flag or a software exception instruction.