JPH08203883A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a method for manufacturing a semiconductor device capable of obtaining a sufficient isolation voltage even if oxidation enhanced diffusion occurs. [Structure] A P-type well 2 is formed on the surface of a P-type silicon substrate 1, an SiO ₂ film 3 is formed on the surface of the P-type silicon substrate 1, and a Si ₃ N ₄ film 4 is deposited on this SiO ₂ film 3. . Then, Si ₃ N ₄ is provided a photoresist film 5 on the film 4, Si ₃ N using the photoresist film 5 as a mask
_{4 The} film 4 is etched and the photoresist film 5 is removed. Next, the element isolation oxide film 6 is formed on the surface of the P-type well 2 by oxidizing the surface of the P-type silicon substrate 1 using the Si ₃ N ₄ film 4 as a mask. Next, the P-type silicon substrate 1 is annealed at a temperature of about 1000 ° C. for at least 1 minute in an atmosphere containing no oxygen. Therefore,
Even if the oxidation enhanced diffusion occurs, a sufficient isolation voltage can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an element isolation oxide film having a sufficient isolation voltage and having a narrow channel effect suppressed on the surface of a semiconductor substrate. .

[0002]

2. Description of the Related Art In the case of manufacturing an integrated circuit such as a DRAM on a silicon substrate, in order to insulate and isolate MOSFET elements from each other, a desired region on the silicon substrate is oxidized to locally isolate the elements from each other. Law (LOCO
S method) is used.

A conventional method of manufacturing a semiconductor device using this local oxidation method will be described below. First, B (boron), for example, is introduced into the silicon substrate as a conductive impurity. As a result, a P-type well is formed on the surface of the silicon substrate. Next, a SiO ₂ film is formed on the surface of the silicon substrate by thermal oxidation, and a Si ₃ N ₄ film is deposited on this SiO ₂ film. After this, this Si ₃ N ₄
A photoresist film is provided on the film, and the Si ₃ N ₄ film is etched using the photoresist film as a mask.

Next, after the photoresist film is removed, the surface of the P-type silicon substrate is oxidized by using the Si ₃ N ₄ film as a mask to form an element isolation oxide film on the surface of the P-type well. To be done.

Thereafter, a MOS transistor composed of a gate electrode and a diffusion layer of a source / drain region is formed in the element region separated and formed by the element isolation oxide film. In the transistor forming process at this time, 10
The heat treatment at 00 ° C or higher is not performed.

[0006]

In the conventional method of manufacturing a semiconductor device described above, when the element isolation oxide film is formed by the local oxidation method, the oxidation acceleration rate is increased in the silicon substrate immediately below the element isolation oxide film. Diffusion (oxidation enhance
d diffusion) occurs. This oxidation enhanced diffusion means that interstitial Si generated in a large amount at the Si-SiO ₂ interface during oxidation is
Increasing the diffusion of impurities by deeply flowing into the substrate. As a result, the B concentration profile in the P-type well of the silicon substrate changes to a profile having a steep gradient. That is, due to this oxidation enhanced diffusion effect, the B concentration in the element isolation oxide film increases,
The B concentration of the P-type well near the element isolation oxide film is
It becomes lower than the B concentration of the P-type well in the region away from the element isolation oxide film. As a result, punch-through easily occurs in the P-type well in the vicinity of the element isolation oxide film, and a problem arises in which a sufficient electrical element withstand voltage cannot be obtained. This problem becomes remarkable as the device becomes finer.

As a method for solving this problem, currently,
A method is used in which B is additionally ion-implanted only in the element isolation region in the P-type well before forming the element isolation oxide film. If the B concentration in the element isolation region is made sufficiently high by the ion implantation of B, the B concentration in the vicinity of the element isolation oxide film will decrease so that punch-through will occur even if the oxidation-enhanced diffusion occurs. It can be prevented. But,
This method has the following drawbacks.

That is, when the additional ion implantation of B is carried out, B exudes to the element region near the element isolation oxide film by diffusion, so that B in the channel region of the MOSFET formed near the element isolation oxide film. The concentration will increase. This is because as devices are miniaturized,
It will be noticeable. In particular, when the channel width of the MOSFET becomes narrower, the B concentration in the channel region of the MOSFET near the element isolation oxide film increases, so that the MOSF
This causes a narrow channel effect in which the threshold voltage of ET rises.

Therefore, in the semiconductor device manufactured by the above conventional manufacturing method, as a result, the profile of the B concentration in the P-type well remains steep.

The present invention has been made in consideration of the above circumstances, and an object thereof is to obtain a sufficient breakdown voltage for element isolation without causing a narrow channel effect even if oxidation enhanced diffusion occurs. Another object of the present invention is to provide a method of manufacturing a semiconductor device.

[0011]

In order to solve the above problems, the present invention comprises a step of forming an element isolation oxide film on the surface of an impurity region in a semiconductor substrate by a local oxidation method,
Annealing the semiconductor substrate in an oxygen-free atmosphere at a temperature of at least about 1000 ° C. for at least 1 minute.
Further, the atmosphere not containing oxygen is characterized by being an inert gas atmosphere.

[0012]

According to the present invention, after the element isolation oxide film is formed on the surface of the impurity region in the semiconductor substrate, the semiconductor substrate is kept in an oxygen-free atmosphere at a temperature of at least about 1000 ° C. for at least 1 minute. Impurity re-diffusion annealing is performed. Therefore, when the element isolation oxide film is formed, the impurity concentration of the region located near the element isolation oxide film in the impurity region is very thin due to the oxidation-enhancing diffusion effect. The impurity concentration in the impurity region can be made uniform by performing the impurity re-diffusion annealing in an atmosphere not containing the impurities.
Therefore, a sufficient isolation voltage can be obtained even if the oxidation enhanced diffusion occurs.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 6 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. First,
As shown in FIG. 2, for example, B (boron) is ion-implanted into the plane orientation (100) surface of the P-type silicon substrate 1 having a resistance of 4 Ω · cm to 6 Ω · cm. Next, the P-type silicon substrate 1 is annealed under a sufficiently high temperature condition of about 1200 ° C. As a result, a so-called P-type well (impurity region) 2 having a B concentration of about 5 × 10 ¹⁶ pieces / cm ³ is formed on the P-type silicon substrate 1.

Thereafter, as shown in FIG. 3, a SiO ₂ film 3 having a thickness of about 500 Å is formed on the surface of the P-type silicon substrate 1 by thermal oxidation. Next, on the SiO ₂ film 3 is, CVD (chemical vapor deposi
Si thickness becomes antioxidant film of the P-type silicon substrate 1 by tion) method is about 1000 Å ₃ N ₄ film 4
Are deposited.

Next, as shown in FIG. 4, the Si ₃ N _{4 is used.}
On the membrane 4, there is an opening 5a located above the P-type well 2.
A photoresist film 5 having is provided. Then, using the photoresist film 5 as a mask, the S located under the opening 5a is subjected to reactive ion etching (RIE) having a high etching selection ratio with respect to SiO _2.
The i ₃ N ₄ film 4 is removed by etching.

Thereafter, as shown in FIG. 5, after the photoresist film 5 is removed, the surface of the P-type silicon substrate 1 is sufficiently oxidized by using the Si ₃ N ₄ film 4 as a mask. As a result, the element isolation oxide film 6 is formed on the surface of the P-type well 2 of the P-type silicon substrate 1. At this time, the region 7 located in the vicinity of the element isolation oxide film 6 in the P-type well 2 is in a state in which the B concentration is very thin due to the oxidation enhanced diffusion effect.

Next, as shown in FIG. 6, the Si ₃ N _{4 is used.}
The film 4 is removed by dry etching having a high etching selection ratio with respect to SiO ₂ . Then, the element isolation forming process is completed.

[0018] Thereafter, as shown in FIG. 1, the P-type silicon substrate 1, in an atmosphere containing no oxygen, for example by a temperature of about 1200 ° C. in an inert gas atmosphere such as N ₂ 30
Annealing is performed for a minute. As a result, the area 7 disappears. That is, the B concentration in the entire region of the P-type well 2 becomes constant by the annealing.

According to the above-mentioned embodiment, the surface of the P-type silicon substrate 1 is locally oxidized by using the Si ₃ N ₄ film 4 as a mask, so that the element isolation oxide film 6 is formed on the surface of the P-type well 2.
Is formed. At this time, as shown in FIG. 6, a region 7 located in the vicinity of the element isolation oxide film 6 in the P-type well 2
Has a very low B concentration due to the oxidation enhanced diffusion effect. Therefore, in the P-type well 2, a steep B concentration profile is formed by the region 7. That is, the B concentration in the P-type well 2 drops sharply in the region 7 as compared with the other P-type well 2 regions. In order to restore such a steep B concentration profile to a gentle profile, after forming the element isolation oxide film 6,
1 on the P-type silicon substrate 1 in an atmosphere of an inert gas such as N _2.
Impurity re-diffusion annealing is performed at a temperature of about 200 ° C. for 30 minutes. As a result, in the P-type well 2, only impurity diffusion due to normal heat occurs, not oxidation enhanced diffusion. As a result, the steep B in the P-type well 2
It is possible to change the density profile in a gentle profile, that is, in the direction in which the B density becomes uniform. Therefore, before the element isolation oxide film is formed, the B concentration of the P-type well 2 in the vicinity of the element isolation oxide film 6 can be reduced even if B is not additionally ion-implanted only in the element isolation region in the P-type well. The decrease can be prevented.
Therefore, it is possible to obtain a sufficient withstand voltage for element isolation even if oxidation enhanced diffusion occurs, without causing a narrow channel effect as in the prior art.

Further, no crystal defect occurs in the P-type silicon substrate 1. In the above-mentioned embodiment, the P-type silicon substrate 1 is annealed in an inert gas atmosphere at a temperature of about 1200 ° C. for 30 minutes. A temperature higher than the heat treatment temperature performed in the transistor forming process,
Specifically, by annealing at a temperature of 1000 ° C. or higher, the time required for re-diffusing the impurities is as short as possible, specifically, if the annealing is performed for 1 minute or more, the above-described effects can be obtained. is there. That is, an experiment was conducted in which an element isolation oxide film was formed on the surface of the P-type silicon substrate 1 by a local oxidation method, and then annealing was performed at a temperature of about 900 ° C. for 4 hours. The effect of making the B concentration uniform was not obtained. On the other hand, as a result of performing an experiment in which an element isolation oxide film is formed and annealing is performed at a temperature of about 1190 ° C. for 20 minutes,
The above effects were obtained. Therefore, the condition of this annealing depends on the state of the B concentration profile and the B concentration of the initial P-type well, but is 1 even if the temperature is low.
About 000 ° C. is required, and time is required for at least 1 minute or several minutes.

Although the present invention is applied to the case where the P well region 2 is formed on the P type silicon substrate 1 and the element isolation oxide film 6 is formed on the P well region 2, the N well region is formed. The present invention can be applied to the case where an element isolation oxide film is formed in this N well region.

[0022]

As described above, according to the present invention,
After forming an element isolation oxide film on the surface of the impurity region in the semiconductor substrate, the semiconductor substrate is annealed in an atmosphere containing no oxygen. Therefore, a sufficient isolation voltage can be obtained even if the oxidation enhanced diffusion occurs without causing the narrow channel effect.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the invention, showing the next step of FIG.

FIG. 2 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

3 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention, showing the next step of FIG.

FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention, showing the next step of FIG. 3;

FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention, showing the next step of FIG.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention, showing the next step of FIG. 5;

[Explanation of symbols]

1 ... P-type silicon substrate, 2 ... P-type well (impurity region), 3 ... SiO ₂ film, 4 ... Si ₃ N ₄ film, 5 ... Photoresist film, 5a ... Opening part, 6 ... Element isolation oxide film, 7 ... P
A region located near the element isolation oxide film in the mold well.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/762 H01L 21/76 D

Claims (2)

[Claims] 1. A step of forming an element isolation oxide film on a surface of an impurity region in a semiconductor substrate by a local oxidation method, and at least at a temperature of at least about 1000 ° C. in an atmosphere containing no oxygen on the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of annealing for 1 minute. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxygen-free atmosphere is an inert gas atmosphere.