JPH08202569A - Gated clock verification method - Google Patents

Abstract

(57) [Abstract] [Purpose] Accurate detection of gated clock errors without increasing the verification time. [Structure] A clock pulse width when a pulse of a desired level of a clock signal passes through a gated clock circuit is calculated (step S4), and a gated clock pulse width of a gated clock output from the gated clock circuit is calculated. When the gated clock pulse width is narrower than the clock pulse width, the timing of the enable signal is determined to be defective (step S8).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design method for automatically designing a logic circuit, and more particularly, verification of a gated clock for detecting an error in a gated clock generated by a gated clock circuit. Regarding the method.

[0002]

2. Description of the Related Art As a data transfer system in an LSI, a circuit configuration of a completely synchronous system is adopted as shown in FIG. 27 because the data transfer conditions are simple and the intended operation is easily designed automatically. (FIG. 28 shows FIG. 27)
Shows a timing chart of the circuit configuration shown in FIG.
Then, when the circuit configuration is determined, it is verified whether or not the storage element such as the memory, the flip-flop, or the latch can store the data without malfunctioning.

That is, whether data is given to a predetermined edge of the clock signal at a time earlier than the timing defined as the standard (setup time), and for the predetermined edge until after the timing defined as the standard. It is verified whether the same data is maintained (hold time) and whether the H-level or L-level pulse width of the clock signal satisfies the minimum value (pulse width).

As a conventional technique for performing timing verification,
There is a technique disclosed in Japanese Patent Laid-Open No. 5-28210, but since this technique corrects the difference in cell delay time when the number of cells connected to the output is different, the above-mentioned setup time, Not applicable for verification of hold time and pulse width. Therefore, for such timing verification, one of two verification methods, a dynamic verification method or a static verification method, is used.

In the dynamic verification method, a test pattern is applied to a logic circuit by using a logic simulation technique. And by observing various signal waveforms obtained by applying the test pattern, or
By comparing the simulation results with expected values, we check whether the designed circuit operates properly.

In the static verification method, circuit connection information,
By referring to the delay information of the elements and wiring, the cycle and duty ratio of the clock signal, etc., all the signal paths related to the verification point in the circuit are searched. Also, the timing of the signal level change at the verification location is obtained from the search results. Then, it is verified whether the obtained timing satisfies the setup time, the hold time, and the pulse width required for the operation of the device.

[0007]

However, as in the circuit shown in FIG. 27, in the data transfer of the perfect synchronization system, the logic circuit 92 always outputs the clock signal. Therefore, the power consumption of the flip-flop increases due to the influence of the clock signal. The amount of increase is 2 to the power consumption of the entire circuit.
It accounts for 50%. On the other hand, when the gated clock method is adopted as the data transfer method as shown in FIG. 29, the clock signal is given only when it is necessary for data transfer, as shown in the timing chart of FIG. Therefore, unnecessary power consumption is suppressed, and the power consumption can be reduced.

However, in the case of this configuration, the data transfer conditions are complicated. As a result, when the gated clock system is adopted in a configuration having a large circuit scale, such as an LSI in recent years, the following problems occur.

That is, in the dynamic verification method, since the number of verification points is large, an extremely large number of test patterns are required to cause a required level change in all the verification points. That is, the test pattern becomes long, and the verification time becomes long. Further, depending on the circuit configuration, it has been difficult to create a test pattern for verifying the setup time, the hold time, and the pulse width.

On the other hand, in the static verification method, it is verified whether the setup time, the hold time, and the pulse width satisfy specified values based on the characteristics of the device. Therefore, the circuit for generating the gated clock is shown in FIG.
Even in the case of the circuit shown in FIG. 4, the increase in the inspection time does not become large. In addition, when the gated clock timing is incorrect and these prescribed values cannot be satisfied, an error is detected.

FIG. 25 is a timing chart when a correct gated clock is generated in the circuit of FIG. 24, and FIG. 26 is a timing chart when an incorrect gated clock is generated. . The error detection will be described in detail with reference to FIG. 26. In FIG. 26, if at least one of the periods 95 and 96 does not satisfy the pulse width specified value, it is detected as an error. However, a situation may occur in which both the periods 95 and 96 satisfy the specified value of the pulse width. When such a situation occurs, since the pulse width satisfies the specified value, no error is detected, and it is determined that no error occurs in the operation as in the case of the timing of FIG.
That is, when the static verification method is applied to the gated clock method, there is a problem that an error may be missed.

The present invention was devised to solve the above problems, and an object of the present invention is to provide a pulse width of a clock signal passing through a gated clock circuit and a pulse width of a gated clock. It is an object of the present invention to provide a method for verifying a gated clock that can accurately detect an error in the gated clock without increasing the verification time by verifying the gated clock based on the comparison.

Another object of the present invention is to provide a gated clock verification method capable of accurately detecting an error in a gated clock in an LSI to which a primary clock is externally applied.

[0014]

In order to solve the above problems, a gated clock verifying method according to the invention of claim 1 includes a clock signal output from a clock signal circuit which is a signal path of a primary clock, and The clock signal circuit is applied to a method for verifying a gated clock generated by a gated clock circuit to which an enable signal output from an enable signal circuit to which a primary enable clock having a known timing with a primary clock is derived is applied. Calculating the edge timing of the pulse of the desired level of the clock signal based on the delay time of the clock signal, Level pulse is the gated Calculating a clock pulse width when it passes through the locking circuit, the based on the primary enable clock and the delay time of the enable signal circuit,
Calculating the edge timing of the desired level pulse of the enable signal, the edge timing of the desired level pulse of the clock signal, the edge timing of the desired level pulse of the enable signal, and the delay time of the gated clock circuit. From the above, the gated clock pulse width of the gated clock output by the gated clock circuit is calculated, and when the gated clock pulse width is narrower than the clock pulse width, it is determined that the timing of the enable signal is defective. How to do it.

A gated clock verification method according to a second aspect of the present invention is a method for verifying the gated clock in an LSI to which the primary clock is externally applied.

[0016]

The operation of the invention according to claim 1 will be described below.

If the gated clock circuit is, for example, the circuit shown in FIG. 24, the edge timing of the pulse 81 shown in FIG. 25 or the pulses 82 and 83 shown in FIG. ,
It is calculated based on the delay time of the clock signal circuit.

Next, the calculated edge timing,
Based on the delay time of the gated clock circuit, the clock pulse width when the pulse 81 or the pulses of the pulses 82 and 83 pass through the gated clock circuit is calculated. Further, the edge timing of the pulse 84 or the pulse 85 is calculated as the pulse of the desired level of the enable signal. Then, the gated clock pulse width that is the pulse width of the gated clock is calculated from the relationship between these pulses.

When there is no error in the gated clock, as shown in FIG. 25, the gated clock pulse width becomes equal to the clock pulse width when the pulse 81 passes through the gated clock circuit.

On the other hand, when there is an error in the gated clock, the gated clock pulse width becomes narrower than the clock pulse width when the pulses 82 and 83 pass through the gated clock circuit, as shown in FIG.
Therefore, when the gated clock pulse width is narrower than the clock pulse width passed through the gated clock circuit, it is determined that the gated clock is defective, that is, the timing of the enable signal is defective.

The operation of the invention according to claim 2 will be described below.

The delay time of the clock signal circuit becomes the delay time of the signal path from the input terminal of the primary clock to the output of the clock signal, and the clock pulse width passing through the gated clock circuit is calculated based on this delay time.

[0023]

An embodiment of the present invention will be described below with reference to the drawings.

As the gated clock circuit, for example, a circuit configuration is shown in FIG. 14, a timing chart is shown in FIG. 15, an AND gate is used, a circuit configuration is shown in FIG. 16, and a timing chart is shown in FIG. , OR
A structure using a gate, a circuit structure in FIG. 18, a structure using a NAND gate as shown in a timing chart in FIG. 19, a circuit structure in FIG. 20, and a NOR gate as shown in a timing chart in FIG. The configuration, the circuit configuration in FIG. 22, and the configuration using a latch as shown in the timing chart in FIG. 23 are possible. The logic of the enable signal, the logic of the clock signal, and the logic of the gated clock are positive logic or negative logic depending on the difference in each element configuration.

FIG. 1 is a flow chart showing an embodiment of a gated clock verification method according to the present invention.
The outline will be described with reference to FIG.

By referring to the connection information of the logic circuit, all the signal paths (clock signal circuits) of the primary clock given from the outside of the LSI are searched. Then, a mark is given to the terminal of the element to which the primary clock is transmitted (step S1).

Next, the delay time of the clock signal which is the source of the gated clock is calculated. That is, the signal path from the clock signal that is the source of the gated clock to the input terminal of the primary clock is searched based on the connection information of the logic circuit and the mark added in step S1. For the searched signal path, the minimum delay time and the maximum delay time when the clock signal rises, and the minimum delay time and the maximum delay time when the clock signal falls (step S2).

Next, the rising time and the falling time of the clock signal (the edge timing of the pulse of the desired level of the clock signal) are calculated. That is, the information such as the cycle and duty of the primary clock is obtained from the information given in advance. Then, with the time when the level of the primary clock changes as the reference time, the time when the clock signal rises after the level of the primary clock changes is calculated from the corresponding minimum delay time and maximum delay time. Further, with the time when the level of the primary clock changes as the reference time, the time when the clock signal falls after the level of the primary clock changes is calculated from the corresponding minimum delay time and maximum delay time (step S3).

Next, the clock pulse width (hereinafter referred to as the C pulse width) which is the pulse width of the clock signal passing through the gated clock circuit is calculated. That is, the minimum value of the H level pulse width or the minimum level of the L level pulse width of the clock signal is calculated from the rising time and the falling time of the clock signal and the delay time of the gated clock circuit. This C pulse width is
It is a value indicating the pulse width of the gated clock when there is no error in the gated clock (step S4).

Next, as in the case of the clock signal, the delay time of the enable signal is calculated. That is, the enable signal circuit is searched based on the connection information of the logic circuit and the added mark. Then, for the searched signal path, the minimum delay time and the maximum delay time when the enable signal rises, and the minimum delay time and the maximum delay time when the enable signal falls (step S
5).

Next, the rising time and the falling time of the enable signal (the edge timing of the desired level pulse of the enable signal) are calculated. That is, the difference in timing between the primary enable clock and the primary clock is obtained from the information given in advance.
With the time at which the level of the primary clock changes as the reference time, the earliest or latest time at which the enable signal rises and the earliest or latest time at which the enable signal falls are the applicable minimum delay time and maximum delay time. And from (step S
6).

Next, the rise time and fall time of the gated clock are calculated. That is, the rising time and the falling time of the gated clock are calculated from the edge timing of the desired pulse of the clock signal obtained in step S3 and the edge timing of the desired pulse of the enable signal obtained in step S6 (step S7). ).

Next, from the edge timing of the desired pulse of the gated clock obtained in step S7, the H level pulse width or the L level pulse width of the gated clock is changed to the gated clock pulse width (G pulse width in the following). Called as). Then, the G pulse width obtained is compared with the C pulse width obtained in step S4. When the G pulse width is narrower than the C pulse width, it is determined that the timing of changing the enable signal is incorrect (steps S8 and S10). If not, the timing of the enable signal is determined to be correct (steps S8 and S9). The above operation is
This is performed for all gated clock circuits (step S11).

The first embodiment will be described in detail below.

FIG. 2 shows a circuit configuration to be verified for the gated clock timing. The gated clock circuit is an AND gate 3. Therefore, the gated clock GCK (in the following, the clock G
(Referred to as CK) becomes an H level pulse. For this reason,
The C pulse width is the minimum value of the H level pulse width of the clock signal CK that has passed through the AND gate 3, and the G pulse width is the minimum value of the H level pulse of the clock GCK. Further, the flip-flop 4 to which the clock GCK is guided to the clock input latches the data at the rising edge of the clock GCK.

A primary clock MCK (hereinafter referred to as a clock MCK) is used as a clock signal CK.
The clock signal circuit that leads to the ND gate 3 is the buffer 2, and the enable signal circuit that generates the enable signal EN from the primary enable clock SCK (hereinafter referred to as the clock SCK) whose phase difference from the clock MCK is known is the clock input circuit. It is a flip-flop 1 (hereinafter referred to as FF1) that operates at a rising edge. Further, the FF1 is set to the reset state by a signal line (not shown) outside the predetermined period.

Further, the cycles of the clock MCK and the clock SCK are both 20 ns as shown in FIG. The H-level pulse width and the L-level pulse width are both 10 ns. That is, the duty of both the clock MCK and the clock SCK is 50%. The phase difference between the clock MCK and the clock SCK is known as skew, as shown in FIG.

The minimum delay time and the maximum delay time of each element are given in advance as a list shown in FIG. It should be noted that "LH _- MIN _- A _- Y" shown in FIG. 8 represents the minimum delay time after the input terminal A changes until the output terminal Y rises. That is, in the buffer 2, the minimum delay time after the input terminal A rises until the output terminal Y rises is 1.0 ns.

The case where the normal clock GCK is generated will be described below.

All the signal paths through which the clock MCK is transmitted are searched, and marks are added to the terminals of the elements forming the searched signal paths. In the case of the circuit shown in FIG. 2, marks are given to the input terminal A and output terminal Y of the buffer 2 and the input terminal B and output terminal Y of the AND gate 3 (step S1).

The signal path (clock signal circuit) of the clock signal CK from which the clock GCK is generated is AND
From the output terminal Y of the gate 3 toward the input terminal of the clock MCK, the marks are sequentially traced to be searched (step S2). In the circuit configuration shown in the figure,
Input terminal A of buffer 2-Output terminal YA of buffer 2
It becomes the input terminal B of the ND gate 3.

Next, the delay of the searched clock signal circuit
Ask for time. In this case, from the input terminal to the AND gate 3
The buffer 2 is only interposed at the input terminal B of
It Therefore, the input terminal B of the AND gate 3 rises.
Minimum delay time lh_-min _-ck, maximum delay time lh_-max
 _-ck, when the input terminal B of the AND gate 3 falls
Minimum delay time of hl_-min_-ck, maximum delay time hl_-max_-
ck is

[0043]

[Formula 1] lh _- min _- ck = LH _- MIN of buffer 2
_{- A - Y = 1.0 (ns} ) lh - max - ck = Buffer _{2 LH - MAX - A - Y} = 1.5 (ns) hl - min - ck = Buffer 2 HL _- MIN _- A _- Y = 1.5 (ns) hl _- max _- ck = HL _- MAX _- A _- Y of buffer 2 = 2.0 (ns).

Referring to the timing charts of FIGS. 4 and 5, the rising time of the clock MCK is t1 (0n
s), assuming that the time when the clock signal CK rises after time t1 is t2, the time when the clock MCK next falls after time t1 is t3, and the time when the clock signal CK falls after time t3 is t4, each time is It becomes as follows (step S3).

[0045]

## EQU00002 ## t1 = 0 (ns) t2 = t1 + lh _- max _- ck = 0 + 1.5 = 1.5 (ns) t3 = t1 + PWH _- MCK = 0 + 10 = 10 (ns) t4 = t3 + hl _- min _- ck = 10 + 1.5 = 11.5 (ns) Therefore, the minimum value pwh _- ck of the C pulse width at which the clock signal CK becomes H level is

[0046]

## EQU00003 ## pwh _- ck = t4-t2 = 11.5-1.5 = 10 (ns). Clock signal CK that is the source of clock GCK
However, if it passes through the AND gate 3 without being affected by the enable signal EN, its C pulse width becomes equal to the G pulse width of the normal clock GCK. Therefore, the normal G pulse width pwh _- const that becomes H level is

[0047]

Equation 4] _{pwh - const = (pwh - ck} + hl - min - ck + AND gates 3 of _{HL - MIN - B - Y)} - (lh - max - ck + AND gates 3 of LH _- MAX _- B _- Y ) = (10 + 1.5 + 1.8) − (1.5 + 1.8) = 10 (ns) (step S4).

Next, all the signal paths from the clock SCK to the enable signal EN are searched (step S5).
This is the clock SC from the input terminal A of the AND gate 3.
By sequentially tracing the mark in the K direction, it becomes possible to find the mark. In the circuit shown in FIG. 2, the signal path (enable signal circuit) of the enable signal EN is SCK-
The input of FF1−the output of FF1−the input terminal A of the AND gate 3.

Therefore, the minimum delay time lh _-- min _-- e of the enable signal circuit when the enable signal EN rises
n, maximum delay time lh _- max _- en, minimum delay time hl _- min _- en, maximum delay time hl _- max _- en when enable signal EN falls,

[0050]

[Number 5] lh _- min _- en = FF1 of _{LH - MIN - CK - Q =} 1.0 (ns) lh - max - en = FF1 of _{LH - MAX - CK - Q =} 1.5 (ns) hl - min _- en = FF1 of _{HL - MIN - CK - Q =} 1.5 (ns) hl - max - en = FF1 of _{HL - MAX - CK - Q =} 2.0 a (ns).

Here, the clock MCK and the clock SCK
The value of the phase difference skew between and SKEW _- MCK _- SCK is 1
4 ns (see FIG. 5). Further, the time when the clock SCK rises is t5, and after the time t5, the enable signal EN
Rises at time t6, and after time t5, clock SC
If the time when K rises is t7 and the time when the enable signal EN falls after time t7 is t8, each time is

[0052]

[6] _{t5 = t1 + SKEW - MCK -} SCK = 0 + 14 = 14 (ns) t6 = t5 + lh - max - en = 14 + 1.5 = 15.5 (ns) t7 = t5 + PWH - SCK + PWL _- SCK = 14 + 10 + 10 = 34 (ns) t8 = t7 + hl _- min _- en = 34 + 1.5 = 35.5 (ns).

Since the gated clock circuit is the AND gate 3, the rising time of the clock GCK is t.
9. If the time when the clock GCK falls is t10, the time t9 is

[0054]

## EQU00007 ## t9 = t2 + delay time of AND gate 3 (however, t6 ≦ t2) t9 = t6 + delay time of AND gate 3 (however, t2 <t6 <t4) (step S7).

When t4 <t6, the times t2 and t
Since the clock GCK is not changed by the clock signal CK or the enable signal EN at 4 and t6, the times t2 and t4 are delayed by one cycle of the clock MCK. Then, at times t9 and t1 by the same method.
Ask for 0.

At time t10,

[0057]

## EQU00008 ## t10 = t4 + delay time of AND gate 3 (where t4 <t8) t10 = t8 + delay time of AND gate 3 (where t2 ≦ t8 ≦ t4)

When t8 <t2, the times t2 and t
The clock signal CK or the enable signal EN at 4, t8 does not change the clock GCK.

In the timing chart shown in FIG. 5, t4
Since <t6, the clock GCK does not rise in response to the level changes at times t2, t4, and t6. Therefore, the times t2 and t4 are delayed by one cycle, and the delayed timing is time t2't4 '. At this time,
At time t2 'and time t4',

[0060]

T2 ′ = t2 + PWH ₋ MCK + PWL ₋ MCK = 1.5 + 10 + 10 = 21.5 (ns) t4 ′ = t4 + PWH ₋ MCK + PWL ₋ MCK = 11.5 + 10 + 10 = 31.5 (ns).

Further, the times t9 and t10 are changed to the times t2 ',
From t4 ', t6, t8, it is obtained as follows. That is, since t6 ≦ t2 ′,

[0062]

[Mathematical formula-see original document] t9 = t2 '+ AND gate 3 LH _- MAX _- B _- Y = 21.5 + 1.8 = 23.3 (ns) Since t4'≤t8,

[0063]

[Expression 11] t10 = t4 ′ + AND gate 3 has HL ₋ MIN ₋ B ₋ Y = 31.5 + 1.8 = 33.3 (ns).

Therefore, the H level G pulse width pwh _- gck of the clock GCK is

[0065]

## EQU00008 ## pwh _- gck = t10-t9 = 33.3-23.3 = 10 (ns). Since this G pulse width is the same as the C pulse width guided to the input terminal B of the AND gate 3, the timing of FIG. 5 is determined to be correct.

Now, consider the case where the phase difference SKEW _- MCK _- SCK between the clock MCK and the clock SCK is 5 ns as shown in FIG. Times t1 to t4 are the same as in the case of the normal clock GCK. Therefore, each time is

[0067]

[Mathematical formula-see original document] t1 = 0 (ns) t2 = 1.5 (ns) t3 = 10 (ns) t4 = 11.5 (ns).

Since the phase difference between the clock MCK and the clock SCK is 5 ns, the time t5 to t8 is

[0069]

[Number 14] _{t5 = t1 + SKEW - MCK -} SCK = 0 + 5 = 5 (ns) t6 = t5 + lh - max - en = 5 + 1.5 = 6.5 (ns) t7 = t5 + PWH - SCK + PWL _- SCK = 5 + 10 + 10 = 25 (ns) t8 = t7 + lh _- min _- en = 25 + 1.5 = 26.5 (ns).

Further, the time t9 when the clock GCK rises
Is t2 <t6 ≦ t4,

[0071]

[Mathematical formula-see original document] t9 = t6 + AND gate 3 has LH _- MAX _- A _- Y = 6.5 + 1.8 = 8.3 (ns), and t4≤t8.

[0072]

## EQU16 ## t10 = t4 + AND gate 3 has HL _- MIN _- B _- Y = 11.5 + 1.8 = 13.3 (ns). Therefore, G pulse width of clock GCK pwh _- gc
k is

[0073]

[Number 17] _{pwh - gck = t10 - t9 =} 13.3 - a 8.3 = 5 (ns). Since this G pulse width is narrower than the C pulse width introduced to the input terminal B of the AND gate 3, it is judged that the timing of FIG. 6 is generating the wrong clock GCK.

The second embodiment will be described in detail below.

FIG. 9 shows a circuit configuration to be verified, and the gated clock circuit is an OR gate 6. Therefore, the clock GCK becomes an L level pulse. Therefore, the C pulse width is the minimum value of the L level pulse width of the clock signal CLK that has passed through the OR gate 6, and the G pulse width is the minimum value of the L level pulse width of the clock GCK. In addition, the latch 5 in which the clock GCK is led to the G input, when the clock GCK is at the H level,
The data given to the D input is sent to the output Q. Then, at the falling edge of the clock GCK, the data is latched and sent to the output Q.

Further, the clock MCK is changed to the clock signal CLK.
The clock signal circuit that leads to the OR gate 6 is only the wiring, and the clock signal CLK is equal to the clock MCK. Also, the enable signal circuit is only wiring,
The enable signal ENBL is equal to the clock SCK.

As shown in FIG. 12, the cycle of the clock MCK is 20 ns, and the H level pulse width and the L level pulse width are both 10 ns. The cycle of the clock SCK is 40 ns, and the pulse width of H level and the pulse width of L level are both 20 ns.
Is. That is, the clock MCK and the clock SCK are
The duty is both 50%. The minimum delay time and the maximum delay time of the OR gate 6 are given in advance as a list shown in FIG.

Below, a normal gated clock GC
The case where K is generated will be described.

Now, it is assumed that the phase difference SKEW _- CLK _- ENBL between the clock MCK and the clock SCK is 5 ns as shown in FIG. First, the clock signal CL
All of the K routes are searched, and the terminal of the element of the searched route is marked. In this case, marks are given to the input terminal A and the output terminal Y of the OR gate 6.

A path is searched from the clock GCK toward the clock SCK. In this case, the clock G
The clock signal CLK that is the source of CK is the clock SCK.
Is. Therefore, the minimum delay time and the maximum delay time of the path from the clock SCK to the input terminal A of the OR gate 6 are
It is 0 ns both when the clock GCK rises and when it falls. That is,

[0081]

Lh _- min _- ck = 0 (ns) lh _- max _- ck = 0 (ns) hl _- min _- ck = 0 (ns) hl _- max _- ck = 0 (ns)

[0082] Normal clock G pulse width of GCK L level pwl _- const is not the clock signal CLK is controlled by the enable signal ENBL, since the same as those that have passed through the OR gate 6,

[0083]

[Mathematical formula-see original document] pwl _- const = (PWL _- CLK + lh _- min _- ck + OR gate 6 LH _- MIN _- A _- Y)-(hl _- max _- ck + OR gate 6 HL _- MAX _- A _- Y) ) = (10 + 0 + 1.5)-(0 + 2.0) = 9.5 (ns).

The enable signal ENBL is the clock S
Since it becomes the same signal as CK, OR from clock SCK
The minimum delay time and the maximum delay time of the signal path (enable signal circuit) to the input terminal B of the gate 6 are 0 ns at both the rising and falling edges of the enable signal ENBL. That is,

[0085]

Lh _- min _- en = 0 (ns) lh _- max _- en = 0 (ns) hl _- min _- en = 0 (ns) hl _- max _- en = 0 (ns)

The time t21 at which the clock MCK (clock signal CLK) rises is set to 0 ns. Then, after t21, the next clock MCK (clock signal CLK)
Falls at t22, and after the clock MCK (clock signal CLK) falls at time t22, the next fall of the clock signal CLK is designated as t23.
After 22 the clock MCK (clock signal CL
If the time when K) rises is t24 and the time when the clock signal CLK rises after t22 is t25, each time is

[0087]

Equation 21] t21 = 0 (ns) t22 = t21 + PWH - CLK = 0 + 10 = 10 (ns) t23 = t22 + hl - max - ck = 10 + 0 = 10 (ns) t24 = t22 + PWL - CLK = 10 + 10 = 20 (ns) t25 = t24 + lh _- min _- ck = 20 + 0 = 20 (ns).

If the enable signal ENBL falls during one cycle of the clock signal CLK from time t21 to time t24, the clock SCK (enable signal ENBL) falls at time t26 and enable after time t26. At time t27 when the signal ENBL falls,

[0089]

## EQU22 ## t26 = t21 + SKEW _- CLK _- ENBL = 0 + 5 = 5 (ns) t27 = t26 + hl _- max _- en = 5 + 0 = 5 (ns).

After the time t26, the clock S
Time t2 when CK (enable signal ENBL) rises
8 and the enable signal ENB after time t28.
The time t29 when L rises is

[0091]

[Mathematical formula-see original document] t28 = t25 + PWL _- ENBL = 5 + 20 = 25 (ns) t29 = t28 + lh _- min _- en = 25 + 0 = 25 (ns).

At time t when the clock GCK falls.
30, and the time t31 when the clock GCK rises,

[0093]

T30 = t27 + maximum delay time of OR gate 6 (however, t23 <t27) t30 = t23 + maximum delay time of OR gate 6 (however, t27 ≦ t23) t31 = t25 + minimum delay time of OR gate 6 However, t25 <t29) t31 = t29 + The minimum delay time of the OR gate 6 (where t29 ≦ t25). That is, in the case of the timing shown in FIG.

[0094]

T30 = t23 + HL _- MAX _- B _- Y = 10 + 2 = 12 (ns) t31 = t25 + LH _- MIN _- A _- Y = 20.0 + 1.5 = 21.5 (ns) Becomes

Further, the G pulse width pwl _- gck at which the clock GCK at this time becomes the L level is

[0096]

[Number 26] _{pwl - gck = t31 - t30 =} 21.5 - a 12 = 9.5 (ns). Therefore, the C pulse width that has passed through the OR gate 6 becomes equal to the G pulse width, so that it is determined that the clock GCK generated at this time is generated at the correct timing.

Below, referring to FIG. 11, the clock M
Phase difference between CK (clock signal CLK) and clock SCK (enable signal ENBL) SKEW _- CLK _- EN
A case where BL is 13 ns will be described.

Times t21 to t25 at this time are the same as those in the case where the phase difference SKEW _- CLK _- ENBL is 5 ns,

[0099]

## EQU27 ## t21 = 0 (ns) t22 = 10 (ns) t23 = 10 (ns) t24 = 20 (ns) t25 = 20 (ns).

If the enable signal ENBL falls during one cycle of the clock signal CLK from time t21 to time t24, the clock SCK (enable signal ENBL) falls at time t26 and after the time t26, the enable signal ENBL is enabled. At time t27 when the signal ENBL falls,

[0101]

[Equation 28] t26 = t21 + SKEW _- CLK _- ENBL = 0 + 13 = 13 (ns) t27 = t26 + hl _- max _- en = 13 + 0 = 13 (ns).

After the time t26, the clock S
Time t2 when CK (enable signal ENBL) rises
8 and the enable signal ENB after time t28.
The time t29 when L rises is

[0103]

T28 = t25 + PWL ₋ ENBL = 13 + 20 = 33 (ns) t29 = t28 + lh ₋ min ₋ en = 33 + 0 = 33 (ns).

At time t when the clock GCK falls.
30, and the time t31 when the clock GCK rises,

[0105]

T30 = t27 + HL _- MAX _- B _- Y = 13 + 2 = 15 (ns) t31 = t25 + LH _- MIN _- A _- Y = 20.0 + 1.5 = 21.5 (ns) Becomes

Further, the G pulse width pwl _- gck at which the clock GCK at this time becomes the L level is

[0107]

[Number 31] _{pwl - gck = t31 - t30 =} 21.5 - a 15 = 6.5 (ns). Thus G pulse width, OR gate 6 C pulse width has passed through Pwh _- since narrower than const, the clock GCK is generated at this time is determined to be generated at the wrong time.

[0108]

According to the gated clock verification method of the first aspect of the present invention, the primary enable is known in which the timing between the clock signal output from the clock signal circuit which is the signal path of the primary clock and the primary clock is known. This is applied to the verification method of the gated clock generated by the gated clock circuit to which the enable signal output from the enable signal circuit to which the clock is guided is given, and the desired level of the clock signal based on the delay time of the clock signal circuit. The edge timing of the pulse of the clock signal is calculated, and the clock pulse width when the pulse of the desired level of the clock signal passes through the gated clock circuit is calculated from the edge timing of the pulse of the desired level of the clock signal and the delay time of the gated clock circuit. Calculate and enable The edge timing of the pulse of the desired level of the enable signal is calculated based on the delay time of the signal circuit and the primary enable clock, and the edge timing of the pulse of the desired level of the clock signal and the edge timing of the pulse of the desired level of the enable signal. And the delay time of the gated clock circuit, the gated clock pulse width of the gated clock output by the gated clock circuit is calculated, and when the gated clock pulse width is narrower than the clock pulse width, the timing of the enable signal is This is a method of determining that it is defective. In other words, when there is no error in the gated clock, the gated clock pulse width is equal to the pulse width of the clock signal that passes through the gated clock circuit, and when there is an error in the gated clock, the gated clock pulse width is Since the determination method is based on the fact that the pulse width is narrower than the pulse width of the clock signal, it is possible to accurately detect the error of the gated clock without increasing the verification time.

The gated clock verification method according to the second aspect of the present invention is a method for verifying a gated clock in an LSI to which a primary clock is externally applied. Therefore, the delay time of the clock signal circuit corresponds to the delay time of the signal path from the input terminal of the primary clock to the output of the clock signal.
The delay time of the enable signal circuit corresponds to the delay time from the input terminal of the primary clock to the output of the enable signal. Therefore, it is possible to accurately detect an error in the gated clock of the LSI to which the primary clock is given from the outside.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a gated clock verification method according to the present invention.

FIG. 2 is a circuit diagram showing a configuration which is a verification target of the first embodiment.

FIG. 3 is a timing chart showing a phase difference between a primary clock and a primary enable clock.

FIG. 4 is a timing chart of main signals in a verification target of the first embodiment.

FIG. 5 is a timing chart of main signals in a verification target of the first embodiment.

FIG. 6 is a timing chart of main signals in a verification target of the first embodiment.

FIG. 7 is a list showing the periods and pulse widths of the primary clock and the primary enable clock.

FIG. 8 is a list showing delay times of elements.

FIG. 9 is a circuit diagram showing a configuration that is a verification target of the second embodiment.

FIG. 10 is a timing chart of main signals in a verification target of the second embodiment.

FIG. 11 is a timing chart of main signals in a verification target of the second embodiment.

FIG. 12 is a list showing the periods and pulse widths of the primary clock and the primary enable clock.

FIG. 13 is a list showing delay times of elements.

FIG. 14 is a circuit diagram showing a configuration of a gated clock circuit.

FIG. 15 is a timing chart showing timings of various signals.

FIG. 16 is a circuit diagram showing a configuration of a gated clock circuit.

FIG. 17 is a timing chart showing timings of various signals.

FIG. 18 is a circuit diagram showing a configuration of a gated clock circuit.

FIG. 19 is a timing chart showing timings of various signals.

FIG. 20 is a circuit diagram showing a configuration of a gated clock circuit.

FIG. 21 is a timing chart showing timings of various signals.

FIG. 22 is a circuit diagram showing a configuration of a gated clock circuit.

FIG. 23 is a timing chart showing timings of various signals.

FIG. 24 is a circuit diagram showing a configuration of a gated clock circuit.

FIG. 25 is a timing chart showing timings of various signals.

FIG. 26 is a timing chart showing timings of various signals.

FIG. 27 is a circuit diagram showing a configuration when data transfer is performed by a completely synchronous method.

FIG. 28 is a timing chart of main signals in the configuration shown in FIG. 27.

FIG. 29 is a circuit diagram showing a configuration when data transfer is performed with a gated clock.

FIG. 30 is a timing chart of main signals in the configuration shown in FIG.

[Explanation of symbols]

 1 enable signal circuit 2 clock signal circuit 3 gated clock circuit 6 gated clock circuit CK clock signal EN enable signal CLK clock signal ENBL enable signal GCK gated clock MCK primary clock SCK primary enable clock

Claims (2)

[Claims] 1. A clock signal output from a clock signal circuit that is a signal path of a primary clock, and an enable signal output from an enable signal circuit to which a primary enable clock whose timing with the primary clock is known is introduced. In a method for verifying a gated clock generated by a given gated clock circuit, an edge timing of a pulse of a desired level of the clock signal is calculated based on a delay time of the clock signal circuit, and a desired level of the clock signal is calculated. From the edge timing of the pulse and the delay time of the gated clock circuit, calculate the clock pulse width when the pulse of the desired level of the clock signal passes through the gated clock circuit, the delay time of the enable signal circuit And the above Calculating the edge timing of the desired level pulse of the enable signal based on the primary enable clock, the edge timing of the desired level pulse of the clock signal, the edge timing of the desired level pulse of the enable signal, and The gated clock pulse width of the gated clock output from the gated clock circuit is calculated from the delay time of the gated clock circuit, and when the gated clock pulse width is narrower than the clock pulse width, the enable signal A method of verifying a gated clock, characterized in that the timing of is determined to be defective. 2. The gated clock verification method according to claim 1, wherein the gated clock is verified in an LSI to which the primary clock is externally applied.