JPH08181577A - Digital signal generator - Google Patents

Abstract

PURPOSE: To generate a digital signal similarly to the case with driving the generator by a clock signal frequency being a K-fold without changing the clock signal frequency. CONSTITUTION: Flip-flop circuits D1, D3, D5, D7, D9, D11, D13, D15 are connected in cascade to form a 1st shift register and flip-flop circuits D2, D4, D6, D8, D10, D12, D14 are connected in cascade to form a 2nd shift register. An exclusive OR gate E2 receives an output signal of the flip-flop circuits D14, D15 and provides an output signal subject to logic processing to the flip-flop D2. An exclusive OR gate E1 receives an output signal of the flip-flop circuits D13, D14 and provides an output signal subject to logic processing to the flip- flop D1. The 1st and 2nd shift registers are shifted and a pseudo random digital signal is obtained from a desired flip-flop.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to digital signal generators, and more particularly to digital signal generators for generating pseudo-random digital signals.

[0002]

2. Description of the Related Art Pseudo-random digital signals are used in various fields. For example, when testing an error in a communication line, a pseudo-random digital signal generated by the PRBS method is supplied to the communication line as a test digital signal and the output signal from this communication line is monitored. The pseudo-random digital signal can also be used to test various digital circuits.

FIG. 5 shows a conventional digital signal generator which generates a pseudo-random digital signal by the PRBS method. The D-type flip-flops D1 to D15 are connected in cascade, that is, the Q output terminal of the flip-flop of the previous stage is connected to the D input terminal of the flip-flop of the next stage to form a shift register. The exclusive OR gate is a logic circuit that performs an exclusive OR processing of the input signal and the output signal of the flip-flop D15, and supplies the processed output signal to the input terminal of the flip-flop D1. In addition,
Although not shown, a common clock signal is supplied to each clock terminal of the flip-flops D1 to D15.

In the circuit operation of FIG. 5, first, all the flip-flops D1 to D15 are preset to 1.
Next, the flip-flops D1 to D are driven by the clock signal.
The digital data stored in 15 are sequentially shifted.
This state is shown in Table 1.

[Table 1] In Table 1, 1 to 15 in the top row represent the flip-flop numbers, and the leftmost vertical row represents the state numbers corresponding to the number of clock generations. That is, in the first state 1, all the storage states of the flip-flops D1 to D15, that is, the output digital states are all 1. Next, when the digital signal accumulated by the clock signal is shifted by one stage to the state 2, the digital signal accumulated only in the flip-flop D1 becomes 0, and the digital signals of the other flip-flops become 1. Hereinafter, the same operation is sequentially repeated. The output signal is the flip-flop D15.
Is obtained from the output terminal 10 for receiving the output signal of. In the digital signal generator of FIG. 5, since there are 15 stages of flip-flops, a pseudo-random digital pattern (excluding the case where all are 0) makes one round by a clock signal of 2 15 −1. Of course, the output signal may be obtained from one or more arbitrary flip-flops depending on the application.

When a communication line is tested using a pseudo-random digital signal generated by the PRBS method,
The pseudo random digital signal may be further processed by the CRC-5 method and then supplied to the communication line. In this CRC-5 method, for example, a CRC message
A block (CMB) is a continuous 3151-bit sequence that starts at the first bit of the first frame and ends at the 784th bit of the fourth frame. Message block check bit (CRC-5 bit) e1,
e2, e3, e4 and e5 are placed in the last 5 bits of the multiframe. The check bit strings e1 to e5 transmitted in the Sth multiframe are obtained by multiplying the Sth CMB by X ** 5 (X to the 5th power), and then using the generator polynomial X ** 5 + X ** 4 + X ** 2 + 1. It is the remainder of the division (modulo 2). Such a check bit string e1
FIG. 6 shows a conventional circuit for generating a digital signal of .about.e5.

In FIG. 6, input terminal 22 receives a pseudo-random digital signal from output terminal 10 of FIG. Exclusive-OR gate 23 receives the pseudo-random digital signal from input terminal 22 and provides its output signal to the D input terminal of flip-flop D21 and exclusive-OR gates 24 and 26. Flip flop 2
The Q output signal of 1 is supplied to the D input terminal of the flip-flop D22, and the Q output signal of the flip-flop D22 is supplied to the exclusive OR gate 24. The flip-flop D23 receives the output signal of the exclusive OR gate 24 at its D input terminal and receives its Q output signal at the flip-flop D23.
It is supplied to the 24 D input terminals. Flip flop D2
The Q output signal of 4 is supplied to the exclusive OR gate 26 and its output signal is supplied to the flip-flop D25. The Q output signal of flip-flop D25 is exclusive OR
Return to gate 23. In these circuit configurations, the same clock signal as that used in FIG.
By supplying to D25, every 8th clock,
The above-mentioned check bit string e1 to be the CRC-5 method
e5 to flip-flops D25, D24, D23,
It can be obtained from the Q output terminals of D22 and D21.

[0007]

By the way, in order to increase the bit rate of the pseudo-random digital signal obtained from the digital signal generator of FIG. 5, it is supplied to the flip-flop in each digital signal generator. The clock frequency should be increased. However, there are cases where the clock frequency cannot be changed due to the relationship with the device used with this digital signal generator. In addition, even if the clock frequency can be set arbitrarily, due to the operating speed limit of each circuit element,
The circuit may not operate above a certain frequency.

Therefore, an object of the present invention is to provide a digital signal generator capable of generating a digital signal similar to that when driven at a clock frequency of a predetermined multiple without changing the clock frequency. Another object of the present invention is to provide a digital signal generator capable of generating a digital signal that equivalently changes at a speed equal to or higher than the operating speed of circuit components.

[0009]

SUMMARY OF THE INVENTION A digital signal generator of the present invention comprises N (N is an integer greater than or equal to 2) flip-flops and K (K is an integer less than N) exclusive OR gates. It is equipped with The P-th flip-flop (P is a number sequentially increasing from 1 by 1 to N−K) supplies its output signal to the input terminal of the K + P-th flip-flop. Further, the Q-th (Q is a number sequentially increasing from 1 to 1 up to K) exclusive OR gate supplies its output signal to the input terminal of the Q-th flip-flop, and N-
It receives the output signals of the K + Q-1th and NK + Qth flip-flops.

[0010]

1 is a block diagram of a digital signal generator of the present invention which produces a digital signal similar to the pseudo-random digital signal produced by the digital signal generator shown in FIG. D-type flip-flops D1, D3, D5, D
7, D9, D11, D13 and D15 are cascaded to form a first shift register. Similarly, the D-type flip-flops D2, D4, D6, D8, D10, D12 and D14 are cascaded to form a second shift register. 1, the first and second shift registers are intricately shown and the flip-flops D1 to D15 are sequentially arranged in order to compare with the conventional example of FIG.
The exclusive OR gate E2, which is a logic circuit that performs an exclusive OR operation, receives the output signals of the final stage flip-flops D14 and D15 of the first and second shift registers, and performs an exclusive OR processing. The output signal is supplied to the D input terminal of the first-stage flip-flop D2 of the second shift register. The exclusive OR gate E1 receives the output signal of the flip-flop D13 of the second final stage of the first shift register and the output signal of the flip-flop D14 of the final stage of the second shift register, and outputs an exclusive signal. The output signal subjected to the logical OR processing is supplied to the D input terminal of the first stage flip-flop D1 of the first shift register.

In the circuit of FIG. 1, although not shown, a clock signal is supplied to each of the flip-flops D1 to D15, and a shift operation is performed in each shift register. The accumulated contents of each flip-flop at this time, that is,
The Q output signal is shown in Table 2.

[Table 2] As can be seen from this table, the exclusive OR gates E1 and E2 perform two feedbacks at the same time, and the flip-flop D
1 and D2 simultaneously receive the digital signal obtained by the feedback. Therefore, shifting one clock of the flip-flops D1 to D15 is equivalent to simultaneously shifting two clocks.

This operation will be described in more detail with reference to Table 2.
Is a table having the same configuration as Table 1 showing the operation of FIG. Table 1
And as can be understood from the comparison of Table 2, the state 1 of Table 2 is the same as the state 1 of Table 1, the state 2 of Table 2 is the same as the state 3 of Table 1, and so on. The Kth state is
This is the same as the 2K-1th state in Table 1. That is, each state in Table 2 is the same as the alternate state of Table 1. Therefore, if the clock frequencies of the digital signal generators of FIGS. 1 and 5 are the same, the digital signal generator of FIG. 1 of the present invention produces two pseudo random digital signals as compared with the conventional case of FIG. It will change at twice the speed. Although the digital signal generator of FIG. 1 cannot obtain the even-numbered states of Table 1, if a digital signal of the odd-numbered states is required, for example, the check bit string of the CRC-5 method shown in FIG. When generating, the even numbered digital signals are not required.

Therefore, the digital signal generator of the present invention shown in FIG. 1 can generate a pseudo-random digital signal whose rate of change is twice as fast as the conventional one, by the same clock frequency as the conventional one. Also, because the clock frequency is the same,
By using the clock signal corresponding to the limit operating speed of the circuit element, it is possible to generate a pseudo-random digital signal that changes at a speed twice the limit operating speed of the circuit element.

In the digital signal generator of the present invention shown in FIG. 1, the digital signal train obtained from the output terminal 14 for outputting the Q output signal of the flip-flop D15 is different from that in FIG. The signal generator of FIG. 6 cannot be used to generate the check bit string. Therefore, in order to perform the processing of the CRC-5 method using the pseudo random digital signal generated in the present invention, the signal generator shown in FIG. 2 is used instead of the signal generator shown in FIG.

In FIG. 2, exclusive OR gate 34
Receives the output signal of the flip-flop D15 of FIG. 1 through terminals 34 and 14 and receives the exclusive OR gate 32.
Receives the output signal of flip-flop D14 of FIG. 1 via terminals 28 and 16. The D-type flip-flop 21 receives the output signal of the exclusive OR gate 32, and the exclusive OR gate 36 receives the output signal of the flip-flop D21 and the output signal of the exclusive OR gate 32. Flip-flop D22 receives the output signal of exclusive-OR gate 34, and exclusive-OR gate 38 receives the output signals of flip-flop D22 and exclusive-OR gate 34. Flip-flop D23 receives the output signal of exclusive-OR gate 36, and exclusive-OR gate 42 receives the output signals of flip-flop D23 and exclusive-OR gate 32.

The flip-flop D24 receives the output signal of the exclusive OR gate 38, and the exclusive OR gate 44 receives the output signals of the flip-flop D24 and the exclusive OR gate 34. The output signal of the flip-flop D25 is supplied to the exclusive OR gate 34,
The output signal of the exclusive OR gate 44 is supplied to the exclusive OR gate 32. With such a configuration, the above-described check bit strings e1 to e5, which are the CRC-5 method, are flip-flops D25, D24, D every four clocks.
It can be obtained from the Q output terminals of 23, D22 and D21. This check bit string has the same contents as in the case of FIG. Therefore, even if a pseudo-random digital signal is generated using the digital signal generator of the present invention, C
The RC-5 technique can be used.

FIG. 3 is a block diagram of a second embodiment of the digital signal generator of the present invention. In the first embodiment of the present invention shown in FIG. 1, a pseudo-random digital signal having a speed twice that of the case of FIG. 5 is generated every one clock, but in the second embodiment of FIG. Generates a pseudo-random digital signal at a speed of. Therefore, flip-flop D
The connection relationship of 1 to D15 is the same as in the case of FIG. However, exclusive OR gate E1 is flip-flop D1
After receiving the output signals of 1 and D12 and performing OR processing,
It is supplied to the input terminal of the flip-flop D1. Exclusive-OR gate E2 has flip-flops D12 and D12.
It receives the output signal of 13 and supplies the logical sum output signal to the input terminal of the flip-flop D2. Also exclusive or
The gate E3 receives the output signals of the flip-flops D13 and D14 and supplies an OR output signal to the input terminal of the flip-flop D3, and the exclusive OR gate E4 is
The output signals of the flip-flops D14 and D15 are received and the logical sum output signal is supplied to the input terminal of the flip-flop D4.

Exclusive OR gates E1, E2, E3, and E4 provide four feedbacks simultaneously, and flip-flop D
1, D2, D3 and D4 simultaneously receive digital signals obtained by feedback. Therefore, flip-flop D
The shift of 1 clock of 1 to D15 is equivalent to the shift of 4 clocks being performed at the same time. Thus, a pseudo-random digital signal that is four times faster than the conventional digital signal generator of FIG. 5 is obtained.

A third embodiment, which is a generalization of the first and second embodiments of the present invention, is shown in FIG. In this embodiment, N flip-flops and K exclusive-OR gates are used to generate a pseudo-random digital signal that is K times faster than the conventional example. Therefore, N flips
Every K flops are connected. That is, the output signal of the flip-flop D1 is supplied to the (K + 1) th flip-flop, the output signal of the flip-flop D2 is supplied to the (K + 2) th flip-flop, and the same connection is made. Do not connect the output terminal of another flip-flop to the input terminal of another flip-flop.

The exclusive OR gate E1 is NK
The output signals of the first and (N−K + 1) th flip-flops are received, the exclusive OR processing is performed, and the processed output signal is supplied to the input terminal of the flip-flop D1. Less than,
Similarly, the (K-1) th exclusive OR gate receives the output signals of the (N-2) th and (N-1) th flip-flops and outputs the signal obtained by the exclusive OR processing to the (K-1) th flip-flop. And the Kth exclusive OR gate is
The output signals of the (N-1) th and Nth flip-flops are received, and the signals subjected to the exclusive OR processing are input to the Kth flip-flop.

In the embodiment of FIG. 4, K exclusive OR gates provide K feedbacks simultaneously, and flip-flop D
1 to DK simultaneously receive digital signals obtained by feedback. Therefore, the shift of N flip-flops by one clock is equivalent to the shift of K clocks at the same time, and the pseudo-random number is K times faster than the conventional digital signal generator of FIG. A digital signal is obtained.

The general construction of the embodiment shown in FIG. 4 is as follows. That is, N (N is an integer of 2 or more) flip-flops and K (K is an integer smaller than N) exclusive OR gates are provided. Pth (P
Are sequentially increased from 1 by 1 and the number of flip-flops from N to K) is equal to the output signal of the K + Pth flip-flop.
Supply to the input terminal of the flop. Also, the Qth (Q is 1
The number of exclusive OR gates sequentially increasing by 1 from 1 to K) supplies its output signal to the input terminal of the Qth flip-flop, and the N−K + Q−1th and N−K + Qth flip-flops. Receives the output signal of the flop.

[0023]

As described above, according to the present invention, a clock signal having the same frequency as that of the prior art can be used to generate a digital signal whose rate of change is K times that of the prior art. Therefore, even if the clock frequency cannot be changed, or even if the circuit does not operate at a certain frequency or higher due to the operating speed limit of each circuit element, it is possible to generate a digital signal with a changing speed of K times.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a digital signal generator that generates a check bit string of the CRC-5 method using the pseudo random digital signal generated in FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional digital signal generator that generates a pseudo-random digital signal.

6 is a circuit diagram of a conventional digital signal generator that generates a check bit string of a CRC-5 method by using a random digital signal generated by the conventional circuit of FIG.

[Description of Reference Signs] D1 to D (N) flip-flops E1 to E (K) exclusive OR gates

Claims (1)

[Claims] 1. N (N is an integer of 2 or more) flips
It has a flop and K exclusive OR gates (K is an integer smaller than N), and it is the P-th (P is a number sequentially increasing from 1 to NK).
The flip-flop of the above supplies the output signal to the input terminal of the K + Pth flip-flop, and the Q-th (Q is a number sequentially increasing from 1 to K) exclusive OR gate is , Its output signal is supplied to the input terminal of the Qth flip-flop, and N−K + Q−
A digital signal generator which receives the output signals of the first and NK + Qth flip-flops.