JPH08186382A - Lamination electronic component - Google Patents
Lamination electronic componentInfo
- Publication number
- JPH08186382A JPH08186382A JP6328107A JP32810794A JPH08186382A JP H08186382 A JPH08186382 A JP H08186382A JP 6328107 A JP6328107 A JP 6328107A JP 32810794 A JP32810794 A JP 32810794A JP H08186382 A JPH08186382 A JP H08186382A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- land
- laminated
- laminated electronic
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Ceramic Capacitors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、電子機器に用いられる
積層電子部品、例えば、移動体通信機用のモジュール、
半導体パッケージ、およびハイブリッドIC等に搭載さ
れる積層電子部品に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component used in electronic equipment, for example, a module for a mobile communication device,
The present invention relates to a semiconductor package, a laminated electronic component mounted on a hybrid IC or the like.
【0002】[0002]
【従来の技術】従来の積層電子部品の構成を、回路素子
としてコンデンサ部を備えるものを例に採り、図4、図
5を用いて説明する。図4、図5において、31は積層
電子部品であり、シート成形体として、セラミックシー
ト2を複数枚積層してなる積層体10を備えるものであ
り、積層体10は、二つの主面10aを有する。ここ
で、各セラミックシート2には、厚み方向に沿って貫通
孔が形成され、その貫通孔の内部に充填等の方法により
設けられた導体が、セラミックシート2の積層方向に連
続して配置されることにより、立体配線3、4が形成さ
れる。また、各セラミックシート2の一方の主面には、
印刷等により設けられた導体からなる電極5が配置さ
れ、セラミックシート2の積層方向において、互いに対
向して積層される複数の電極5間にコンデンサ部が形成
される。さらに、立体配線3、4の、セラミックシート
2の一方の主面に露出する露出部3a、4a上、および
露出部3a、4aの周辺に、印刷等の方法により導体が
設けられ、ランド6が形成される。ランド6は、引出線
7を介して電極5に接続される。このとき、互いに対向
する二枚のセラミックシート2において、一方のセラミ
ックシート2上では、露出部3a上に形成されるランド
6が電極5に接続され、他方のセラミックシート2上で
は、露出部4a上に形成されるランド6が電極5に接続
される。また、立体配線3、4の各一端は、積層体10
の一方の主面10aに引き出され、主面10a上の配線
や抵抗等からなる表面回路(図示せず)に接続される。
このように構成される積層電子部品31は、プリント配
線基板(図示せず)に実装され、電極5間に形成される
コンデンサ部が、プリント配線基板上の回路配線(図示
せず)に接続される。2. Description of the Related Art The structure of a conventional laminated electronic component will be described with reference to FIGS. 4 and 5, taking as an example a circuit element having a capacitor section. In FIGS. 4 and 5, reference numeral 31 denotes a laminated electronic component, which is provided with a laminated body 10 formed by laminating a plurality of ceramic sheets 2 as a sheet molded body. The laminated body 10 has two main surfaces 10a. Have. Here, through holes are formed in each ceramic sheet 2 along the thickness direction, and conductors provided inside the through holes by a method such as filling are continuously arranged in the stacking direction of the ceramic sheets 2. By doing so, the three-dimensional wirings 3 and 4 are formed. Also, on one main surface of each ceramic sheet 2,
Electrodes 5 made of a conductor provided by printing or the like are arranged, and a capacitor portion is formed between a plurality of electrodes 5 that are laminated facing each other in the stacking direction of the ceramic sheets 2. Further, a conductor is provided by a method such as printing on the exposed portions 3a, 4a exposed on one main surface of the ceramic sheet 2 of the three-dimensional wiring 3, 4, and around the exposed portions 3a, 4a, and the land 6 is formed. It is formed. The land 6 is connected to the electrode 5 via the lead wire 7. At this time, in the two ceramic sheets 2 facing each other, the land 6 formed on the exposed portion 3a is connected to the electrode 5 on one of the ceramic sheets 2 and the exposed portion 4a on the other ceramic sheet 2. The land 6 formed above is connected to the electrode 5. In addition, one end of each of the three-dimensional wirings 3 and 4 has a laminated body 10
It is drawn out to one main surface 10a and is connected to a surface circuit (not shown) composed of wiring and resistors on the main surface 10a.
The multilayer electronic component 31 thus configured is mounted on a printed wiring board (not shown), and the capacitor portion formed between the electrodes 5 is connected to the circuit wiring (not shown) on the printed wiring board. It
【0003】[0003]
【発明が解決しようとする課題】ところが、このように
構成される積層電子部品31においては、製造工程でセ
ラミックシート2を積層する際、対向する二枚のセラミ
ックシート2間に位置ずれが生じることがあった。ま
た、積層体10を焼成する際、対向する二枚のセラミッ
クシート2を構成するセラミックの収縮量の相違から、
焼成後、これらセラミックシート2間で、立体配線3、
4とランド6との位置がずれることがあった。こうした
ことによって、図6に示すように、一方のセラミックシ
ート2の対向面上の立体配線3、4の露出部3b、4b
と、他方のセラミックシート2の対向面上のランド6と
が重なり合う部分が無くなったり、極めて小さくなった
りして、両者の接続がなされず、それにより、コンデン
サ部において、所望の容量が得られなくなる恐れがあっ
た。とくに、立体配線3、4が引き出される主面10a
側に配置されるセラミックシート2間で位置ずれが生じ
た場合、積層電子部品31が実装されるプリント配線基
板上の回路配線と、コンデンサ部との接続がなされず、
容量がほとんど期待できなくなる恐れがあった。However, in the laminated electronic component 31 configured as described above, when the ceramic sheets 2 are laminated in the manufacturing process, a displacement occurs between the two ceramic sheets 2 facing each other. was there. Further, when firing the laminated body 10, due to the difference in the shrinkage amount of the ceramics forming the two ceramic sheets 2 facing each other,
After firing, the three-dimensional wiring 3, between these ceramic sheets 2,
The positions of the land 4 and the land 6 sometimes deviated. As a result, as shown in FIG. 6, the exposed portions 3b, 4b of the three-dimensional wiring 3, 4 on the facing surface of the one ceramic sheet 2 are exposed.
And the land 6 on the opposite surface of the other ceramic sheet 2 does not overlap with each other or becomes extremely small, so that the two are not connected, and as a result, the desired capacitance cannot be obtained in the capacitor section. I was afraid. In particular, the main surface 10a from which the three-dimensional wirings 3 and 4 are drawn out
When a displacement occurs between the ceramic sheets 2 arranged on the side, the circuit wiring on the printed wiring board on which the laminated electronic component 31 is mounted and the capacitor portion are not connected,
There was a risk that the capacity could hardly be expected.
【0004】また、立体配線3、4の露出部3b、4b
とランド6とが重なり合う部分を確保するために、ラン
ド6の面積を拡大すると、セラミックシート2上におい
て、抵抗やコイル等の他の回路素子や回路配線を配置可
能な空間が削減され、これにより、積層電子部品の高密
度化を妨げることとなってしまった。The exposed portions 3b, 4b of the three-dimensional wiring 3, 4 are also provided.
If the area of the land 6 is increased in order to secure a portion where the land and the land 6 overlap with each other, the space on the ceramic sheet 2 in which other circuit elements such as a resistor and a coil and circuit wiring can be arranged is reduced. , Which has hindered the densification of laminated electronic components.
【0005】そこで、本発明においては、積層体を構成
するシート成形体(セラミックシート)間に多少の位置
ずれが生じても、立体配線の露出部とランドとが重なり
合う部分が確保され、両者が確実に接続されることによ
って所望の特性が得られ、しかも、セラミックシート上
の、回路素子や回路配線を配置可能な空間が確保される
ことによって、高密度化が実現される積層電子部品を提
供することを目的とする。Therefore, in the present invention, even if a slight displacement occurs between the sheet molded bodies (ceramic sheets) forming the laminated body, a portion where the exposed portion of the three-dimensional wiring and the land overlap each other is secured, and both of them are secured. Providing a laminated electronic component that achieves the desired characteristics by being securely connected, and that secures a space on the ceramic sheet in which circuit elements and circuit wiring can be placed, thereby achieving high density The purpose is to do.
【0006】[0006]
【課題を解決するための手段】上記の目的を達成するた
め、本発明においては、シート成形体を複数枚積層して
なる積層体と、前記シート成形体間に設けられる回路素
子と、前記シート成形体を厚み方向に沿って貫通する貫
通孔の内部に設けられた導体からなり、前記積層体の少
なくとも一方の主面に引き出される立体配線と、前記シ
ート成形体上の、前記立体配線の露出部と該露出部周辺
との双方、または、どちらか一方に設けられた導体から
なり、前記回路素子に接続されるランドと、を備える積
層電子部品において、前記積層体の一方の主面側から他
方の主面側にかけて、前記ランドの面積を連続的または
段階的に変化させたことを特徴とする。In order to achieve the above object, in the present invention, a laminate formed by laminating a plurality of sheet moldings, a circuit element provided between the sheet moldings, and the sheet. A three-dimensional wiring formed of a conductor provided inside a through-hole penetrating the molded body along the thickness direction and drawn out to at least one main surface of the laminate, and an exposure of the three-dimensional wiring on the sheet molded body. And a periphery of the exposed part, or a land provided with a conductor provided on either side and connected to the circuit element, in a laminated electronic component, from one main surface side of the laminated body. It is characterized in that the area of the land is changed continuously or stepwise toward the other main surface side.
【0007】[0007]
【作用】本発明によれば、積層電子部品を構成する積層
体の一方の主面側から他方の主面側にかけて、ランドの
面積が連続的または段階的に大きくなっている。したが
って、積層体のどちらか一方の主面側においては、互い
に対向する二枚のシート成形体間に多少の位置ずれが生
じても、これらのシート成形体の立体配線の露出部とラ
ンドとが重なり合う部分が必ず形成され、立体配線とラ
ンドとが確実に接続される。これによって、積層電子部
品内の回路素子と、積層電子部品が実装されるプリント
配線基板上の回路配線との接続が確実になされ、積層電
子部品において所望の特性が得られる。According to the present invention, the land area is continuously or stepwise increased from one main surface side to the other main surface side of the laminated body constituting the laminated electronic component. Therefore, on one of the main surface sides of the laminated body, even if there is some misalignment between the two sheet molded bodies facing each other, the exposed portion of the three-dimensional wiring and the land of these sheet molded bodies are not separated from each other. The overlapping portion is always formed, and the three-dimensional wiring and the land are surely connected. As a result, the circuit element in the laminated electronic component and the circuit wiring on the printed wiring board on which the laminated electronic component is mounted are securely connected, and desired characteristics can be obtained in the laminated electronic component.
【0008】また、本発明によれば、積層電子部品を構
成する積層体のどちらか一方の主面側においては、シー
ト成形体上のランドの面積が比較的小さいので、回路素
子や回路配線を配置可能な空間が削減されることはな
く、設計の自由度が損われない。したがって、積層電子
部品の高密度化が実現される。Further, according to the present invention, since the area of the land on the sheet molded body is relatively small on either one of the main surfaces of the laminated body constituting the laminated electronic component, the circuit element and the circuit wiring are The space that can be arranged is not reduced, and the degree of freedom in design is not impaired. Therefore, high density of the laminated electronic component is realized.
【0009】[0009]
【実施例】本発明の一実施例にかかる積層電子部品の構
成を、図1、図2を用いて説明する。なお、従来の積層
電子部品と同一または相当する部分には、同一の符号を
付し、その説明を省略する。EXAMPLE The structure of a laminated electronic component according to an example of the present invention will be described with reference to FIGS. The same or corresponding parts as those of the conventional laminated electronic component are designated by the same reference numerals, and the description thereof will be omitted.
【0010】図1、図2において、1は積層電子部品で
あり、セラミックシート2を複数枚積層してなる積層体
10の一方の主面10a側の層、すなわち上層8から、
他方の主面10a側の層、すなわち下層9にかけて、ラ
ンド6の面積が連続的に大きくなっている。1 and 2, reference numeral 1 denotes a laminated electronic component, which is a layer on the one main surface 10a side of a laminated body 10 formed by laminating a plurality of ceramic sheets 2, that is, an upper layer 8.
The area of the land 6 continuously increases in the layer on the other main surface 10a side, that is, in the lower layer 9.
【0011】このように構成される積層電子部品1によ
れば、下層9において、ランド6の面積が比較的大き
く、互いに対向する二枚のセラミックシート2間におい
て、立体配線3、4の対向面上の露出部3b、4b(図
6)と、ランド6とが重なり合う部分が大きく、これに
より、製造工程でセラミックシート2を積層する際に、
セラミックシート2間で多少の位置ずれが生じたり、焼
成の際、セラミックの収縮量の相違によって、セラミッ
クシート2間で、立体配線3、4とランド6との位置が
ずれたりしても、立体配線3、4とランド6との接続が
確実になされる。したがって、電極5間に形成されるコ
ンデンサ部が、ランド6および立体配線3、4を介し
て、積層体10の主面10a上の表面回路(図示せず)
に確実に接続される。そして、積層電子部品1がプリン
ト配線基板に実装される際、コンデンサ部は表面回路を
介して、プリント配線基板上の回路配線(図示せず)に
確実に接続され、これにより、コンデンサ部において所
望の容量が得られる。According to the laminated electronic component 1 having the above-described structure, in the lower layer 9, the land 6 has a relatively large area, and between the two ceramic sheets 2 facing each other, the facing surfaces of the three-dimensional wirings 3 and 4 are opposed. The exposed portions 3b and 4b (FIG. 6) on the upper side and the land 6 overlap with each other in a large area, and when the ceramic sheets 2 are laminated in the manufacturing process,
Even if some displacement occurs between the ceramic sheets 2 or the three-dimensional wirings 3 and 4 and the lands 6 are displaced between the ceramic sheets 2 due to the difference in the shrinkage amount of the ceramics during firing, The wirings 3 and 4 and the land 6 are securely connected. Therefore, the capacitor portion formed between the electrodes 5 has a surface circuit (not shown) on the main surface 10a of the laminated body 10 via the land 6 and the three-dimensional wirings 3 and 4.
Securely connected to. Then, when the laminated electronic component 1 is mounted on the printed wiring board, the capacitor section is securely connected to the circuit wiring (not shown) on the printed wiring board via the surface circuit. Capacity is obtained.
【0012】また、上層8を構成するセラミックシート
2上においては、ランド6の面積が比較的小さく、抵抗
やコイル等の他の回路素子や、回路配線を配置する空間
が確保されるため、設計の自由度が損われず、これによ
り、積層電子部品1の高密度化が実現される。Further, on the ceramic sheet 2 which constitutes the upper layer 8, the area of the land 6 is relatively small and a space for arranging other circuit elements such as resistors and coils and circuit wiring is secured, so that the design The degree of freedom of the laminated electronic component 1 is not impaired, and the high density of the laminated electronic component 1 is thereby realized.
【0013】ここで、本発明の他の実施例を図3を用い
て説明する。なお、図3において、図1と同一または相
当する部分には、同一の符号を付し、その説明は省略す
る。図3において、21は積層電子部品であり、積層体
10の上層8から下層9にかけて、ランド6の面積が段
階的に大きくなっている。すなわち、同じ面積の複数の
ランド6からなるランド群11が複数形成され、これら
ランド群11が、面積の小さいものから順に配置される
ものである。このように構成される積層電子部品21に
おいても、積層電子部品1と同様の効果が得られる。Now, another embodiment of the present invention will be described with reference to FIG. In FIG. 3, parts that are the same as or correspond to those in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted. In FIG. 3, reference numeral 21 is a laminated electronic component, and the area of the land 6 is gradually increased from the upper layer 8 to the lower layer 9 of the laminated body 10. That is, a plurality of land groups 11 including a plurality of lands 6 having the same area are formed, and these land groups 11 are arranged in order from the smallest area. Also in the laminated electronic component 21 configured in this way, the same effect as that of the laminated electronic component 1 can be obtained.
【0014】なお、上記二つの実施例においては、シー
ト成形体としてセラミックシートを用いる場合について
説明したが、セラミック以外の材料からなるシート成形
体を複数枚積層して積層体を形成する場合にも、本発明
を適用できる。In the above two embodiments, the case where the ceramic sheet is used as the sheet molded body has been described. However, when a plurality of sheet molded bodies made of a material other than ceramic are laminated to form a laminated body. The present invention can be applied.
【0015】また、上記二つの実施例においては、回路
素子としてコンデンサ部を内部に備える積層電子部品に
ついて説明したが、コンデンサ部以外に、例えば抵抗や
コイル等の回路素子を内部に備える積層電子部品にも、
本発明を適用できる。Further, in the above-mentioned two embodiments, the laminated electronic component having the capacitor portion as the circuit element therein has been described. However, in addition to the capacitor portion, the laminated electronic component internally having the circuit element such as a resistor and a coil. Also,
The present invention can be applied.
【0016】さらに、上記二つの実施例においては、立
体配線が積層体の一方の主面にのみ引き出される場合に
ついて説明したが、積層体の双方の主面に引き出される
立体配線を備える積層電子部品にも、本発明を適用でき
る。Further, in the above two embodiments, the case where the three-dimensional wiring is drawn out only on one main surface of the laminated body has been described, but the laminated electronic component having the three-dimensional wiring drawn out on both main surfaces of the laminated body is described. Also, the present invention can be applied.
【0017】また、上記二つの実施例においては、立体
配線の露出部に対して、回路素子を構成する電極に接続
されるものであるか否かに関わらず、すべてにランドを
設ける場合について説明したが、回路素子を構成する電
極に接続される露出部に対してのみランドを設け、回路
素子を構成する電極に接続されない露出部に対してはラ
ンドを設けない場合にも、本発明を適用できる。Further, in the above two embodiments, the case where the land is provided on the exposed portion of the three-dimensional wiring regardless of whether or not it is connected to the electrode forming the circuit element will be described. However, the present invention is also applied to the case where the land is provided only for the exposed portion connected to the electrode forming the circuit element and the land is not provided for the exposed portion not connected to the electrode forming the circuit element. it can.
【0018】さらに、上記二つの実施例においては、積
層体の主面に、配線や抵抗等からなる表面回路が設けら
れる場合について説明したが、積層体に表面回路が設け
られず、実装の際には、積層体の主面に引き出された立
体配線の各一端が、プリント配線基板上の回路配線に直
接接続される積層電子部品にも、本発明を適用できる。Further, in the above two embodiments, the case where the main surface of the laminated body is provided with the surface circuit including the wiring, the resistance and the like has been described, but the laminated body is not provided with the surface circuit and is mounted at the time of mounting. In addition, the present invention can be applied to a laminated electronic component in which one end of each of the three-dimensional wirings drawn out to the main surface of the laminated body is directly connected to the circuit wiring on the printed wiring board.
【0019】[0019]
【発明の効果】本発明にかかる積層電子部品によれば、
シート成形体を複数枚積層してなる積層体の、一方の主
面側から他方の主面側にかけて、ランドの面積が連続的
または段階的に大きくなっている。したがって、積層体
のどちらか一方の主面側においては、互いに対向する二
枚のシート成形体間で、立体配線の対向面上の露出部と
ランドとが重なり合う部分が大きい。これにより、製造
工程でシート成形体を積層する際に、シート成形体間で
多少の位置ずれが生じても、立体配線とランドとの接続
が確実になされる。また、シート成形体がセラミックか
ら構成される場合に、積層体を焼成する際、セラミック
の収縮量の相違から、シート成形体間で立体配線とラン
ドとの位置がずれても、立体配線とランドとの接続が確
実になされる。したがって、積層電子部品がプリント配
線基板に実装される際、積層電子部品内の回路素子が、
ランドおよび立体配線を介して、プリント配線基板上の
回路配線に確実に接続され、これにより、積層電子部品
において所望の特性が得られる。According to the laminated electronic component of the present invention,
The area of the land increases continuously or stepwise from one main surface side to the other main surface side of a laminated body formed by laminating a plurality of sheet molded bodies. Therefore, on one of the main surfaces of the laminated body, between the two sheet moldings facing each other, the exposed portion on the facing surface of the three-dimensional wiring and the land overlap with each other. Thereby, when stacking the sheet molded bodies in the manufacturing process, even if a slight positional deviation occurs between the sheet molded bodies, the connection between the three-dimensional wiring and the land can be ensured. Further, when the sheet molded body is made of ceramic, when the laminated body is fired, even if the positions of the three-dimensional wiring and the land are deviated between the sheet molded bodies due to the difference in the shrinkage amount of the ceramic, the three-dimensional wiring and the land The connection with is surely made. Therefore, when the laminated electronic component is mounted on the printed wiring board, the circuit element in the laminated electronic component is
It is surely connected to the circuit wiring on the printed wiring board via the land and the three-dimensional wiring, whereby desired characteristics can be obtained in the laminated electronic component.
【0020】また、本発明にかかる積層電子部品によれ
ば、積層体のどちらか一方の主面側に配置されるランド
の面積が比較的小さく、他の回路素子や回路配線を配置
する空間が確保されるため、設計の自由度が損われず、
これにより、積層電子部品の高密度化が実現される。Further, according to the laminated electronic component of the present invention, the area of the land arranged on one of the main surfaces of the laminated body is relatively small, and the space for arranging other circuit elements and circuit wiring is provided. Since it is secured, the degree of freedom in design is not impaired,
As a result, high density of the laminated electronic component is realized.
【図1】本発明の一実施例にかかる積層電子部品の要部
断面図である。FIG. 1 is a cross-sectional view of essential parts of a laminated electronic component according to an embodiment of the present invention.
【図2】本発明の一実施例にかかる積層電子部品の要部
分解斜視図である。FIG. 2 is an exploded perspective view of essential parts of a laminated electronic component according to an embodiment of the present invention.
【図3】本発明の他の実施例にかかる積層電子部品の要
部断面図である。FIG. 3 is a cross-sectional view of essential parts of a laminated electronic component according to another embodiment of the present invention.
【図4】従来の積層電子部品の要部断面図である。FIG. 4 is a sectional view of a main part of a conventional laminated electronic component.
【図5】従来の積層電子部品の要部分解斜視図である。FIG. 5 is an exploded perspective view of essential parts of a conventional laminated electronic component.
【図6】図4に示す積層電子部品の部分拡大図である。6 is a partially enlarged view of the laminated electronic component shown in FIG.
1、21 積層電子部品 2 セラミックシート(シー
ト成形体) 3、4 立体配線 3a、4a 露出部 6 ランド 10 積層体 10a 主面1, 21 Laminated electronic component 2 Ceramic sheet (sheet molded body) 3, 4 Three-dimensional wiring 3a, 4a Exposed part 6 Land 10 Laminated body 10a Main surface
Claims (1)
体と、 前記シート成形体間に設けられる回路素子と、 前記シート成形体を厚み方向に沿って貫通する貫通孔の
内部に設けられた導体からなり、前記積層体の少なくと
も一方の主面に引き出される立体配線と、 前記シート成形体上の、前記立体配線の露出部と該露出
部周辺との双方、または、どちらか一方に設けられた導
体からなり、前記回路素子に接続されるランドとを備え
る積層電子部品において、 前記積層体の一方の主面側から他方の主面側にかけて、
前記ランドの面積を連続的または段階的に変化させたこ
とを特徴とする積層電子部品。1. A laminate formed by laminating a plurality of sheet compacts, a circuit element provided between the sheet compacts, and a through hole penetrating the sheet compact in the thickness direction. Provided on at least one of the main surfaces of the laminated body, and the exposed portion of the three-dimensional wiring and the periphery of the exposed portion on the sheet molded body, or one of them. In a laminated electronic component comprising a conductor and a land connected to the circuit element, from one main surface side of the laminate to the other main surface side,
A laminated electronic component, wherein the area of the land is changed continuously or stepwise.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6328107A JPH08186382A (en) | 1994-12-28 | 1994-12-28 | Lamination electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6328107A JPH08186382A (en) | 1994-12-28 | 1994-12-28 | Lamination electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08186382A true JPH08186382A (en) | 1996-07-16 |
Family
ID=18206581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6328107A Pending JPH08186382A (en) | 1994-12-28 | 1994-12-28 | Lamination electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08186382A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006048507A1 (en) * | 2004-11-01 | 2006-05-11 | Aspocomp Technology Oy | Printed circuit board, method of manufacturing the same, and electronic device |
-
1994
- 1994-12-28 JP JP6328107A patent/JPH08186382A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006048507A1 (en) * | 2004-11-01 | 2006-05-11 | Aspocomp Technology Oy | Printed circuit board, method of manufacturing the same, and electronic device |
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