JPH08186174A - Wiring structure and method for forming the same - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a wiring structure capable of reducing contact resistance between metal wirings and a method for forming the same by slightly modifying the conventional semiconductor manufacturing process. [Structure] A semiconductor device 1 includes a silicon substrate 11 on which a semiconductor element is formed. An interlayer insulating film 12 is formed on the surface of the silicon substrate 11, and a first insulating film 12 is formed on the surface of the interlayer insulating film 12.
A metal wiring layer 13 is formed. An interlayer insulating film 14 is formed on the interlayer insulating film 12 including the first metal wiring layer 13, and a contact via hole 14a exposing the MVIA region of the first metal wiring layer 13 is formed in the interlayer insulating film 14. And
A second metal wiring layer 15 is formed on the surface of the interlayer insulating film 14, and the first and second metal wiring layers 13 and 15 are electrically connected. On the surface of the first metal wiring layer 13 (contact portion 5), a concave portion for reducing the contact resistance is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor device and a method of forming the same, and more particularly to a wiring structure in which two wiring layers are joined via a contact hole and a method of forming the same.

[0002]

2. Description of the Related Art A wiring structure of a conventional semiconductor device will be described.

For example, boron silicon phosphate glass (BP
A contact hole, a barrier metal, etc. are formed on the flattened surface of the (SG) film or the like, and a metal wiring material for the first layer (for example, Al / Si / C formed by the sputtering method)
u) about 4000-5000 angstroms (hereinafter A
Will be deposited). Then, after the wiring pattern is baked by photolithography, dry etching (B
C13 / C12 / 8 mtorr / 130 W) to form a first metal wiring pattern.

Next, an interlayer oxide film (IMOX) is deposited on the first metal wiring pattern, and a planarization process is performed to obtain about 1 μm.
Forming an interlayer insulating film. Then, a metal via hole (MVIA) is formed at a predetermined position of this interlayer insulating film, and a second-layer metal wiring material is deposited thereon. As a result, the first and second metal wirings are joined together.

[0005]

In recent years, the degree of integration and miniaturization of semiconductor devices has been remarkably increased.
The size of the product also tends to be reduced. This MVIA is restricted by design rules according to the manufacturing technology level, and the minimum size is about 0.8 μm at present. However, it is presumed that this size will be further reduced with the progress of the technical level, and it is desirable to reduce this size in view of the layout of the semiconductor device.

However, as the size of the MVIA is reduced, the contact area between the metal wirings is reduced, and the contact resistance is increased.

The present invention has been made in view of the above points, and an object thereof is to provide a wiring structure capable of reducing the contact resistance between metal wirings and a method for forming the same by slightly changing the conventional semiconductor manufacturing process. To provide.

[0008]

In order to achieve the above object, the wiring structure according to the present invention has a first wiring layer having a minimum width and a part of the first wiring layer as a contact region. An insulating film having an exposed contact hole and covering the first wiring layer except for this contact region, and a second film formed on the insulating film by being joined to the contact region through the contact hole. A wiring layer, and the contact region has a recess having a depth set to a value smaller than the thickness of the first wiring layer.

According to the wiring structure of the present invention,
The recess has an opening set to have an opening size smaller than the minimum width of the first wiring layer.

A method of forming a wiring structure according to the present invention includes a step of forming a first wiring layer having a minimum width and a contact hole exposing a part of the first wiring layer as a contact region. Then, a step of forming an insulating film covering the first wiring layer except the contact region, and forming a second wiring layer on the insulating film by joining to the contact region through the contact hole. And the step of forming the first wiring layer includes the step of forming a concave portion having a value smaller than the thickness of the first wiring layer in the contact region.

Further, according to the wiring structure forming method of the present invention, in the step of forming the recess, the first wiring layer is formed by photolithography using a mask having an opening having a size smaller than the resolution of the exposure wavelength. The step of removing a part is included.

[0012]

According to the wiring structure and the forming method thereof according to the present invention, first, the first wiring layer having the minimum width is formed. Next, an insulating film having a contact hole is formed on the surface of the first wiring layer. The contact hole exposes a contact region provided in a part of the first wiring layer. Then, the insulating film covers the first wiring layer other than the contact region. Further, a second wiring layer is formed on the insulating film, and the second wiring layer is bonded to the contact region via the contact hole. In the contact region, a recess having a depth smaller than the thickness of the first wiring layer is formed.

The above-mentioned recess is formed as follows. First, a resist layer is formed on the surface of the first wiring layer. Next, a mask having an opening having a size smaller than the resolution of the exposure wavelength is prepared, and this mask is arranged on the surface of the resist layer. Then, the resist layer is exposed and developed using this mask to form a resist pattern.
In this case, the part of the resist layer that is exposed by the light passing through the opening having a size smaller than the resolution is not sufficiently exposed. Therefore, holes are formed on the surface of the developed resist pattern so as to correspond to the positions of the openings. Then, the first wiring layer is etched using this resist pattern to form a wiring pattern. Thereby, the first
A recess is formed in the contact region on the surface of the wiring layer.

Therefore, the contact area between the first and second wiring layers is increased, and the contact resistance between them is reduced.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view schematically showing a contact region 5 between metal wirings in a wiring structure according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor device 1 includes a silicon substrate 11 having a semiconductor element (not shown) formed on its surface. The surface of the silicon substrate 11 is an interlayer insulating film 12 made of boron silicon phosphate glass (BPSG).
Covered by A first metal wiring layer 13 is formed on the surface of the interlayer insulating film 12 according to a design rule that defines a predetermined minimum width, and the first metal wiring layer 13 is connected to the above-described semiconductor element at a position not shown. It A part of the first metal wiring layer 13 is used as a contact region,
This region has a recess having a depth smaller than the thickness of the first metal wiring layer 13.

The first metal wiring layer 13 and the interlayer insulating film 12 are covered with an interlayer insulating film 14 made of a metal oxide. The interlayer insulating film 14 has a contact via hole 14a exposing the contact region 5 of the first metal wiring layer 13. The second metal wiring layer 15 is formed on the surface of the interlayer insulating film 14.
Are joined to the contact region via the contact via hole 14a. That is, these metal wiring layers 1
3 and 15 are electrically connected via a contact via hole 14a.

In the above-mentioned first metal wiring layer 13, the concave portion of the contact region 5 is formed between the first metal wiring layer 13 and the second metal wiring layer 15 even when the size of the MVIA is relatively small. The effective contact area can be increased.
As a result, the contact resistance between the first and second metal wiring layers 13 and 15 can be reduced. In addition, MVIA
If the above-mentioned recesses are positioned so as to overlap in the region, the effect of reducing the contact resistance between the first and second metal wiring layers 13 and 15 can be obtained, but as many recesses as possible are formed in this MVIA region. The contact resistance can be further reduced by arranging the contact resistance.

Next, a method of forming the wiring structure of the semiconductor device as described above will be described in detail.

First, as shown in FIG. 2A, a first metal wiring layer 13 of about 5000 A is formed on the surface of the planarized interlayer insulating film 12 provided on the silicon substrate 11. Then, a photoresist layer 20 (hereinafter, simply referred to as resist layer 20) having a thickness of about 1.5 μm is applied thereon. Then, at a predetermined position on the resist layer 20, the
A photomask 25 (hereinafter, simply referred to as a mask 25) as shown in (B) is arranged, and the resist layer 20 is exposed and developed. In this case, the area indicated by the imaginary line on the mask 25 is a predetermined MVI of the first metal wiring layer 13.
The mask 25 is formed on the resist layer 20 so as to match the area A.
Placed on top.

A mask 25 arranged on the resist layer 20.
Is a design rule for the first metal wiring layer 13 (L / S =
0.7 / 0.6), and in this embodiment, as shown in FIG. 3 (A), one side of the MVIA region is a square of 0.8 μm, and each MVIA region has a square shape. The distance from the side to the edge of the mask 25 is 0.4 μm. Then, as shown in FIG. 3B, a plurality of square holes 25 a each having a side of 0.2 μm are formed in a lattice pattern on the mask 25 in a portion overlapping with the MVIA region shown by an imaginary line. .

When the resist layer 20 is exposed and developed using the mask 25 as described above, a resist pattern 20 'shown in FIG. 2B can be obtained. The resist pattern 20 'has a hole 20b at a position corresponding to the opening 25a of the mask 25. Opening 2 of mask 25
5a has a size smaller than the resolution of the exposure wavelength (a square having a side of 0.2 μm), and the portion of the resist layer 20 irradiated with the light passing through the opening 25a of the mask 25 is not sufficiently exposed. Therefore, when the resist layer 20 exposed using the mask 25 is developed, the surface portion of the resist layer 20 corresponding to the opening 25a of the mask 25 becomes the hole 20b having the above-described depth.

It is also possible to use a mask 30 as shown in FIG. 4 instead of the mask 25 shown in FIG. 3 (B). The mask 30 has a circular opening 25a of the mask 25.
Instead of the above, a slit-shaped opening 30a is formed, and the width of each opening 30a is set smaller than the resolution of the exposure wavelength. Therefore, also in this case, holes corresponding to the slit-shaped openings 30a can be formed on the surface of the resist pattern 20 '. The opening shape of the mask is
The shape is not limited to the above-mentioned circle or slit. Any shape may be used as long as the opening has a size smaller than the resolution of the exposure wavelength. Further, the depth of the hole 20b formed on the surface of the resist pattern 20 'can be adjusted by changing the opening size of the mask.

When the resist pattern 20 'is formed in this manner, subsequently, metal dry etching (BC13
/ C12 / 8 mtorr / 130W). The etching conditions for this metal dry etching are determined as follows, for example. That is, the over-etching is 100 times the etching time of the first metal wiring layer 13.
%, That is, the etching time is determined such that the first metal wiring layer 13 is completely etched and then the same time is further etched, and the selection ratio of the first metal wiring layer 13 to the resist is 1.5 to 1.8. Has been decided to be.

When the metal dry etching is carried out under the above-mentioned conditions, the first metal wiring layer 13 is etched as shown in FIG. 2 (C). In this case, since the over-etching and the resist selectivity ratio are determined as described above, the first metal wiring layer 13 is etched and the resist pattern 20 'is simultaneously etched. Then, the hole 20b portion of the resist pattern 20 'disappears entirely during the etching, and the metal wiring layer 13 thereunder is further etched. Therefore, when the etching of the first metal wiring layer 13 is completed, the holes 13a corresponding to the holes 20b of the resist pattern 20 'are formed on the surface of the first metal wiring layer 13.

Next, the resist material slightly left on the first metal wiring layer 13 is removed, and an interlayer oxide film is deposited on the first metal wiring layer 13 according to a conventional method, and the interlayer oxide film is planarized. The interlayer insulating film 14 is formed. Then, a contact via hole 14a is formed at a predetermined position of the interlayer insulating film 14, that is, at a position corresponding to the contact region of the first metal wiring layer 13. Then, a second film is formed on the interlayer insulating film 14.
The metal wiring layer 15 is deposited, the first and second metal wiring layers 13 and 15 are electrically connected, and the semiconductor device 1 having the wiring structure as shown in FIG. 1 is formed. When the MVIA is designed to be smaller than a predetermined size, the contact region 5 may be formed by inserting a plug material such as tungsten into the contact via hole 14a.

Next, the holes 2 formed on the surface of the resist pattern 20 'to obtain the improved contact resistance between the first and second metal wiring layers 13 and 15 as described above.
The 0b depth margin will be described.

As shown in FIG. 5A, a hole 20b is formed on the surface of the resist pattern 20 'formed on the surface of the first metal wiring layer 13. The first metal wiring layer 13 has a layer thickness of 5000 A, and the resist pattern 20 'has a layer thickness of 1.5 μm. The selection ratio of the first metal wiring layer 13 to the resist is 1.5 to 1.6.

As described above, when the first metal wiring layer 13 having the resist pattern 20 'on its surface is etched by, for example, 100% over-etching amount (etching time which is twice the etching time of the entire first metal wiring layer 13). As shown in FIG. 5B, the resist pattern 20 '
The resist pattern 20 'is also etched according to the selection ratio between the first metal wiring layer 13 and the first metal wiring layer 13. Then, the resist material at the position where the hole 20b of the resist pattern 20 'is formed and which is relatively thin (resist layer remaining thickness a) is
All disappear during the etching, and at the end of the etching, the etching of the underlying first metal wiring layer 13 is started. Therefore, in consideration of the above etching conditions, the holes 13a formed on the surface of the first metal wiring layer 13 are formed.
Depth b and holes 20 on the surface of the resist pattern 20 '
The relationship between the resist residual thickness a from the bottom of b to the resist lower end is a × k + b = t × 2 (k = resist selection ratio, t
= Thickness of the first metal wiring layer).

Holes 20 on the surface of the resist pattern 20 '
The margin of the depth of b is determined by the margin of the resist residual thickness a, and the margin of the resist residual thickness a is determined by the margin of the depth b of the hole 13a on the surface of the first metal wiring layer 13 from the above formula. It is determined. Hole 1 in first metal wiring layer 13
The margin of the depth b of 3a is 0 <b <5000 (A) because the layer thickness of the first metal wiring layer 13 is 5000A.
Is required to be.

FIG. 6 is a graph showing the relationship between a and b based on the above equation. According to this, the resist residual thickness a is 3000 <a <6000 (A)
In particular, the margin of the resist residual thickness a for obtaining the optimum depth b of the hole 13a is 3750 ≦ a ≦
It is preferably 5600 (A).

On the other hand, the hole 20b for determining the resist residual thickness a
The depth of the holes is the opening size of the holes 25a formed in the mask 25 when exposing the resist layer 20 and the resist layer 20.
Is determined by the exposure energy of. FIG. 7 shows 435.
The relationship between the resist residual thickness a and the opening size of the hole 25a of the mask 25 when the resist layer 20 is exposed with the exposure energy of mj is shown. According to this graph,
Hole 25 in mask 25 for obtaining optimum resist residual thickness a
It can be seen that the opening size of a is 0.2 μm ± 0.05 μm.

Further, FIG. 8 shows the contact resistance of the contact portion 5 of the semiconductor device 1 obtained as a result of variously changing the opening size of the hole 25a of the mask 25. It can be seen that the minimum contact resistance is obtained when is 0.2 μm.

As described above, the opening 25a having a size equal to or smaller than the resolution of the exposure wavelength is formed in the mask 25 used for exposing the resist layer 20, and the resist layer 2 is formed using this mask 25.
When 0 is exposed and developed, holes 20b due to the opening size are formed on the surface of the developed resist pattern 20 '.
Is formed. When the first metal wiring layer 13 is etched using the resist pattern 20 ′ having such holes 20 b, holes 13 a are formed in the contact regions of the first metal wiring layer 13 at positions corresponding to the holes 20 b of the resist pattern. It When the hole 13a is formed in the contact region of the first metal wiring layer 13 as described above, the contact area between the first and second metal wiring layers 13 and 15 is increased, and as a result, the first and second metal wiring layer 13 is formed. , 15 is reduced.

The present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the present invention. Even if the resolution of the exposure wavelength is improved with the progress of technology, the resist pattern may be formed using a mask having an opening having a size equal to or smaller than the resolution. The depth of the hole formed on the surface of the first metal wiring layer is
It can be adjusted by changing the degree of over-etching, the resist ratio of the metal wiring layer, or other etching environment. Furthermore, in the above embodiment,
Although the opening of the mask is smaller than the resolution of the exposure wavelength, it is possible to make it larger than the resolution. In this case, the depth of the recess formed in the first metal wiring layer is the same as the layer thickness of the wiring layer. Become.

[0037]

As described above, since the wiring structure of the present invention has the above-mentioned structure and operation,
The contact resistance between the metal wirings can be reduced by slightly changing a part of the process without changing the flow of the conventional semiconductor manufacturing process.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a wiring structure of the present invention.

2A to 2C are process diagrams showing each step of the method for forming the wiring structure in FIG.

FIG. 3 is a schematic view showing a first embodiment of a photomask used in the step of FIG.

FIG. 4 is a schematic view showing a second embodiment of the photomask used in the step of FIG.

5A and 5B are cross-sectional views showing etching states of a resist and a first metal wiring layer during metal etching.

6 is a graph showing the relationship between the resist residual thickness a and the hole depth b of the first metal wiring layer in FIG.

FIG. 7 is a graph showing the relationship between the resist residual thickness a and the opening size of a mask hole in FIG.

FIG. 8 is a graph showing the relationship between the opening size of a mask hole and the contact resistance of a contact portion.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 5 ... Contact part, 11 ... Silicon substrate, 12, 14 ... Interlayer insulating film, 13 ... 1st metal wiring layer,
14a ... Contact via hole, 15 ... Second metal wiring layer.

Claims (4)

[Claims] 1. A first wiring layer having a minimum width set, and a contact hole exposing a part of the first wiring layer as a contact region, and the first wiring except the contact region. An insulating film covering the layer, and a second wiring layer formed on the insulating film by being joined to the contact region through the contact hole, the contact region having a thickness of the first wiring layer. A wiring structure having a recess having a depth set to a value smaller than the above. 2. The wiring structure according to claim 1, wherein the recess has an opening having an opening size smaller than the minimum width of the first wiring layer. 3. A step of forming a first wiring layer in which a minimum width is set, and a contact hole exposing a part of the first wiring layer as a contact region, wherein the contact region is excluded. A step of forming an insulating film covering the first wiring layer, a step of forming a second wiring layer on the insulating film by joining to the contact region through the contact hole,
And a step of forming the first wiring layer, the step of forming a concave portion having a value smaller than a thickness of the first wiring layer in the contact region. Method. 4. The step of forming the recess includes a step of removing a part of the first wiring layer by photolithography using a mask having an opening having a size smaller than the resolution of the exposure wavelength. The method for forming a wiring structure according to claim 3.