JPH0817294B2 - Semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a high input resistance amplifier circuit.

2. Description of the Related Art FIG. 4 is a circuit diagram of a semiconductor integrated circuit including a conventional high input resistance amplifier circuit. In FIG. 4, reference numeral 1 is a differential amplifier circuit for inputting a field effect transistor (hereinafter referred to as FET),
Reference numerals 2, 3 and 4 denote a positive phase input terminal, a negative phase input terminal and an output terminal of the differential amplifier circuit 1, respectively. Reference numerals 5 and 6 are feedback resistors for determining the amplification factor of the differential amplifier circuit 1. In an actual semiconductor integrated circuit, each end may be taken out of the semiconductor integrated circuit or may be connected inside the semiconductor integrated circuit. However, hereinafter, the positive phase input end 2 and the output end 4 will be described. A semiconductor integrated circuit whose only part is taken out will be described. The positive phase input terminal 2 is normally the differential amplifier circuit 1.
In order to maintain the normal operation of (1), it is necessary to maintain an appropriate DC potential through the resistor 7 or the like. here,
DC voltage generation circuit (hereinafter referred to as DC bias circuit) 8
As a result, a DC potential is applied via the resistor 7. 9,
Reference numerals 10 are a coupling capacitor and a signal source for applying a signal to the positive phase input terminal 2 from the outside.

This differential amplifier circuit 1 is often a FET input differential amplifier circuit as shown in FIG. 5 as a high input resistance amplifier. In FIG. 5, reference numerals 11 and 12 denote input FETs connected to the positive phase input terminal 2 and the negative phase input terminal 3 of the differential amplifier circuit 1, and 13 is an NPN transistor for reducing the output resistance, Output signal is differential amplifier circuit 1
Is output to the output terminal 4. 15 and 16 are current sources, 17,18
Is a load resistance of the input stage and is connected to the power supply line 19. The input FETs 11 and 12 shown in FIG. 5 are formed in a relatively deep P-type region (hereinafter referred to as P-well) in an N-type semiconductor, and the P-type regions above and below the N channel can both be used as gates. Possible N-channel junction type FET
(Hereinafter referred to as JEET) is used. Unless otherwise specified, a JFET having this structure will be described below as an example. In the semiconductor integrated circuit in which the differential amplifier circuit of FIG. 5 is connected as a constituent element as shown in FIG. 4, the input resistance of the positive phase input terminal 2 when viewed from the outside is almost equal to the DC bias circuit 8 and the positive phase input terminal 2.
It is determined by the resistance value of a resistor (hereinafter, referred to as a bias resistor) 7 that connects with, and when an input resistance of several MΩ or more is required, the same method as the resistance formation used in a normal semiconductor integrated circuit is used. , Difficult to achieve.

In order to solve this and realize high input resistance,
A method used in a semiconductor integrated circuit including a FET input differential amplifier circuit will be described with reference to FIG. In FIG. 6, the input bias resistor is composed of the FET20 made by the same method as the FET of FIG. 5, and the channel portion of the FET20 has a narrow width and a long source-drain distance. This realizes high resistance.
In this case, the gate of the FET 20 is connected to another bias circuit 21 as shown in FIG. 6 or to the ground potential or the input bias circuit 8 depending on the characteristics of the FET. For example, in the process of FET threshold voltage 0.7V, channel width 6μm, source-drain distance 15mm
When the channel of the FET is configured and the gate is connected to the input bias circuit 21, a high resistance of about 100 MΩ can be obtained.

Problems to be Solved by the Invention A high input resistance amplifier can be realized with the configuration of the conventional semiconductor integrated circuit described above, and good amplification characteristics can be obtained under the condition that the internal impedance of the signal source can be regarded as a substantially pure resistance. However, in the configuration of such a conventional semiconductor integrated circuit, like the AC signal generated in the dielectric piezoelectric element,
If the internal impedance of the signal source is capacitive, then
There is a problem that the amplitude of the output signal changes depending on the frequency of the input signal. For example, in a semiconductor integrated circuit that uses a FET as an input bias resistor, when 10PF is used as the coupling capacitance 9 shown in FIG. 6, when the frequency of the signal source 10 is 100 Hz, the semiconductor is compared with the case of 5 KHZ. The output signal 4 of the integrated circuit has a problem that the output signal is reduced by 6 dB.

The present invention solves the above-mentioned conventional problems.
It is an object of the present invention to provide a semiconductor integrated circuit including a differential amplifier circuit having a good frequency characteristic even for a capacitive signal source, which is a high input resistance amplifier circuit using a T channel as a resistance for applying an input DC bias. It is intended.

Means for Solving the Problems A first invention of a semiconductor integrated circuit of the present invention for solving the above problems is a differential circuit composed of first and second field effect transistors for input forming a differential pair. Semiconductor comprising an amplifier circuit (1) and a third field effect transistor (22) for DC bias connected between a positive phase input terminal (+) of the differential amplifier circuit and a DC bias potential point An integrated circuit, comprising: a first resistor (5) connected between an output terminal of the differential amplifier circuit and a negative phase input terminal (-), and between the negative phase input terminal and a ground point. Second and third resistors (23a, 23) connected in series
b) is provided, the input signal of the signal source (10) is applied to the positive phase input terminal of the differential amplifier circuit (1), and the gate of the third field effect transistor (22) is connected to the second and second gates. 3 is connected to the intermediate connection point of the resistor.

Further, a second invention is a differential amplifier circuit (1) composed of first and second field effect transistors for input which form a differential pair, and one conductivity type formed on a semiconductor substrate (29). A well region (28), first and second diffusion regions of opposite conductivity type formed separately in the well region, and on the well sandwiched by the first and second diffusion regions. A semiconductor integrated circuit comprising a third field effect transistor (30) for direct current bias composed of the formed gate region (31), the output terminal of the differential amplifier circuit and the negative phase input terminal. A first resistor (5) connected to (-) and a second and a third resistor (23a, 23a, 23a, 23b connected in series between the negative-phase input terminal and the ground point.
23b) and a positive phase input terminal (+) of the differential amplifier circuit.
Is connected to the first diffusion region to supply the input signal of the signal source (10), the second diffusion region is connected to a DC bias potential point, and the well region (28) and the gate region (31) are connected. ) Is commonly connected to the intermediate connection point of the second and third resistors.

With the above configuration, the first to third resistors (5, 23a, 23b) forming the negative feedback path of the differential amplifier circuit (1) cause a part of the output signal having the same phase as the input signal to output the third signal. Differential amplifier circuit (1) given to the gate of field effect transistor (22)
When an input signal is applied to the positive phase input terminal of, the amount of potential change between the channel portion and the gate of the third field effect transistor (22) is reduced, and the input capacitance of the signal source (10) side is reduced. The effective value becomes small, and the signal from the capacitive signal source with high internal impedance can be amplified without frequency dependency.

Furthermore, a second aspect of the invention is that the gate region (31) and the well region (28) of the third field effect transistor (30) for direct current bias are connected in common, and the second and third resistors (23a, 23b) are connected. )
Since it is connected to the intermediate connection point of, the channel region of the third field effect transistor (30) which operates as a transistor can be made the narrowest, and the structure can obtain the highest resistance for bias with the same input capacitance value. By reducing the shape, the input capacitance can be minimized with the same resistance value.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit showing an embodiment of the present invention. The same parts as those in the conventional example are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, 22 is
4 is a DC bias application FET connected between the DC bias circuit 8 and the positive phase input terminal of the differential amplifier circuit 1, and the gate of this FET 22 is connected to the differential amplifier circuit 1 The feedback resistor 23 connected between the negative phase input terminal 3 of the differential amplifier circuit 1 whose output terminal 4 is connected via the feedback resistor 5 and the ground
It is connected to the midpoint between a and 23b.

The operation of the semiconductor integrated circuit configured as described above will be described below. In FIG. 1, the signal source 10 inputs a signal to the positive phase input terminal 2 of the differential amplifier circuit 1,
The signal is amplified by the differential amplifier circuit 1 and output to the output terminal 4. At that time, the output signal is input to the gate of the FET 22 via the feedback resistors 5 and 23a. At this time, a signal in phase with the positive phase input signal input to the positive phase input terminal 2 of the differential amplifier circuit 1 is added to the gate of the FET 22, and the current for charging / discharging by this positive phase input signal. As shown in FIG. 2, the capacitance 2 existing between the FET channel portion 24, which has a high resistance of the FET 22, and the gate 25 of the FET 22, as shown in FIG.
6 becomes smaller. Therefore, the effective capacitance seen from the positive-phase input terminal 2 becomes small, and the signal from the capacitive signal source with high internal impedance can be amplified without frequency dependency.

In Fig. 1, under the condition that the input coupling capacitance 9 is 10PF, the feedback resistor 5 is 1.5KΩ and the feedback resistors 23a and 23b are 1.8KΩ and 8.4K, respectively.
High resistance FET2 with the same circuit constant by setting to Ω
In the case of the conventional circuit of FIG. 6 in which the gate of 2 is connected to the DC potential, the change of the output signal of the output terminal 4 is 6 dB when the frequency of the input signal is 100 HZ to 5 KHZ, but it is output in the case of FIG. The signal change could be suppressed within ± 0.5 dB.

Further, in the present embodiment, the example in which the P-type regions above and below the N channel of the FET 22 are both used as gates has been described. However, the P well including the FET 22 is fixed to a DC potential,
Even when only the P-type region above the N channel is used as a gate and the connection is made as shown in Fig. 1, the change in the output signal under the same conditions as above is within ± 2.5 dB, and even when it is not the upper and lower gates. The effect of this example was confirmed.

Further, in the present embodiment, JEET is used as an example for explanation, but it is natural that the same effect can be obtained even when an insulated gate field effect transistor (hereinafter referred to as MISFET) is used as FET. In this case, for example, N
Considering the N-channel MISFET formed in the P-well in the substrate, as shown in FIG. 3, a different potential is usually set independently of the region of the P-well 27 which needs to be fixed to the lowest DC potential during operation. A MISFET constructed in the region of the p-well 28 that can be applied,
Specifically, for example, an independent P in the N-type semiconductor substrate 29 is used.
The N channel MISFET 30 made in the well 28 is used as the high resistance FET in the DC bias applying FET 22 of FIG.
By connecting the P well 28 and the gate 31 in the region including the FET, it is possible to realize the bias resistance having the smallest input capacitance and the highest value, and the most effective.

EFFECTS OF THE INVENTION As described above, according to the present invention, the first to third resistors forming the negative feedback path of the differential amplifier circuit cause a part of the output signal in phase with the input signal to cause the third electric field effect. When applied to the gate of the transistor and applied to the positive phase input terminal of the differential amplifier circuit, the amount of potential change between the channel section and the gate of the third field effect transistor is reduced, which is viewed from the signal source side. The effective value of the input capacitance can be reduced.

Further, if the gate region and the well region of the third field effect transistor for DC bias are commonly connected and connected to the intermediate connection point of the second and third resistors, the channel region in which the transistor operates can be made the narrowest. The structure is the most effective because the structure can obtain the highest biasing high resistance even with the same input capacitance value.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the semiconductor integrated circuit showing the DC bias field effect transistor in an equivalent circuit, and FIG. 3 is the same semiconductor integrated circuit. FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit, FIG. 5 is a circuit diagram of a field effect transistor input differential amplifier circuit of the semiconductor integrated circuit, and FIG. 5 is a circuit diagram of a semiconductor integrated circuit obtained by improving the semiconductor integrated circuit of FIG. 1 ... Differential amplifier circuit, 2 ... Positive phase input terminal, 3 ... Reverse phase input terminal, 4 ... Output terminal, 5,23, 23a, 23b ... Feedback resistor, 8 ...
… DC bias circuit, 11,12 …… Input FET, 22,30 …… DC bias applying FET, 24 …… FET channel section, 27 ……
P well of input FET, 28 ... P of FET for applying DC bias
Well, 31 ... Gate of FET for DC bias application.

Claims (2)

[Claims] 1. A differential amplifier circuit composed of input first and second field effect transistors forming a differential pair, and between a positive phase input terminal of the differential amplifier circuit and a DC bias potential point. A third field effect transistor for direct current bias connected to the first integrated circuit, comprising: a first resistor connected between the output terminal and the negative phase input terminal of the differential amplifier circuit. , A series connection between the negative-phase input terminal and the ground point
And a third resistor, which supplies an input signal of a signal source to the positive phase input terminal of the differential amplifier circuit, and which connects the gate of the third field effect transistor to the middle of the second and third resistors. A semiconductor integrated circuit connected to a connection point. 2. A differential amplifier circuit composed of first and second field effect transistors for input forming a differential pair, a well region of one conductivity type formed on a semiconductor substrate, and the inside of the well region. DC bias composed of first and second diffusion regions of opposite conductivity type spaced apart from each other and a gate region formed on the well sandwiched between the first and second diffusion regions A third field effect transistor for use in a semiconductor integrated circuit, comprising: a first resistor connected between an output terminal of the differential amplifier circuit and a negative-phase input terminal; and the negative-phase input terminal. A second and a third resistance connected in series between the differential amplifier circuit and a ground point, and the first diffusion region is connected to the positive phase input terminal of the differential amplifier circuit to provide an input signal of a signal source. At the same time, the second diffusion region is connected to a DC bias potential point, and the well region and the gate region are connected. The second semiconductor integrated circuit are commonly connected to the intermediate connection point of the third resistor.