JPH08162479A - Method of manufacturing field effect transistor and field effect transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] To optimize the electrical characteristics and processability of MES-FET. A process of forming a sidewall 9 having a refractive index of about 1.55 to 1.65 on a sidewall of a Schottky contact type gate electrode 4 formed on a semi-insulating substrate 1, and a semi-insulating substrate. 1 and the step of coating the surface protective film 5 having a refractive index of about 1.8 or more on the surface of the MES • FET 2 so as to satisfy both the electrical characteristics and the other characteristics such as workability of the MES • FET 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor and a field effect transistor technology, and more particularly to a Schottky gate type field effect transistor (Metal Semiconductor Fiel) formed on a compound semiconductor substrate.
d Effect Transistor; hereinafter referred to as MES / FET)
It is related to the technology effectively applied to.

[0002]

2. Description of the Related Art As the information-oriented society advances, it is required to develop a circuit capable of processing high-density information at high speed. The MES • FET using a compound semiconductor substrate typified by gallium / arsenic (GaAs) has been drawing attention as an element that meets the demand.

This is an MES ・ using a GaAs substrate or the like.
Compared with the case where a FET uses a semiconductor substrate made of a single element such as silicon (Si), carrier mobility is large and high speed can be expected, and substrate resistance is large and stray capacitance can be small. Because it has.

Such a compound semiconductor device is described, for example, in "LSI Handbook", P703 to P710, published by Ohmsha Co., Ltd., November 30, 1984, and is Schottky contacted on a semi-insulating substrate. The channel layer is provided under the gate electrode provided in the state,
Various MES • FET structures having a source region and a drain region on both sides thereof have been introduced.

By the way, according to the technique studied by the present inventor, for example, MES · F such as Schottky barrier resistance
From the viewpoint of improving the electrical characteristics of ET, an ME having a structure in which a so-called gate sidewall insulating film is formed on the sidewall of the gate electrode.
There is an S-FET.

In the case of the MES-FET having this structure, the gate sidewall insulating film and the surface protective film serving as a protective film for ion implantation at the time of forming the source / drain regions are made of the gate sidewall insulating film. Was determined by focusing on only the characteristics required for the above, that is, the characteristics that determine the electrical characteristics of the MES • FET, and was composed of insulating films having the same characteristics (refractive index).

[0007]

However, the gate sidewall insulating film and the surface protection film are determined by focusing only on the characteristics required for the gate sidewall insulating film, and are composed of insulating films having the same characteristics (refractive index). The MES studied by the inventor
In the FET technology, there is a problem that the insulating film having the best film quality as the gate sidewall insulating film is not necessarily the best as the surface protective film, and there arises a problem in the characteristics as the surface protective film, such as workability and protective characteristics. The present inventor has found that.

An object of the present invention is to provide a technique capable of optimizing both electric characteristics and workability of FET.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0010]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, in the FET of the present invention, a step of forming a gate electrode in a Schottky contact state on a semiconductor substrate and forming a gate sidewall insulating film having a first refractive index on a sidewall of the gate electrode. And a step of coating a surface protection film having a second refractive index different from the first refractive index on the semiconductor substrate.

The FET of the present invention has the first refractive index of 1.55 to 1.65 and the second refractive index of 1.8 or more.

[0013]

According to the above-described method of manufacturing the FET of the present invention,
Since the refractive index of the gate side wall insulating film and the refractive index of the surface protective film can be changed, it is possible to optimize both electric characteristics and processability of the FET. For example, according to the study by the present inventors, the refractive index of the gate sidewall insulating film is 1.5
By setting it to 5 to 1.65, the leak current can be minimized, and by setting the refractive index of the surface protective film related to the interface reaction with the semi-insulating substrate to 1.8 or more,
It has been found that properties such as its processability and protective properties can be improved.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a field effect transistor according to an embodiment of the present invention, and FIGS. 2 to 5 are sectional views of the field effect transistor of FIG. 1 during a manufacturing process.

A semi-insulating substrate (semiconductor substrate) 1 shown in FIG.
Consists of a compound semiconductor such as GaAs,
The MES • FET2 is formed in the element region.

Although not shown, other elements such as a plurality of MES • FETs 2 and Schottky barrier diodes are formed on the semi-insulating substrate 1, which allows, for example, ICs for communication equipment ( Integrated Circui
A predetermined semiconductor integrated circuit device such as t) is constructed.

The MES • FET 2 has a channel region 3a formed on the semi-insulating substrate 1, a source region 3b and a drain region 3c formed on both sides of the channel region 3a on the semi-insulating substrate 1, Channel region 3
and a gate electrode 4 formed in a Schottky contact state on a.

For example, n-type impurity silicon (Si) is introduced into the channel region 3a, the source region 3b and the drain region 3c.

The source region 3b is composed of a low impurity concentration semiconductor region 3b1 and a high impurity concentration semiconductor region 3b2 formed on the channel region 3a side. The high impurity concentration semiconductor region 3b2 of the source region 3b is electrically connected to the source extraction electrode 7a through a connection hole 6a formed in the surface protective film 5 deposited on the semi-insulating substrate 1.

The drain region 3c is composed of a low impurity concentration semiconductor region 3c1 and a high impurity concentration semiconductor region 3c2 formed on the channel region 3a side. The high impurity concentration semiconductor region 3c2 of the drain region 3c is
It is electrically connected to the drain extraction electrode 7b through a connection hole 6b formed in the surface protective film 5.

The source extraction electrode 7a and the drain extraction electrode 7b are formed of, for example, gold germanium (AuG).
e) Made of alloy.

The gate electrode 4 has, for example, a specific resistance of 150 Ωc.
It is made of tungsten silicide of about m to 200 Ωcm, and is electrically connected to the gate extraction electrode 8 through a connection hole (not shown) formed in the surface protection film 5.

The gate lead-out electrode 8 is provided to reduce the resistance value of the gate electrode 4, and is, for example, on the molybdenum (Mo) layer, for example, A having a specific resistance of about 3 to 4 Ωcm.
The u layer is deposited and configured. The Mo layer in the gate extraction electrode 8 is provided to improve the adhesion with the gate electrode 4.

A sidewall (gate sidewall insulating film) 9 is formed on the sidewall of the gate electrode 4. The sidewall 9 is made of oxynitride. In this embodiment, the sidewall 9 has a refractive index of, for example, 1.5.
It was set to be about 5 to 1.65, preferably about 1.6. The refractive index is set according to the concentration of nitrogen contained in the sidewall 9, for example.

Further, by forming the side wall 9 with such a material, according to the study result of the present inventor, the leakage current can be minimized and the gate breakdown voltage can be improved. There was found. Also,
It is possible to improve the electrical characteristics such as the threshold voltage, frequency characteristics, resistance, and transfer conductance of the MES • FET2.

Further, in this embodiment, the source region 3
The surface protective film 5, which serves as a protective film when the b and drain regions 3c are formed, is also made of, for example, oxynitride.
However, in this embodiment, the refractive index of the surface protective film 5 is set to, for example, 1.8 or more, preferably about 1.9 to 2.0. The refractive index is set according to the concentration of nitrogen contained in the surface protective film 5.

By setting the material of the surface protective film 5 in this way, according to the results of the study by the present inventors, it is possible to improve the protective property at the time of impurity ion implantation and the processability at the time of forming the connection hole. It turned out to be possible.

That is, according to the result of the study by the present inventor,
Since the side wall 9 and the surface protection film 5 are formed of an oxynitride film having a different refractive index, M
It has been found that it is possible to optimize both the electrical characteristics and the workability of the ES • FET2.

Next, a method of manufacturing the MES • FET 2 of this embodiment will be described with reference to FIGS.

FIG. 2 is a sectional view of the semi-insulating substrate 1 during the manufacturing process of the MES • FET 2 of this embodiment.

The semi-insulating substrate 1 is made of, for example, GaAs, and a channel region 3a and low impurity concentration semiconductor regions 3b1 and 3c1 are formed on the upper portion thereof. The channel region 3a and the semiconductor region 3b1 of low impurity concentration,
For example, n-type impurity Si is introduced into 3c1. A gate electrode 4 is formed on the channel region 3a. The gate electrode 4 is made of, for example, tungsten silicide.

First, as shown in FIG. 3, an insulating film 9a made of, for example, oxynitride is deposited on such a semi-insulating substrate 1 by a CVD method or the like. This insulating film 9
The refractive index of a is, for example, about 1.55-1.65, preferably
It was set to about 1.6. The refractive index is
It is set by the concentration of nitrogen contained in the insulating film 9a.

As a result, the leak current can be minimized and the gate breakdown voltage can be improved. Moreover, it is possible to improve the electrical characteristics such as the threshold voltage, frequency characteristics, resistance, and transfer conductance of the MES • FET2.

Then, the insulating film 9a is etched back by a dry etching method or the like to form a sidewall 9 made of the insulating film 9a on the side wall of the gate electrode 4, as shown in FIG.

After that, a surface protective film 5 made of, for example, oxynitride is deposited on the semi-insulating substrate 1 by the CVD method or the like. However, the refractive index of the surface protective film 5 is
For example, it is set to be 1.8 or more, preferably about 1.9 to 2.0. The refractive index is set according to the concentration of nitrogen contained in the surface protective film 5.

Next, semiconductor regions 3b2 and 3c2 having a high impurity concentration are formed on the semi-insulating substrate 1 by ion-implanting n-type impurities such as Si. Thereby, the source region 3b of the MES • FET2
And the drain region 3c is formed.

Subsequently, as shown in FIG. 1, connection holes 6a and 6b are formed in the surface protective film 5 so that the semiconductor regions 3b2 and 3c2 having a high impurity concentration are exposed.

At this time, in this embodiment, since the material having the above-mentioned refractive index is used as the surface protective film 5, the insulating film remains at the bottoms of the connection holes 6a and 6b, and the like, which is excellent. Since the connection holes can be formed, it is possible to reduce the contact resistance in the connection holes 6a and 6b.

After that, the source extraction electrode 7a and the drain extraction electrode 7b are simultaneously formed, and then the gate extraction electrode 8 is formed, whereby the MES • FET 2 is manufactured.

As described above, according to this embodiment, since the sidewall 9 and the surface protective film 5 are formed of the oxynitride film or the like having different refractive indexes, the MES.F
It is possible to optimize the electrical characteristics of ET2 and other characteristics such as workability and protection. Therefore, the yield and reliability of the MES • FET 2 formed on the semi-insulating substrate 1 can be improved.

The invention made by the inventor of the present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, MES.F
The case where the ET channel is an n-type has been described, but the present invention is not limited to this, and for example, a p-channel ME is used.
It can also be applied to S-FETs.

Further, in the above embodiment, the case where the semi-insulating substrate is made of GaAs has been described, but the present invention is not limited to this, and various modifications are possible, for example, indium phosphide or the like may be used.

In the above description, the invention made mainly by the present inventor is the field of application which is the background of the invention.
Although the case where it is applied to the FET has been described, the present invention is not limited to this, but various applications are possible, such as a FET in which the gate electrode 4 is provided on the channel region 3a via the insulating layer 10 as shown in FIG. It is also possible to apply to other FETs. The insulating layer 10a of the insulating layer 10 is made of, for example, AlGaAs, and the insulating layer 10b is made of, for example, GaAs.

[0046]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method of manufacturing an FET of the present invention,
Since the refractive index of the gate side wall insulating film and the refractive index of the surface protective film can be changed, it is possible to optimize both electric characteristics and processability of the FET. For example, according to the study by the present inventors, the refractive index of the gate sidewall insulating film is 1.5
By setting it to 5 to 1.65, the leak current can be minimized, and by setting the refractive index of the surface protective film related to the interface reaction with the semi-insulating substrate to 1.8 or more,
It has been found that properties such as its processability and protective properties can be improved. Therefore, the yield and reliability of the FET formed on the compound semiconductor substrate can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a field effect transistor that is an embodiment of the present invention.

FIG. 2 is a cross-sectional view during a manufacturing process of the field effect transistor of FIG.

3 is a cross-sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 2;

4 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 3;

5 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 4;

FIG. 6 is a cross-sectional view of a field effect transistor that is another embodiment of the present invention.

[Explanation of symbols]

 1 semi-insulating substrate (semiconductor substrate) 2 Schottky gate type field effect transistor 3a channel region 3b source region 3b1 low impurity concentration semiconductor region 3b2 high impurity concentration semiconductor region 3c drain region 3c1 low impurity concentration semiconductor region 3c2 high impurity Concentration semiconductor region 4 Gate electrode 5 Surface protection film 6a, 6b Connection hole 7a Source extraction electrode 7b Drain extraction electrode 8 Gate extraction electrode 9 Sidewall 9a Insulating film 10, 10a, 10b Insulating layer

Claims (8)

[Claims] 1. A step of forming a gate electrode in a Schottky contact state on a semiconductor substrate, a step of forming a gate sidewall insulating film having a first refractive index on a sidewall of the gate electrode, and the semiconductor substrate. And a step of coating a surface protective film having a second refractive index different from the first refractive index thereon. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the first refractive index is 1.55 to 1.65.
And the second refractive index is 1.8 or more. 3. The method of manufacturing a field effect transistor according to claim 1, wherein the semiconductor substrate is GaAs.
And a method of manufacturing a field effect transistor, wherein the gate sidewall insulating film and the surface protective film are made of an oxynitride film. 4. The method for manufacturing a field effect transistor according to claim 1, 2 or 3, wherein the gate electrode is a Schottky gate type electrode. 5. A gate sidewall insulating film formed on a sidewall of a gate electrode formed on a semiconductor substrate and a surface protective film deposited on the semiconductor substrate are made of insulating films having different refractive indexes. Field effect transistor characterized by. 6. The field effect transistor according to claim 5, wherein the gate sidewall insulating film has a refractive index of 1.55 to 1.6.
5. The field effect transistor according to claim 5, wherein the surface protection film has a refractive index of 1.8 or more. 7. The field effect transistor according to claim 5, wherein the semiconductor substrate is GaAs, and the gate sidewall insulating film and the surface protective film are oxynitride films. . 8. The field effect transistor according to claim 5, 6 or 7, wherein the gate electrode is a Schottky gate type electrode.