JPH08167864A - Spread spectrum communication device - Google Patents

Abstract

(57) [Abstract] [Purpose] An object is to provide a spread spectrum communication device capable of reducing the circuit scale. [Composition] The downsizing of the high-speed synchronization circuit is realized by providing a spreading code channel dedicated to synchronization and providing a synchronization circuit using a SAW convolver that performs code phase synchronization and clock synchronization common to all channels only to this channel. However, it is not necessary to provide a synchronization circuit for each of the other data channels. In addition, a carrier wave is regenerated by despreading the synchronization dedicated channel, the received signal is directly converted into a baseband signal using this regenerated carrier wave, and this baseband signal is demodulated by digital signal processing, so that the demodulation unit Use a circuit configuration suitable for LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct spread spectrum spread spectrum communication device, and more particularly to a communication device in a code division multiple communication system for multiplexing and transmitting a plurality of spread code channels.

[0002]

2. Description of the Related Art In a conventional spread spectrum communication system using a direct spread system, a transmitting side uses a spread code sequence such as a pseudo noise code (PN code) so that a base band signal of a digital signal to be normally transmitted is transmitted. It produces a baseband signal with a much wider bandwidth than the original data. Then, modulation such as PSK (phase shift keying) or FSK (frequency shift keying) is performed and converted into an RF (radio frequency) signal for transmission.

On the receiving side, the same spreading code as that on the transmitting side is used to perform despreading for correlating with the received signal to convert the received signal into a narrow band signal having a bandwidth corresponding to the original data. Then, normal data demodulation is performed to reproduce the original data.

As described above, in the spread spectrum communication system, the transmission bandwidth is extremely wide with respect to the information bandwidth.
Under the condition that the transmission bandwidth is constant, only a very low transmission rate can be realized as compared with the ordinary narrow band modulation method. To solve this problem, there is a method called code division multiplexing.

In this system, a high-speed information signal is converted into low-speed parallel data, spread-modulated by different spread-code sequences, added, and then converted into an RF signal for transmission, whereby the spread factor of spread-modulation. It realizes high-speed data transmission under the condition that the transmission bandwidth is constant without lowering.

FIG. 3 is a block diagram showing the configuration of a transmitter based on such a code division multiplexing system.

In the figure, the input data is converted into n parallel data by the serial-parallel converter 301. Each converted data has n multiplier groups 302-1 to 30-30.
In 2-n, n different spreading code outputs of the spreading code generator 303 are multiplied and converted into an n-channel wide band spreading signal.

Next, the outputs of the respective multipliers are added by the adder 304 and output to the high frequency stage 305. The added baseband wideband spread signal is converted by the high frequency stage 305 into a transmission frequency signal having an appropriate center S frequency, and transmitted by the transmission antenna 306.

FIG. 4 is a block diagram showing the configuration of a receiver according to the code division multiplexing system.

First, the signal received by the antenna 401 is appropriately filtered and amplified by the high frequency signal processing section 402 and converted into an intermediate frequency signal. This intermediate frequency signal is distributed to the channels corresponding to each of the n spreading codes connected in parallel.

In each channel, the input signal is the correlator group 4
In 03-1 to 0-n, correlation detection is performed with the output of the spreading code generator group 404-1 to 40-n corresponding to the channel, and despreading is performed.

This despread signal is the synchronous circuit group 405-1.
The synchronization is established for each channel at .about.n, and the code phases and clocks of the spread code generators are matched. The despread signal is demodulated by demodulator groups 406-1 to 40-n to reproduce data. Subsequently, this reproduction data is converted into serial data by the parallel-serial converter 407, and the original information is reproduced.

[0013]

However, in the above-mentioned conventional example, since the carrier wave is not reproduced at the time of inputting the correlator, the correlator of each demodulation channel must operate in the intermediate frequency stage. However, there is a drawback that the circuit scale becomes very large as the number of code division multiplexing increases.

Further, in order to perform a normal demodulation operation in each demodulation channel, code phase synchronization and clock synchronization have not been established with respect to the transmission spread code included in the received signal of each spread code generator output. However, it is necessary to provide a synchronization circuit for this purpose for each channel, which also causes an increase in circuit scale.

It is an object of the present invention to provide a spread spectrum communication device capable of reducing the circuit scale.

[0016]

The present invention provides an SA in which a spread code channel dedicated to synchronization is prepared and code phase synchronization and clock synchronization common to all channels are performed only in this channel.
By providing a synchronization circuit that uses a W convolver, the high-speed synchronization circuit can be downsized, eliminating the need to provide a synchronization circuit for each of the other data channels, and by despreading the synchronization-dedicated channel. Play the carrier wave,
The received signal is directly converted into a baseband signal by using the reproduced carrier wave, and the baseband signal is demodulated by digital signal processing, so that the demodulation unit has a circuit configuration suitable for an LSI, thereby reducing the size of the circuit. It is intended to make a significant contribution to the.

[0017]

1 is a block diagram showing the structure of a transmitter in a first embodiment of the present invention, and FIG. 2 is a block diagram showing the structure of a receiver in this first embodiment.

In FIG. 1, a serial-parallel converter 101 is for converting serially input data into n pieces of parallel data, and the multiplier groups 102-1 to 102-n are parallel to the parallelized data. It is to be multiplied by n spread codes output from the spread code generator 103.

The spread code generator 103 generates n different spread codes and a spread code dedicated to synchronization, and the adder 104 multiplies the spread code dedicated to synchronization output from the spread code generator 103. N of the device groups 102-1 to n
This is to add the individual outputs. The high frequency stage 105
The output of the adder 104 is converted into a transmission frequency signal, and this transmission frequency signal is transmitted from the transmission antenna 106.

In FIG. 2, the transmission frequency signal from the transmitter is received by the receiving antenna 201, appropriately filtered and amplified by the high frequency signal processing section 202, and modulated into a predetermined frequency band signal. It

The synchronization circuit 203 captures and maintains the synchronization with the spread code and the clock on the transmission side, and the spread code generator 204 receives the code synchronization signal and the clock signal input from the synchronization circuit 203 on the transmission side. The same n + 1 spreading codes as those of the above spreading code group are generated.

The carrier reproduction circuit 205 reproduces a carrier signal from the carrier reproduction spread code output from the spread code generator 204 and the output of the high frequency signal processing section 202. The output of the reproduction circuit 205, the output of the high-frequency signal processing unit 202, and the output of the spread code generator 204 are used to perform demodulation in the base band using n spread codes.

The parallel-serial converter 207 parallel-serial converts the n pieces of parallel demodulated data output from the baseband demodulation circuit 206.

In the above structure, on the transmitting side, the input data is first converted by the serial-parallel converter 101 into n parallel data equal to the number of code division multiplexes. on the other hand,
The spreading code generator 103 generates n + 1 pieces of spreading codes PN0 to PNn having the same code period but different from each other.

Of these, the spread code PN0 is dedicated to synchronization and carrier reproduction, is not modulated by the parallel data, and is directly input to the adder 104.

The remaining n spreading codes PN1 to PN
n is modulated by n pieces of parallel data in the multiplier groups 102-1 to 10-n and input to the adder 104. Adder 10
Reference numeral 4 linearly adds the input n + 1 signals and outputs the added baseband signal to the high frequency stage 105.

The baseband signal is subsequently converted into a high frequency signal having an appropriate center frequency in the high frequency stage 105 and transmitted from the transmitting antenna 106.

On the other hand, on the receiving side, the signal received by the receiving antenna 201 is appropriately filtered and amplified by the high frequency signal processing section 202 and is converted into a transmission frequency band signal as it is or converted into an appropriate intermediate frequency band signal. Is output.

This signal is input to the synchronizing circuit 203,
The synchronization circuit 203 establishes spread code synchronization and clock synchronization for the transmission signal by using the reference spread code input from the code generator 204, and outputs the code synchronization signal and the clock signal to the spread code generator 204.

As the synchronizing circuit 203, for example, a circuit using a SAW convolver as shown in FIG. 7 is used.
In FIG. 7, the received intermediate frequency band signal is input to the SAW convolver 701. On the other hand, the reference spreading code input from the code generator 204 is a signal obtained by inverting the transmitted synchronization-only spreading code on the time axis, and the multiplier 7
09 is multiplied by the output of the local oscillator 710 and converted into a predetermined intermediate frequency band signal, and then the SAW convolver 7
01 is input.

The SAW convolver 701 has an integration area length corresponding to one cycle of the spread code and outputs a convolutional integration of two input signals. This output is then passed through a bandpass filter 702 that blocks signals other than the convolution integrated signal, with the center frequency being twice the input frequency of the convolver 701, and the amplifier 7
After being appropriately amplified in 03, the envelope detector 704 detects the envelope. Since one signal of the convolutional integration is the other signal time-reversed, this integration is a correlation integration.

Therefore, if the auto-correlation characteristic of the synchronization-dedicated spreading code has a sharp peak at the synchronization point and has a sufficiently low side lobe at other points, the synchronization-dedicated spreading code component is included in the received signal. When included, a steep peak appears in the output of the envelope detector 704.

The peak detection circuit 705 detects this steep peak and outputs this peak to the phase detector 706. The phase detector 706 detects the phase difference between the peak and the signal indicating the start point of the cycle of the reference spreading code generated by the spreading code start signal extraction circuit 711 from the reference spreading code, It outputs the voltage level according to the phase difference. This voltage level is smoothed by the loop filter 707 and output to the voltage controlled oscillator 708.

The voltage controlled oscillator 708 generates a clock signal having a frequency corresponding to the input voltage level and outputs it as a clock of the spread code generator 204. The spread code start signal output from the spread code start signal extraction circuit 711 is output to the code generator 204 and the baseband demodulation circuit 206 as a code synchronization signal.

The synchronizing circuit 203 and the code generator 204 constitute a kind of phase lock loop as a whole. Then, in the state where the synchronization is not established, since there is a phase difference between the correlation peak signal which is the input of the phase detector 706 and the spread code start signal, the spread code clock is advanced (or delayed), which causes The phase difference between the synchronization-specific spreading code component included in the received signal and the reference spreading code gradually decreases. Then, when the phases of the both coincide with each other, the phase difference of the phase detector 706 becomes 0, and thereafter, the phase difference is controlled so as to become 0.

After the synchronization is established, the spread code generator 204
Generates a spreading code group having the same clock and spreading code phase as the spreading code group on the transmitting side. The spread code PN0 dedicated to synchronization of these code groups is input to the carrier reproduction circuit 205.

The carrier reproducing circuit 205 despreads the received signal converted to the transmission frequency band or the intermediate frequency band which is the output of the high-frequency signal processing unit 202 by the synchronization-dedicated spreading code PN0, and despreads the transmission frequency band or the intermediate frequency band. Play carrier wave.

As a structure of the carrier reproducing circuit 205, for example, a circuit using a phase locked loop as shown in FIG. 5 is used.

In FIG. 5, the received signal and the synchronization-specific spreading code PN0 are multiplied by the multiplier 501. Then, after synchronization is established, the clock and code phase of the synchronization dedicated spreading code and the reference synchronization dedicated spreading code in the received signal match, and since the transmission side synchronization dedicated spreading code is not modulated with data, The signal is despread by the multiplier 501, and a carrier component appears at its output.

This output is then input to the band pass filter 502, and only the carrier component is extracted and output. This output is then fed to the phase detector 503, the loop
The phase-locked loop formed by the filter 504 and the voltage-controlled oscillator 505 is input to the voltage-controlled oscillator 50.
5, the signal whose phase is locked to the carrier component output from the band pass filter 502 is output as a reproduced carrier.

The reproduced carrier wave is input to the baseband demodulation circuit 206. In the baseband demodulation circuit 206, a baseband signal is generated from the reproduced carrier wave and the output of the high frequency signal processing unit 202. This baseband signal is distributed to n branches and spread code generator 20
Despreading is performed for each code division channel by the spreading code groups PN1 to PNn, which are the outputs of No. 4, and subsequently data demodulation is performed.

The baseband demodulation circuit 206 is constructed, for example, as shown in FIG. In FIG. 6, the input received signal and the reproduced carrier wave are multiplied by the multiplier 601.
The reception signal is converted into a baseband signal by removing unnecessary signals with the low-pass filter 602. This baseband signal is converted into a digital signal having a resolution of a single bit or a plurality of bits by an A / D converter 603 having a reproduction clock as a sampling period.

This digital signal is distributed to n branches, and the most significant bit of the digital signal in each branch is the spreading code group P which is the output of the spreading code generator 204.
N1-PNn and exclusive OR circuit group 604-
The exclusive OR operation is performed by 1 to n, and the exclusive OR operation is input to the adder groups 605-1 to 60n together with other bits.

In the adder groups 605-1 to 60-n, the input signal and the outputs of the register groups 606-1 to 606-1 are added for each reproduction clock pulse and output to the register groups 606-1 to 606-1. The register groups 606-1 to 606-n are reset when the leading bit of each spreading code is input, and thereafter, the result of adding the product of the received signal and the spreading code over one period of the spreading code is stored. Go.

Therefore, when the last bit of one cycle of the spread code is input, the register groups 606-1 to 606-1n store the correlation value between each cycle of the spread code and the received signal. . With respect to this correlation value, data determination is performed by the subsequent determination circuit groups 607-1 to 607-1.
The parallel demodulated data are obtained. Then, the n demodulated parallel demodulated data are converted into serial data by the parallel-serial converter 207 and output.

Next, a second embodiment of the present invention will be described.

FIG. 8 is a block diagram showing the structure of the synchronizing circuit in the second embodiment. The second embodiment also shows a case where the synchronizing circuit has a phase lock loop type configuration using a SAW convolver.

In FIG. 8, reference numerals 801 to 805 denote the first
This is the same as 701 to 705 in FIG. 7 of the embodiment. Then, the correlation peak signal output from the peak detector 805 is output to the phase detector 806.

The phase detector 806 outputs a voltage signal corresponding to the phase difference between the output of the frequency divider 809 and the correlation peak signal. This voltage signal is smoothed by the loop filter 807 and controls the output frequency of the voltage controlled oscillator 808. This output is output to the spread code generator 204 as a spread code clock. Further, this output is frequency-divided by a frequency divider 809 having the same frequency division ratio as the spread code length,
The phase detector 80 is output at the same time as the code synchronization signal.
6 is input.

In the first embodiment described above, the loop is composed of only the clock, but in the case of this embodiment, both the clock and the code synchronization signal form the loop. Therefore, it is possible to optimize the synchronization acquisition time of each loop,
Although the circuit configuration is slightly complicated as compared with the first embodiment,
Higher-speed synchronization acquisition becomes possible.

[0051]

As described above, according to the present invention,
A spreading code channel dedicated to synchronization is prepared between the code division multiplex communication devices, and a synchronization circuit using a SAW convolver that performs common code phase synchronization and clock synchronization for all channels is provided only for this channel, so that other data can be used. Since it is not necessary to provide a synchronization circuit for each of the channels, the size can be reduced.

Since the carrier wave can be reproduced by despreading the synchronization dedicated channel and the received signal can be directly converted into the baseband signal by using the reproduced carrier wave, it is possible to demodulate the data channel. The correlator can be configured with a digital signal processing circuit, and the circuit scale can be easily reduced.
There is an effect that the correlator can be easily integrated into an IC.

Further, there is an effect that a small and inexpensive communication device can be provided even when the number of code division multiplexing is large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a transmitter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a receiver in the first embodiment.

FIG. 3 is a block diagram showing a configuration of a transmitter according to a conventional code division multiplexing system.

FIG. 4 is a block diagram showing a configuration of a receiver according to a conventional code division multiplexing system.

FIG. 5 is a block diagram showing a configuration of a carrier regenerating circuit in the first embodiment.

FIG. 6 is a block diagram showing a configuration of a baseband demodulation circuit in the first embodiment.

FIG. 7 is a block diagram showing a configuration of a synchronizing circuit in the first embodiment.

FIG. 8 is a block diagram showing a configuration of a synchronizing circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 101 ... Serial-parallel converter, 102-1 to n ... Multiplier group, 103 ... Spread code generator, 104 ... Adder, 105 ... High frequency stage, 106 ... Transmit antenna, 201 ... Receive antenna, 202 ... High frequency signal processing unit , 203 ... Synchronous circuit, 204 ... Spread code generator, 205 ... Carrier reproducing circuit, 206 ... Baseband demodulating circuit, 207 ... Parallel-serial converter.

Claims (2)

[Claims] 1. An antenna means for receiving a signal from a transmission line, a modulating means for appropriately filtering and amplifying the output of the antenna means to modulate it into a predetermined frequency band signal, and an output from the output of the modulating means. Synchronization means for extracting the clock and the code phase synchronization signal of the spreading code on the transmission side included in, and a clock signal which is the output of the synchronizing means by generating the same plurality of spreading code sequences as the spreading code generating means of the transmitting device. And a spreading code generating means driven by a code phase synchronization signal, an output of the converting means for converting the signal to the predetermined frequency band signal, and a synchronization-only spreading code sequence which is the output of the spreading code generating means to generate a carrier signal. The carrier reproducing means for reproducing, the output of the converting means for converting to the predetermined frequency band signal, and the reproduced carrier wave which is the output of the carrier reproducing means, Means for reproducing the received signal, means for converting the baseband signal into a digital signal sequence, output of the digital signal sequence and the spread code generating means n.
Means for performing a correlation operation using the data spreading code sequence, the clock signal and the code phase synchronization signal output from the synchronizing means, and the correlation value output from the means for performing the correlation operation for each spreading code cycle. Demodulating means for judging and demodulating n-symbol data, wherein the synchronizing means receives the received signal or the received intermediate frequency signal as one input and the reference signal modulated by the reference spread code as the other input. , A correlation means for outputting a signal component having a center frequency which is twice the center frequency of these two input signals, and a peak component extracted from this correlation output, and the period of the spread code transmitted from this peak component Means for extracting the starting point of and outputting as a code synchronization signal,
And a means for extracting a code clock of a spread code transmitted from the peak component and outputting it as a reproduced clock signal. 2. The transmission device according to claim 1, wherein the transmission device is driven by the same clock and has n spread code sequences for data and 1 in which the code phases match in the same cycle.
Spreading code generating means for generating at least one synchronization-only spreading code sequence, modulation means for modulating each of the n data spreading code sequences output from the spreading code generating means in each of the parallel data sequences, and Addition means for linearly adding the n outputs of the modulation means and the synchronization-dedicated spreading code sequence output by the spreading code generation means, and the baseband or intermediate frequency band signal output by the addition means are transmitted in a predetermined manner. A spread spectrum communication device, comprising: a conversion means for converting to a frequency band signal, and an antenna means for transmitting the output of the conversion means to a transmission path.