JPH08167658A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] Semiconductor device and CM having an extremely shallow junction
Provided is a method for manufacturing the above semiconductor device applicable to an OS process. A glass film containing a high concentration of impurities for forming a junction is formed between a gate sidewall that is not substantially doped with impurities and a main surface of a semiconductor substrate, and the above-mentioned impurities are solidified from the glass film. Phase diffusion is performed to form a source / drain junction. [Effect] A simple process with few photoresist steps,
Shallow junction of 30nm or less can be formed, gate length 0.15
High-speed operation of complementary MOSFETs of μm or less has become possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, an extremely fine complementary MOSF
The present invention relates to a semiconductor device having a structure suitable for ET (metal-semiconductor-oxide film field effect transistor) and a method for manufacturing a semiconductor device capable of easily forming the semiconductor device.

[0002]

2. Description of the Related Art As is well known, in the conventional semiconductor integrated circuit, high integration and high speed have been realized by miniaturization of processing dimensions. In order to further increase the integration and speed of these, MOSFET (Metal-Oxide-Semiconductor Fie)
According to the proportional reduction rule of ld Effect Transistor), in addition to miniaturization in the planar direction, it is necessary to reduce the thickness of the gate oxide film and the junction depth of the source and drain in the depth direction as well.

Conventionally, in forming a source / drain junction,
Ion implantation has been commonly used. However, in a fine device with a gate length of 0.15 μm or less,
In order to completely suppress the short channel effect, a shallower junction is required. Instead of the above ion implantation method, solid-phase diffusion from an oxide film (boron glass film, phosphorus glass film) doped with boron and phosphorus is required. It is proposed to use the method. For example, an n-channel M with a gate length of 0.04 μm
An example of a trial manufacture of OSFET using this method is 1993.
・ International Electron Devices Meeting (1993 International Electron Devices Me
eting, Technical Digest, p. 119), and a junction depth of 10 nm, which cannot be realized by the ion implantation method, has been achieved. In this method,
As shown in (a), when the deep n ⁺ (or p ⁺ ) layer 21 is formed by the ion implantation method, the side wall (sidewall) 23 of the gate electrode 22 which acts as a mask is made of phosphorus glass or boron glass. Form. In this way, the deep n ⁺ formed by ion implantation is
When the (or p ⁺ ) layer 21 is activated by heat treatment, impurities are simultaneously diffused from the gate sidewall 23,
A shallow n ⁺ (or p ⁺ ) layer 24 is formed.

[0004]

However, selective doping is performed by the above-mentioned conventional method, and complementary MOSFE is used.
In order to form T (CMOS), it is necessary to form gate side walls 23 made of phosphorus glass for n-MOS and boron glass for p-MOS on both sides of the gate electrode 22, respectively, which makes the process extremely complicated. become. Furthermore, since a glass film having high hygroscopicity is used as the side wall 23 of the gate, there is a problem that the reliability of the device is lowered, and a solution is required.

An object of the present invention is to solve the above problems of the conventional semiconductor device and the manufacturing method thereof, to make the junction depth extremely shallow, and to provide a highly reliable CMOS and an easy CMOS. It is to provide a manufacturing method that can be manufactured.

Another object of the present invention is to provide a semiconductor in which a highly reliable CMOS can be easily formed by a simple process without losing the advantages of the shallow junction forming method by the solid phase diffusion method. An object of the present invention is to provide a device and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention provides a thin layer in which an impurity is highly doped at a portion where a gate side wall made of a Si oxide film (SiO ₂ film) contacts a Si substrate. Is formed, and impurities are diffused from this portion into the Si substrate to form shallow source and drain diffusion layers.

That is, as shown in FIG. 2B, a thin phosphorus glass (or boron glass) film 25 having a thickness of about several tens nm is formed along the surface of the semiconductor substrate 10 and the side portion of the gate electrode 22. Formed, and after removing unnecessary portions by etching, a Si oxide film having a thickness of about 0.1 μm is formed on the entire surface, and this Si oxide film is subjected to overall reactive ion etching to form a gate sidewall 111. . If the phosphorus glass (or boron glass) film 25 is left only in the n-MOS (or p-MOS) formation region, a shallow source, due to solid phase diffusion from the phosphorus glass (or boron glass) film 25, The drain region 24 is formed, and the CMOS can be easily formed.

FIG. 2C shows an example in which a thin phosphorus glass (or boron glass) film 26 serving as a diffusion source is formed only between the gate sidewall 110 and the semiconductor substrate 10. In this case, phosphorus (or boron) is added to the Si substrate 1
Pre-adsorbed on the surface of 0, thickness 0.1 μm
After forming a Si oxide film of a certain degree on the entire surface, the entire surface is subjected to reactive ion etching to form the gate sidewall 111. In this case, the previously adsorbed phosphorus (or boron) is diffused into the lower portion of the gate sidewall 111, and a thin phosphorus glass having a thickness of 10 nm or less (or, at the portion contacting the surface of the Si substrate 10). A boron glass) film 26 is formed. If the area other than the n-MOS (or p-MOS) forming area is masked with an oxide film or the like and the adsorption is performed, phosphorus (or boron) is formed.
Does not adsorb to the masked portion, so that the selective doping is performed only in the formation region to form the shallow source / drain regions 24 and the CMOS can be easily formed.

[0010]

The phosphorus glass (or boron glass) film 25 used as a diffusion source for solid-phase diffusion has a very small thickness (for example, 30 nm and 10 nm), and therefore, most of the gate sidewalls are n-MOS and p-MOS. Both are formed of a common non-doped Si oxide film. Therefore, in order to form the side wall 111, the conventional process may be performed once.
The difference between the widths of the sidewalls of the -MOS and the p-MOS can be suppressed to a negligible level of 30 nm or less. Moreover, since the non-doped Si oxide film does not have hygroscopicity, there is no possibility that the element characteristics will be deteriorated by moisture.

[0011]

【Example】

<Example 1> In this example, an n-MOS source / drain junction is formed by implanting As ions, and a shallow p-MOS source is formed by diffusion from a boron glass film.
This is an example of forming a drain junction. As shown in FIG. 1A, the p-well 1 is formed on the Si substrate 10 using a well-known method.
After forming the 1 and n wells 12, the well known LOCOS
By the method, local oxidation was performed to form an oxide film 13, and elements were isolated.

The gate oxide film 14 and the gate electrode 15 are formed by using the well-known film forming method and the selective etching method, the oxide film 14 on the source and drain forming regions is removed with a hydrofluoric acid aqueous solution, and then the well-known CVD method is used. A boron glass film 16 having a thickness of 20 nm was formed on the entire surface by (chemical vapor deposition).

As shown in FIG. 1B, a well-known photolithography technique is used to cover only the p-MOS formation region with a resist mask 17, and As ⁺ ions 18 are ion-implanted to form an As ion-implanted region. 19 was formed.

As shown in FIG. 1C, dry etching is performed using the resist mask 17 as a mask to remove the boron glass film 16 formed in the n-MOS region, and the As ions are removed. The surface of the driving region 19 was exposed.

After removing the resist film 17, FIG.
As shown in FIG. 3, an oxide film 110 having a thickness of 0.1 μm was formed on the entire surface, and further, reactive ion etching was performed on the entire surface to form a gate sidewall 111 as shown in FIG.

Through the above steps, the p-MOS gate side wall 111 having the boron glass film 16 as a part thereof is formed. Then, As ions and boron ions were implanted respectively by a usual selective ion implantation method using a photoresist film as a mask to form deep n ⁺ layers and p ⁺ layers. After heat treatment (950 ° C. 10 seconds),
The ion-implanted layer was activated to form the n ⁺ source / drain regions 112. At this time, boron diffused from the gate side wall 111, and as shown in FIG. 1F, the p ⁺ source / drain region 113 having the shallow junction was formed.

According to this embodiment, a shallow junction having a junction depth of 20 nm and a sheet resistance of 2 kΩ / □ can be formed, and a CM having a gate length of 0.15 μm can be formed without causing a short channel effect.
It was confirmed that the OS operates at high speed. In this embodiment,
The selective doping of the n ⁺ and p ⁺ shallow junction portions can be performed in a self-aligned manner in one photoresist step, which is simplified as compared with the conventional method which requires two steps.
A shallow junction of the p ⁺ layer could be realized without complicating the process.

<Embodiment 2> This embodiment is an example in which a shallow junction of a CMOS is formed by using a method of selectively adsorbing boron on silicon. As shown in FIG.
As in the first embodiment, the p-MOS region is covered with the photoresist film 17 by using a normal photoresist process, and n-M is formed.
As ⁺ ions 18 were implanted only in the OS region to form As ion-implanted regions (n ⁺ regions) 19. After removing the photoresist film 17, the surface was washed with an aqueous solution of hydrofluoric acid to remove the oxide film 14. Next, the surface was washed with water and dried. In this step, the As ion-implanted region 19 was removed.
A natural oxide film 31 having a thickness of about 1 nm was formed only on the surface of the. This sample was introduced into an ultra-high vacuum apparatus, B ₂ H ₆ 32 was adsorbed at a substrate temperature of 700 ° C., and boron was formed only on the Si surface on the p-MOS region as shown in FIG. 3B. Selectively adsorbed on the Si surface on the n-MOS region,
Boron did not adsorb.

Next, as shown in FIG. 3C, a Si oxide film 110 having a thickness of 0.1 μm was formed. At this time,
Boron, which was selectively adsorbed only on the Si surface on the p-MOS region, was diffused to the lower portion of the Si oxide film 11 to form the boron glass film 33. The entire surface is subjected to reactive ion etching to form a p-MOS gate side wall 1 having a boron glass film 33 under it as shown in FIG.
11 was formed. Thereafter, a deep n-thickness is obtained by a usual selective ion implantation method using a photoresist film as a mask.
^{+ And} p ⁺ layers were formed. Heat treatment (950 ° C., 10 seconds) is performed to activate the ion-implanted layer to form the n ⁺ source / drain regions 112, and FIG.
As shown in (e), the p ⁺ source / drain region 113 having a shallow junction was formed by the diffusion of boron from the gate sidewall 111.

In this embodiment, the junction depth is 20 nm,
A CM with a gate length of 0.15 μm can be formed without forming a short channel effect because a shallow junction with a sheet resistance of 2 kΩ / □ can be formed.
It was confirmed that the OS operates at high speed. In this embodiment, B
By utilizing the selective adsorption phenomenon of ₂ H ₆ , the process could be further simplified in comparison with Example 1 as well as the conventional method.
The source of B is HBO ₂ . B ₂ O ₃ may be used, and in order to prevent the adsorption of boron, instead of using a natural oxide film, a thermal oxidation method in water vapor is used.
A method may be used in which a thick oxide film is formed on the ⁺ layer and the thin oxide film grown on other portions is removed by etching with a hydrofluoric acid aqueous solution.

Needless to say, only the oxide film 14 on the p-MOS region may be etched and removed again (the oxide film immediately below the gate is left) by using the photoresist process once again.

<Embodiment 3> In the present embodiment, an n-type which constitutes a CMOS using a phosphorus glass film and a boron glass film.
This is an example of forming shallow junctions of MOS and p-MOS, respectively. In the same manner as in Example 1, the Si substrate 10
After forming the p-well 11 and the n-well 12 on the substrate, an oxide film 13 is formed by the well-known LOCOS method to perform element isolation. Further, as shown in FIG. 4A, after forming the gate oxide film 14 and the gate electrode 15, the gate oxide film 14 on the source / drain regions was removed with a hydrofluoric acid aqueous solution.

4B, the boron glass film 16 is formed, and is removed from the n-MOS region by ordinary photolithography and dry etching. Then, as shown in FIG. -This was left only on the MOS area.
Next, as shown in FIG. 4C, after forming the phosphorus glass film 41 and the Si oxide film 110, the entire surface is subjected to reactive ion etching, and as shown in FIG. 111 was formed. Between the gate side wall 111 and the substrate surface or the gate electrode 15, a phosphorus glass film 41 is used for n-MOSS and a boron glass film 16 is used for p-MOS.
And the phosphorus glass film 41 were formed respectively.

By heat treatment at 950 ° C. for 10 seconds, phosphorus and boron are diffused from the phosphorus glass film 41 and the boron glass film 16 into the Si substrate, respectively.
As shown in (e), n ⁺ source / drain regions 112 and p ⁺ source / drain regions 113 having shallow junctions were formed.

According to this embodiment, a shallow junction having a junction depth of 10 nm and a sheet resistance of 2 kΩ / □ can be formed, and a CMOS having a gate length of 0.1 μm can be formed without causing a short channel effect.
Was confirmed to operate at high speed. Needless to say, the formation order of the phosphorus glass film and the boron glass film may be reversed. Further, arsenic glass formed by diffusing arsenic may be used instead of the phosphorus glass film.

<Embodiment 4> In this embodiment, an n-MOS and a p-type are formed by utilizing the selective adsorption of a phosphorus glass film and B ₂ H ₆ gas.
In this example, a shallow MOS junction is formed. As shown in FIG. 5A, as in Example 1, Si
After the p well 11 and the n well 12 are formed on the substrate 10, the oxide film 1 for element isolation is formed by using the well-known LOCOS method.
3 was formed, and the gate oxide film 14 and the gate electrode 15 were further formed. Next, a phosphorous glass film 5 having a thickness of 10 nm
1 is formed and removed from the p-MOS region by ordinary photolithography and dry etching.
I left this only on the area.

Next, as shown in FIG. 5B, at a substrate temperature of 700 ° C., B ₂ H ₆ gas 32 was adsorbed on the p-MOS region by about one atomic layer. At this time, B ₂ H ₆ gas molecules 32
On the phosphor glass film 51, Si in the p-MOS region
It was confirmed that only about 1/100 of the surface of the substrate was adsorbed. When an undoped SiO ₂ film was formed on the phosphor glass film 51, the amount of B ₂ H ₆ adsorbed was further reduced.

As shown in FIG. 5C, the thickness is 0.1 μm.
A Si oxide film 110 having a thickness of m was formed, and a boron glass film 33 was formed on the portion where B ₂ H ₆ was adsorbed. Thereafter, similarly to the first embodiment, the formation of the gate sidewall 111 shown in FIG. 5D, ion implantation, and short-time annealing are performed to perform the boron glass film 33 and the phosphorus glass film 51 between the gate sidewall 111 and the substrate. Boron and phosphorus were diffused from the substrate to form p ⁺ source / drain regions 113 and n ⁺ source / drain regions 112 having shallow junctions, as shown in FIG. 5 (e).

In this embodiment, the junction depth is 10 nm,
A shallow junction with a sheet resistance of 2 kΩ / □ can be formed, and a CMO with a gate length of 0.1 μm can be obtained without causing a short channel effect.
It was confirmed that S operates at high speed. In the case of the third embodiment, the boron glass film 16 needs to have a thickness of 30 nm or more in order to mask the diffusion of phosphorus from the phosphorus glass film 41. The width of the gate sidewall becomes larger than the width of the gate sidewall of the n-MOS. However, in this embodiment, since the phenomenon of selective adsorption of impurities is used, the phosphorus glass film 1
The thickness of 8 can be approximately 10 nm, and such a problem does not occur. In addition, boron glass film and PH
Similar results could be obtained by combining adsorption of ₃ gases (or P and Sb which are solid sources).

<Embodiment 5> This embodiment is the same as the above Embodiment 4 except that the B ₂ H ₆ gas is selectively adsorbed to the p-MOS forming region and then Si is grown to lower the resistance of the p ⁺ layer. Here is an example. First, processing is performed in the same manner as in the above-described first embodiment, and FIG.
As shown in FIG.
After forming the well 12, the oxide film 13 was formed by the well-known LOCOS method, the gate oxide film 14 and the gate electrode 15 were formed, and the Si ₃ N ₄ side wall protective film 61 having a thickness of 10 nm or less was formed. The gate electrode 15 was covered with a thin oxide film 62.

Next, after forming a phosphor glass film 51 having a thickness of 10 nm, selective etching is performed by ordinary photolithography and dry etching, and as shown in FIG. 6B, only on the n-MOS region. Left, p-MO
It was removed from the S region.

As shown in FIG. 6C, the substrate temperature 70
At 0 ° C., 0.2 atomic layer of B ₂ H ₆ gas 32 was adsorbed. At this time, B ₂ H ₆ molecules were adsorbed on the phosphor glass film 51 only about 1/100 on the Si surface.

Next, using the well-known UHV-CVD method,
A Si film 63 was selectively epitaxially grown to a thickness of 5 nm (this method is known as δ-doping). Less than,
By the same process as in Example 4, as shown in FIG. 6D, formation of the gate sidewall 111, ion implantation, and short-time annealing are performed to remove boron and phosphorus from the δ-doped layer and the phosphorus glass foil 51. Diffusion, Figure 6 (e)
, The p ⁺ source / drain region 113 and the n ⁺ source / drain region 112 having a shallow junction
Was formed.

According to this embodiment, a shallow junction having a junction depth of 10 nm and a sheet resistance of 1 kΩ / □ can be formed, and a CMOS having a gate length of 0.05 μm can be obtained without causing a short channel effect.
Was confirmed to operate at high speed. Since the Si ₃ N ₄ side wall protective film 61 has a very small thickness of 10 nm or less, there is no fear that the impurity diffusion layer and the gate electrode will be offset. Rather, the sidewall protective film 61 apparently reduces the diffusion length of impurities in the channel direction, and has an effect of suppressing an increase in overlap capacitance. Needless to say, the side wall protective film 61 can be applied to the first to fourth embodiments. Further, the n ⁺ shallow junction may be formed by δ doping of Sb. In this case, first, a δ-doped layer of Sb is formed, and boron doping may be performed using a natural oxide film selectively grown on the n ⁺ layer as in the second embodiment.

[0035]

According to the present invention, it is possible to form an extremely shallow source / drain junction of, for example, 30 nm or less by a simple process. As a result, the gate length is 0.15
High-speed operation of an extremely fine complementary MOSFET of less than μm is realized without causing a short channel effect,
Moreover, it becomes possible to form such an excellent complementary MOSFET easily and at high throughput.

[Brief description of drawings]

FIG. 1 is a process drawing showing a first embodiment of the present invention,

FIG. 2 is a sectional view showing a main part of a conventional MOSFET and a MOSFET of the present invention,

FIG. 3 is a process drawing showing a second embodiment of the present invention,

FIG. 4 is a process drawing showing a third embodiment of the present invention,

FIG. 5 is a process drawing showing a fourth embodiment of the present invention,

FIG. 6 is a process drawing showing a fifth embodiment of the present invention.

[Explanation of symbols]

10 ... Si substrate, 11 ... p well, 12 ...
... n-well, 13 ... LOCOS oxide film, 14 ...
Gate oxide film, 15 ... Gate electrode, 16 ... Boron glass film, 17 ... Photoresist film, 19 ... A
s ⁺ ion implantation region, 110 ... Si oxide film,
111 ... Gate sidewall, 112 ... N ⁺ source / drain layer, 113 ... P ⁺ source / drain layer.

Claims (22)

[Claims] 1. A source and a drain having a second conductivity type opposite to the first conductivity type, which are formed in a surface region of a semiconductor substrate having a first conductivity type and are spaced apart from each other with a predetermined distance therebetween. A gate electrode formed on the main surface of the semiconductor substrate between the source and the drain with a gate insulating film interposed therebetween, and a sidewall insulating film selectively formed on a side portion of the gate electrode. A semiconductor device characterized in that an insulating film doped with an impurity having the second conductivity type is interposed between the side wall insulating film and the upper surfaces of the source and the drain. 2. The semiconductor device according to claim 1, wherein the impurity-doped insulating film extends from upper surfaces of the source and drain along a side portion of the gate electrode. 3. The gate electrode, the source and the drain are respectively provided in a complementary field effect transistor.
-The semiconductor device according to claim 1 or 2, which is a gate electrode, a source, and a drain of a channel MOS transistor. 4. The semiconductor according to claim 1, wherein the impurity having the second conductivity type is boron, and the insulating film doped with the impurity is a boron glass film. apparatus. 5. The gate electrode, the source and the drain are respectively provided in a complementary field effect transistor.
-The semiconductor device according to claim 1 or 2, which is a gate electrode, a source, and a drain of a channel MOS transistor. 6. The impurity having the second conductivity type is phosphorus or arsenic, and the insulating film doped with the impurity is
The semiconductor device according to claim 1, which is a phosphorous glass film or an arsenic glass film. 7. The semiconductor device according to claim 1, wherein the impurity having the second conductivity type is arsenic. 8. The impurity-doped insulating film having the second conductivity type is formed between the sidewall insulating film of the p-channel MOS transistor and the upper surfaces of the source and drain, and the insulating film of the n-channel MOS transistor is formed. The semiconductor device according to claim 1, wherein the semiconductor device is not formed between the sidewall insulating film and the upper surfaces of the source and the drain. 9. The insulating film doped with impurities having the second conductivity type is formed between the sidewall insulating film of the p-channel MOS transistor and the n-channel MOS transistor and the upper surfaces of the source and the drain, respectively. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 10. A step of forming a gate electrode having a predetermined shape on a main surface of a semiconductor substrate having the first conductivity type via a gate insulating film, and a second conductivity opposite to the first conductivity type. A step of forming a glass film containing a high concentration of impurities having a mold on the main surface of the semiconductor substrate in contact with a side portion of the gate electrode, and diffusing the impurities from the glass film into the semiconductor substrate to form a source. And a step of forming a drain, a method of manufacturing a semiconductor device. 11. The step of forming the glass film on the main surface of the semiconductor substrate in contact with the side portion of the gate electrode comprises laminating the glass film and a silicon oxide film substantially undoped with impurities. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the anisotropic etching is performed after the entire surface is formed. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the glass film is a boron glass film, a phosphorus glass film or an arsenic glass film. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the thickness of the boron glass film or the phosphorus glass film is 30 nm or less. 14. The glass film is formed by adsorbing a source containing the impurity on the surface of the semiconductor substrate and then forming a silicon oxide film substantially not doped with the impurity on the entire surface. Claim 1 characterized by the above-mentioned.
0. A method for manufacturing a semiconductor device according to item 0. 15. An n-type well and a p-type are provided in a surface region of a semiconductor substrate.
Forming the wells adjacent to each other, and forming a gate electrode on each of the n-type well and the p-type well via a gate insulating film, and then forming a glass film heavily doped with p-type impurities. Forming the entire surface, forming an n-type source and drain into the p-type well by selectively doping an n-channel MOS transistor in a region where an n-channel MOS transistor is to be formed, and forming the n-channel A step of selectively removing the glass film formed on the region where the MOS transistor is to be formed, and a silicon oxide film substantially free of impurities are formed on the entire surface and then anisotropic etching is performed on the entire surface. A semiconductor device comprising: a step of performing and a step of diffusing impurities from the glass film into the n-type well to form a p-type source and drain. Manufacturing method. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the p-type impurity and the n-type impurity are boron and phosphorus or arsenic, respectively. 17. An n-type well and a p-type are provided in the surface region of the semiconductor substrate.
Forming the wells adjacent to each other, and forming the gate electrodes on the n-type well and the p-type well through the gate insulating film, respectively, and then forming the n-channel MOS transistor only in the region to be formed. Selectively doping a type impurity to form an n-type source and drain, selectively depositing a diffusion source of a p-type impurity only on the exposed surface of the n-type well, and Undoped silicon oxide film is formed on the entire surface, and the p-type silicon oxide film is formed between the silicon oxide film and the n-type well.
The step of forming a glass film in which the diffusion source of the type impurities is highly doped, and the entire surface anisotropic etching are performed.
Of the silicon oxide film and the glass film, a step of leaving the part formed on the semiconductor substrate on the side portion of the gate electrode and in the vicinity thereof and removing it from the other part, and from the glass film, A method of manufacturing a semiconductor device, comprising the step of diffusing impurities in an n-type well to form a p-type source and drain. 18. The p-type impurity B is used as the diffusion source.
_The method of manufacturing a semiconductor device according to claim 17, wherein the method is selected from the group consisting of ₂ H ₆ , HBO ₂ and B ₂ O ₃ . 19. An n-type well and a p-type are formed in the surface region of a semiconductor substrate.
Forming the wells adjacent to each other, and forming a gate electrode on each of the n-type well and the p-type well via a gate insulating film, and then forming a p-channel MOS transistor on the entire surface. , A step of forming a glass film heavily doped with p-type impurities, a step of forming a glass film heavily doped with n-type impurities, and a silicon oxide not substantially doped with impurities A step of forming a film on the entire surface, and an anisotropic etching on the entire surface to form the silicon oxide film, the glass film heavily doped with p-type impurities, and the glass film heavily doped with the n-type impurities, A step of leaving the gate electrode side portion and the vicinity thereof on the surface of the semiconductor substrate and removing it from other portions, and a glass film and a top portion in which the p-type impurity is highly doped. A semiconductor device comprising a step of diffusing the p-type and n-type impurities from a glass film heavily doped with n-type impurities to form p-type and n-type sources and drains, respectively. Production method. 20. The method of manufacturing a semiconductor device according to claim 19, wherein the p-type and n-type impurities are boron and phosphorus or arsenic, respectively. 21. An n-type well and a p-type are formed in a surface region of a semiconductor substrate.
And forming a gate electrode on each of the n-type well and the p-type well via a gate insulating film, and then forming a glass film highly doped with n-type impurities. a step of forming an n-channel MOS transistor on the entire surface of a region to be formed, a step of selectively depositing the diffusion source of the p-type impurity only on the exposed surface of the n-type well, and a step of substantially eliminating the impurities. And a step of forming a silicon oxide film which is not doped on the entire surface and forming a glass film in which the diffusion source of the p-type impurity is highly doped between the silicon oxide film and the n-type well. The silicon oxide film, the glass film heavily doped with the n-type impurities, and the glass film heavily doped with the diffusion source of the p-type impurities are subjected to isotropic etching. A step of leaving a portion formed on the semiconductor substrate on the side portion of the gate electrode and in the vicinity thereof and removing it from the other portion, and a glass in which the diffusion source of the p-type impurity is highly doped. A step of forming p-type and n-type sources and drains by diffusing p-type and n-type impurities into the n-type and p-type wells from a film and a glass film heavily doped with n-type impurities, respectively. A method of manufacturing a semiconductor device, comprising: 22. The method of manufacturing a semiconductor device according to claim 15, wherein the boron glass film, the phosphorus glass film or the arsenic glass film has a thickness of 30 nm or less.