JPH08167618A - Method for manufacturing power semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] When the area of a chip of an element having a gate electrode for controlling the main current is increased, a defect that causes a breakdown voltage between the gate electrode and the main electrode is likely to occur, and the chip Solve the problem of low yield. [Structure] A gate electrode is divided into a plurality of parts, and each gate electrode 6
A gate electrode connecting portion 6a having a through hole 22 is provided on the extension of the gate electrode, and a gate pad electrode 9 is formed on the gate electrode connecting portion 6a. The gate pad electrode 9 connected to the gate electrode 6 whose measured breakdown voltage does not satisfy the specified value insulates the contact hole 21 with the insulating film 20, and the gate terminal 25a is formed on the upper surface of this insulating film 20. 9 and the gate terminal 25a are separated from each other, the through-hole 22 is closed by the emitter terminal 25b, the emitter terminal 25a and the gate electrode contact portion 6a are short-circuited, and the gate pad electrode connected to the gate electrode 6 satisfying the specified value. Reference numeral 9 closes the contact hole 21 with a gate terminal 25a and connects it to the gate terminal 25a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor such as an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) MOS field effect transistor which has a gate electrode for controlling a main current and which is turned on / off by a gate voltage. The present invention relates to a method of manufacturing an element.

[0002]

2. Description of the Related Art In a semiconductor device for electric power as described above, a semiconductor chip is fixed on a substrate made of metal or the like, and a main electrode for supplying a main current has a main terminal outside the chip by a conductor wire bonded to the electrode surface. Connected to. The gate electrode insulated from the main electrode and the gate terminal are connected by a conductor wire bonded to a gate pad portion provided on the electrode surface. Increasing the chip area of such an element realizes an increase in the current capacity per chip and a reduction in the on-voltage, and at the same time, the area ratio of the guard ring section and the gate pad section to the entire element for improving the breakdown voltage is increased. Since it can be lowered, there are advantages such as improvement in utilization rate of semiconductor wafers and reduction in the number of wire bonding when assembling into a module or the like.

FIG. 5 is a cross-sectional view of an example of a conventional IGBT unit cell. In such a structure, a p well 2 independent on one main surface of a semiconductor chip is diffused on the surface of a high resistance n ⁻ layer 1. Made by. Further, an emitter region 3 for injecting electrons into the n ⁻ layer 1 is formed in the surface layer of the p well 2. Further, in order to form a MOS channel 4 for injecting electrons from the emitter layer 3 to the n ⁻ layer 1 at the end of the p well 2, a thin gate oxide film 5 is formed on the surface of the end of the p well 2, for example, A gate electrode 6 made of crystalline silicon is provided. The gate electrode 6 is entirely covered with an oxide film 7, and an emitter electrode 8 that contacts the surfaces of the p well 2 and the emitter region 3 through a window formed in the oxide film 7 is formed by, for example, Al vapor deposition. On the extended portion of the gate electrode 6, a gate pad electrode 9 is formed by vapor deposition and separation at the same time as the emitter electrode 8.
To contact. Since the gate electrode 6 and the emitter electrode 8 are separated by the oxide film 7, a voltage can be applied between the gate and the emitter. A p collector layer 12 is provided on the lower surface side of the n ⁻ layer 1 with an n buffer layer 11 in between, and a collector electrode 13 in contact with the surface of the collector layer 12 is formed by, for example, Al vapor deposition.

FIG. 6 is a plan view of a conventional IGBT chip as seen from the emitter electrode side. As shown in FIG. 5, the emitter electrode 8 covering the gate electrode formed within the outline shown by the dotted line is also used. The emitter lead wire 14 is bonded, and the gate lead wire 15 is bonded to the gate pad electrode 9 exposed at the window of the emitter electrode 8 as shown in FIG. A guard ring 17 for forming a breakdown voltage between the emitter and the collector is formed on the periphery of the chip.

[0005]

However, as one of the problems in increasing the area of a chip, there is a problem of withstand voltage failure between the gate and the emitter in the case of the IGBT and between the gate and the source in the case of the MOSFET. is there. For example, in the case of an IGBT, the channel is opened / closed by the voltage of the gate electrode to turn on / off the collector current. Gate. If the emitters are short-circuited or if the withstand voltage is insufficient, the collector current cannot be controlled normally.

Further, in the structure described above, for example, when a hole or a defect other than the mask design is generated in the oxide film during the photo process, the polycrystalline silicon layer serving as the gate electrode comes into contact with the emitter electrode. Further, when the separation between the emitter electrode and the gate pad electrode or the gate liner, which is deposited at the same time as the emitter electrode, is poor, the gate-emitter short circuit occurs. In addition, if there is a defect in the gate oxide film under the gate electrode, the breakdown voltage between the gate and the emitter also becomes defective.

If there is even one such defect in the chip, the breakdown voltage between the gate and the emitter becomes poor, and the chip cannot be used. Even if the photo process is improved, it is inevitable that some defects will occur in the wafer.
The larger the chip area, the lower the chip yield.
It is an object of the present invention to provide a method of manufacturing a power semiconductor device that does not disable the entire chip even if a gate-emitter short circuit occurs from such a viewpoint.

[0008]

In order to achieve the above-mentioned object, a main electrode for supplying a main current to one main surface of a semiconductor substrate and a plurality of main current controls insulated by the main electrode and a gate insulating film are provided. In a method for manufacturing a power semiconductor device, the gate electrode for use in a power semiconductor device is provided, and an extension portion of the gate electrode is provided with a gate pad electrode for connecting to the gate electrode by a conductor. A step of providing a gate pad electrode respectively, a step of measuring the breakdown voltage between each gate electrode and the main electrode on the same main surface of the semiconductor substrate, and a whole main surface is covered with an insulating film,
The step of forming a hole in the insulating film on the main electrode to form a connection hole for connecting the main electrode with a conductor, and the interlayer insulating film covering the surface of the gate electrode whose withstand voltage measured value does not satisfy the specified value and the interlayer insulating film. The step of forming a through hole that penetrates the main electrode formed on the surface of the film and the insulating film covering the main electrode, and the insulating film on the gate pad electrode connected to the gate electrode whose breakdown voltage measurement value satisfies the specified value. The method includes a step of providing a gate contact hole, a step of covering the main electrode with a metal film that closes the through hole, and a step of covering the gate pad electrode with a metal film that closes the gate contact hole.

Further, in the step of forming the through hole and the gate contact hole in the insulating film, after patterning is performed using the negative type photoresist film coated on the insulating film, the through hole and the gate contact hole are formed in unnecessary places. Re-exposure to leave the resist film by etching, leaving the insulating film where the through hole and the gate contact hole are unnecessary, and forming the through hole and the gate contact hole where the through hole and the gate contact hole are required. To do. It is effective to use a negative photosensitive insulating film for this insulating film. Further, it is preferable to use a negative photosensitive polyimide for this negative photosensitive insulating film.

[0010]

[Function] By dividing the gate electrode into a plurality of parts, it is possible to connect only the non-defective gate electrode having a normal breakdown voltage between the main electrode and the gate electrode to the gate terminal through the gate pad electrode. However, for this reason, the gate pad electrode is covered with an insulating film to open a contact hole, and the contact hole on the gate pad electrode connected to the defective gate electrode is an insulating film. The gate pad electrode, which is closed and connected to the gate electrode of the non-defective part, is connected to the gate terminal through the contact hole. As a result, the control signal voltage is not input to the gate electrode of the defective part that is not connected to the gate terminal, so that normal operation is not hindered. Furthermore, in order to prevent malfunction due to the potential floating of the gate electrode not connected to the gate terminal, it is preferable to short-circuit with the main electrode on the main surface of the same semiconductor substrate. If a through hole is opened in the insulating film between them and it is closed with a metal film,
It can be easily connected to the main electrode.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an IGBT manufactured by utilizing the present invention.
A cross-sectional view of the chip is shown, (a) shows a cross section of a non-defective part in which the breakdown voltage between the gate electrode and the emitter electrode has reached a specified value, and (b) shows the breakdown voltage between the gate electrode and the emitter electrode. The sectional view of the defective part which did not reach the specified value is shown. Here, the same elements as those in FIG. 6 of the conventional example are designated by the same reference numerals. The buffer layer 11, the collector layer 12, and the collector electrode 13 are omitted. The size of the IGBT chip is 20 mm square, the polycrystalline silicon layer forming the gate electrode is divided into eight, and one gate electrode is about 4
mm square. And the size of the gate pad electrode is
It is 0.3 mm square.

Next, the manufacturing process will be described. After the structure of each unit cell is formed by a method similar to the conventional method, the breakdown voltage between each divided gate electrode 6 and the emitter electrode 8 is measured, and the quality of each unit cell is determined. Normal,
A unit cell having a gate-emitter breakdown voltage of 35 V or higher is defined as a non-defective part. Next, the IGBT chip is covered with an insulating film 20 made of polyimide resin having a thickness of 4 μm, for example. Then, it is baked at 90 ° C. for 30 minutes and further at 350 ° C. for about 1 hour to harden the insulating film 20. A negative photoresist is coated on the insulating film 20, and a part of the photoresist on the defective emitter electrode 8 and a part of the photoresist on the non-defective gate pad electrode 9 are left to be exposed to ultraviolet light. Expose. Then, for the defective part, a through hole 22 reaching the gate electrode connecting part 6 is opened in the insulating film 20, the emitter electrode 8 and the interlayer insulating film 7, and for the non-defective part, the contact hole 21 reaching the gate pad electrode 9 is insulated. Open to membrane 20. Next, a metal film is deposited on the emitter electrode 8 and the gate pad electrode 9 via the insulating film 20 to close the through hole 22 and the contact hole 21, and the emitter terminal 25b and the gate terminal 25a.
To form. Next, a process of forming the contact hole 21 and the through hole 22 will be described.

FIG. 2 is a process explanatory view of the first embodiment for forming a contact hole in a non-defective part and a through hole in a defective part. The negative photoresist 30 is covered, and a photosensitive portion 60 and an unexposed portion 61 are formed on the photoresist by exposure through a photomask and patterned (FIG. 9A). At this stage, the non-exposed portion 61 is not exposed to the photoresist in the portions where the contact hole and the through hole are formed in both the non-defective portion and the defective portion.
Next, only the photoresist of the unexposed portion 61, which is the portion where the through hole of the non-defective portion is formed and the portion where the contact hole of the defective portion is formed, is exposed to be the exposed portion 62 (FIG. 6B). The photoresist is etched to remove the photoresist in the unexposed portion including the portions where the contact hole and the through hole are formed, and the etching hole 24 is formed (FIG. 7C). A contact hole 21 and a through hole 22 are formed in the insulating film 20 using the photoresist as a mask (FIG. 3D). The photoresist is removed ((e) in the figure). A metal film is coated so as to close the contact hole 21 and the through hole 22 to form a gate terminal 25a and an emitter terminal 25b (FIG. 6 (f)). Here, a connection hole 23 for opening a window in the insulating film on the emitter electrode and connecting to the emitter terminal
The step of forming (FIG. 1A) is omitted.

FIG. 3 is a process explanatory diagram of a second embodiment using a negative photosensitive insulating film (photosensitive polyimide or the like).
The insulating film 20a is covered and exposed through a photomask to form a photosensitive portion 60 and an unexposed portion 61 on the insulating film 20a, and patterning is performed (FIG. 9A). At this stage, neither the non-defective part nor the defective part is exposed to the insulating film at the location where the contact hole and the through hole are formed. Next, the non-photosensitive portion 61 at the portion where the through hole of the non-defective portion is formed and at the portion where the contact hole of the defective portion is formed.
This insulating film is exposed to light to form a photosensitive portion 62 (FIG. 7B).
The insulating film is etched to form the contact hole 21 and the through hole 22 in the unexposed portion, thereby forming the etching hole 24b by etching the insulating film to form the contact hole 21 and the through hole 22 (FIG. 7C). . A metal film is coated so as to close the contact hole 21 and the through hole 22, and a gate terminal 25a and an emitter terminal 25b are formed (FIG. 7 (d)). Also here, the step of forming a window in the insulating film 20a on the emitter electrode 8 to form the connection hole 23 and forming the emitter terminal 25b thereon is omitted. When photosensitive polyimide is used for the insulating film, the photoresist becomes unnecessary, and the same effect as in the first embodiment can be obtained by directly exposing the polyimide. In this case, the steps of applying and stripping the photoresist are unnecessary, and there is a great effect in shortening the steps.

FIG. 4 is a diagram for explaining a method of irradiating the photoresist with ultraviolet rays at a portion where a through hole is formed in a non-defective portion and a portion where a contact hole is formed in a defective portion to be exposed.
The semiconductor wafer 40 is placed on the XY stage 41, and light is emitted from the optical nozzle 42 to a predetermined location.

[0016]

According to the present invention, when the gate electrode of one chip is divided and only the gate electrode of the non-defective part is connected to the gate terminal to improve the chip yield, the gate terminal provided on the gate pad electrode. By forming the contact hole for connection with the defective portion with the insulating film instead of forming the defective portion, the gate terminal can be connected only to the defective portion.
Further, a short circuit between the gate electrode and the main electrode in the defective portion can be performed by closing a through hole formed in the insulating film between the main electrode and the main electrode with a metal film forming an emitter terminal. By thus forming the contact hole and the through hole at the same time and simultaneously closing them with the metal film, the process can be significantly shortened.

[Brief description of drawings]

1A and 1B are cross-sectional views of an IGBT chip manufactured by utilizing the present invention, in which FIG. 1A is a cross-sectional view of an essential part of a non-defective part, and FIG. 1B is a cross-sectional view of a defective part.

FIG. 2 is a process explanatory view of a first embodiment for forming a contact hole in a non-defective part and a through hole in a defective part.

FIG. 3 is a process explanatory diagram of a second embodiment using a negative photosensitive polyimide (insulating film).

FIG. 4 is an explanatory view of a method of exposing a photoresist at a place where a through hole and a contact hole are formed.

FIG. 5 is a sectional view of an example of a conventional IGBT unit cell.

FIG. 6 is a plan view of a conventional IGBT chip.

[Explanation of symbols]

1 n ^- layer 2 p-well 3 emitter region 4 MOS channel 5 gate oxide film 6 gate electrode 6a gate electrode connecting part 7 interlayer insulating film 8 emitter electrode 9 gate pad electrode 10 semiconductor chip 14 emitter lead wire 15 gate lead wire 17 guard ring 20 Insulating Film (Polyimide) 21 Contact Hole 22 Through Hole 23 Connection Hole 24 Etching Hole 24a Etching Hole 24b Etching Hole 25a Gate Terminal 25b Emitter Terminal 30 Photoresist 40 Semiconductor Wafer 41 XY Stage 42 Optical Nozzle 60 Photosensitive Part 61 Unexposed Part 62 Photosensitive part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9055-4M 658 Z

Claims (4)

[Claims] 1. A main electrode for flowing a main current on a main surface of a semiconductor substrate and a plurality of main current controlling gate electrodes insulated from the main electrode by a gate insulating film, and an extension of the gate electrode. In a method of manufacturing a power semiconductor device, in which a gate pad electrode for connecting to a gate electrode with a conductor is provided, a step of dividing the gate electrode into a plurality of parts and providing a gate pad electrode for each gate electrode; Measuring the withstand voltage between the gate electrode and the main electrode on the same main surface of the semiconductor substrate; covering the entire main surface with an insulating film; applying a negative resist; and exposing the negative resist by exposure. And a negative resist on the gate contact hole portion that connects the gate pad electrode and the gate terminal, which are connected to the gate electrode whose measured withstand voltage does not satisfy the specified value. In order to prevent the negative resist on the through-hole that short-circuits the gate electrode and the main electrode that satisfy the withstand voltage measurement value from being etched, the exposure step is performed again, and the negative resist and the insulating film are etched to determine the withstand voltage measurement value. A gate pad electrode and a gate terminal that are connected to a gate electrode whose measured withstand voltage satisfies a specified value by forming a through-hole that short-circuits the gate electrode and the main electrode that do not satisfy the value in the insulating film that sandwiches the main electrode and the main electrode. Forming a gate contact hole connecting the gate pad electrode in the insulating film on the gate pad electrode, and forming a connection hole for connecting to the main terminal in the insulating film on the main electrode; and closing the through hole and the connection hole. The method is characterized by including a step of forming a main terminal by coating a metal film on the main electrode and a step of forming a gate terminal by coating a metal film for closing the gate contact hole on the gate pad electrode. Method of manufacturing a power semiconductor device according to. 2. The method for manufacturing a power semiconductor device according to claim 1, wherein a negative photosensitive insulating film is used as the insulating film. 3. The method for manufacturing a power semiconductor element according to claim 1, wherein a polyimide resin is used for the insulating film. 4. The method for manufacturing a power semiconductor device according to claim 2, wherein a negative photosensitive polyimide is used for the negative photosensitive insulating film.