JPH08167589A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention relates to a semiconductor device that suppresses plasma damage generated in the manufacturing process of the semiconductor device and a manufacturing method thereof.
In particular, it is easy to control when etching via holes,
Provided are a semiconductor device capable of suppressing plasma damage without sacrificing a via hole diameter, and a method for manufacturing the same. [Structure] First wiring layer 1 formed on base substrate 10
2 and the interlayer film 14 formed on the first wiring layer 12,
The second wiring layer 16 formed on the interlayer film 14 and the first wiring layer 12 and the second wiring layer 16 formed on the interlayer film 14.
It has a via hole 18 for connecting to each other and an inner wall metal layer 24 formed on an upper portion of the inner wall of the via hole 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which suppresses plasma damage generated in a semiconductor device manufacturing process, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In the current manufacturing process of semiconductor devices, reactive ion etching (RIE) is used.
Various plasma processes such as tching) have been adopted. However, due to the miniaturization of elements accompanying the recent high integration of semiconductor devices, various problems caused by plasma irradiation have occurred.

For example, an etching process for opening a via hole is one of the processes for damaging plasma irradiation. A conventional typical via hole forming method will be described below. First, an interlayer insulating film is deposited on the wiring layer formed on the base substrate. Next, resist patterning is performed by a lithography process, and a via hole is opened in the interlayer insulating film by etching using this resist as a mask.

Here, it is desirable to use anisotropic etching when etching the inter-layer insulating film in order to miniaturize the contact holes as the device becomes highly integrated. However, for example, as shown in FIG. 10, in the case where the wiring layer 46 is connected to the gate electrode 38 of the MOS transistor formed on the semiconductor substrate 30 and a large number of via holes 58 are formed on the wiring layer 46. In the anisotropic etching process of opening the via hole 58 in the interlayer insulating film 48, plasma damage is likely to occur. That is, as shown in the drawing, when the wiring area is larger than the area of the gate electrode, if the charge charged by the reactive ions flows into the gate electrode 34, the dielectric breakdown of the gate oxide film 34 is caused. .

In particular, it has been known that the so-called electron shielding effect becomes remarkable when the aspect ratio of the via hole becomes large as seen in recent years, and the charge-up associated therewith is a problem. The electron shielding effect means that, in the ion sheath portion formed between the semiconductor substrate and the plasma, the ability of electrons to move toward the semiconductor substrate decreases, so that reactive ions can reach the bottom of the via portion. This is a phenomenon in which the bottom of the via portion is positively charged because electrons do not reach the bottom of the via portion.

Therefore, conventionally, the anisotropic etching is stopped before the opening formed by the anisotropic etching reaches the wiring layer 46, and then the etching is performed by using the neutral active species in which charge-up does not occur. By completely opening the via hole 58 by down-flow type isotropic etching, plasma damage such as charge-up is suppressed and the via hole is formed.

[0007]

However, in the above-described conventional method for manufacturing a semiconductor device, anisotropic etching must be stopped with the insulating film left in the via portion, so that calculation of the etching amount is troublesome. There was such a problem. In addition, it is difficult to accurately grasp the etching amount due to variations in the insulating film thickness due to the difference in the underlying step, so that there is a problem that it is difficult to control the etching.

Further, since anisotropic etching is performed after isotropic etching, even if fine patterning can be performed by lithography, the formed via hole has a large opening diameter, so it is not compatible with miniaturization. There was a problem such as leprosy. An object of the present invention is to provide a semiconductor device that can be easily controlled during etching and that can suppress plasma damage without sacrificing the via hole diameter, and a manufacturing method thereof.

[0009]

The above object is to form a first wiring layer formed on a base substrate, an interlayer film formed on the first wiring layer, and an interlayer film formed on the interlayer film. A second wiring layer, a via hole formed in the interlayer film and connecting the first wiring layer and the second wiring layer, and an inner wall metal layer formed on an upper portion of an inner wall of the via hole. It is achieved by a semiconductor device characterized by:

Further, in the above semiconductor device, it is preferable that the interlayer film is formed by laminating a plurality of insulating films having different etching characteristics. In addition, an interlayer insulating film deposition step of depositing an interlayer insulating film on a first wiring layer formed on a base substrate, a second wiring layer and a first wiring layer deposited on the interlayer insulating film, A resist patterning step of forming a resist patterned so as to form a via hole for connection, and a step of partially etching the interlayer insulating film using the resist as a mask
Etching step, a metal film depositing step of depositing a metal film on the etched interlayer insulating film, the metal film is etched by anisotropic etching, and the metal film is formed only on the inner wall of the via hole opened halfway. And a third etching step of completely etching the via hole by etching the interlayer insulating film in the via hole partially opened to the first wiring layer. And a method for manufacturing a semiconductor device.

In the method of manufacturing a semiconductor device described above, in the step of depositing an interlayer insulating film, a first interlayer insulating film contacting the first wiring layer and a second interlayer insulating film contacting the first interlayer insulating film are formed. An interlayer insulating film is deposited, in the first etching step, the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, and in the third etching step, the first interlayer insulating film is etched. It is desirable to etch the interlayer insulating film.

A first interlayer insulating film depositing step of depositing a first interlayer insulating film on a first wiring layer formed on a base substrate, and a first interlayer insulating film depositing step on the first interlayer insulating film. A first metal film deposition step of depositing a metal film; a second interlayer insulating film deposition step of depositing a second interlayer insulating film on the first metal film; and a second interlayer insulating film deposition step on the second interlayer insulating film. A resist patterning step of forming a resist patterned so as to form a via hole for connecting the second wiring layer to be deposited and the first wiring layer, and using the resist as a mask,
A first etching step of etching the second interlayer insulating film up to the first metal film; and etching the first metal film up to the first interlayer insulating film using the resist pattern as a mask A second etching step, a second metal film depositing step of depositing a second metal film, and an anisotropic etching to etch the second metal film, and only on the inner wall of the via hole opened halfway The second
Third etching step for leaving the metal film, and the fourth interlayer insulating film for etching the first interlayer insulating film in the via hole partially opened to the first wiring layer to completely open the via hole. It is also achieved by a method for manufacturing a semiconductor device, which includes an etching step.

[0013]

According to the present invention, by providing the inner wall metal layer in the via hole, it functions as a bypass for preventing the electron blocking effect and the like that occur in the via hole when the semiconductor substrate is exposed to plasma. When cleaning the contact portion using plasma, it is possible to prevent charge-up at the contact portion.

Further, when the interlayer film is formed by a laminated film formed by laminating a plurality of insulating films having different etching characteristics, the etching of the interlayer film can be easily stopped on the way, so that the inner wall metal layer can be easily formed. Can be formed.
Further, by providing the inner wall metal layer in the via hole, the inner wall metal layer functions as a bypass for preventing the electron blocking effect generated in the via hole, so that the via hole can be opened only by anisotropic etching. As a result, plasma damage such as charge-up can be prevented without sacrificing the via hole diameter.

If the interlayer insulating film is formed of two insulating films having different etching characteristics, the end point can be detected at the interface between these insulating films when the via hole is opened, so that the contact can be made without performing half etching. The insulating film can be left on the part. Further, this makes it possible to easily control etching. Also,
Since the endpoints can be detected at the interface between the metal film and the insulating film when the via hole is opened, the insulating film can be left in the contact portion without performing half etching. Further, this makes it possible to easily control etching.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. FIG.
2 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIG.
6A to 6D are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

The semiconductor device according to this embodiment is characterized in that the metal layer is provided on the upper portion of the inner wall of the via hole.
That is, the wiring layer 12 formed on the base substrate 10 and the wiring layer 1 formed on the wiring layer 12 with the interlayer insulating film 14 interposed therebetween.
In the upper part of the inner wall of the via hole 18 for connecting with 6,
An inner wall metal layer 24 is formed to prevent charge-up when opening the via hole 18.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described. First, the interlayer insulating film 14 is deposited on the wiring layer 12 formed on the base substrate 10. Next, the resist 22 is patterned into the shape of the via hole 18 to be opened by a lithography process (FIG. 2A).
Anisotropic etching is performed using the formed resist 22 as a mask to open the interlayer insulating film 14 halfway (FIG. 2).
(B)).

After removing the resist 22, the metal film 20 is deposited (FIG. 2C), and the metal film 20 is etched again by anisotropic etching. This makes the via hole 18
An inner wall metal layer 24 is formed on the inner wall of the. Further, etching is continued to remove the interlayer insulating film 14 remaining on the bottom of the via hole 18. In this way, the inner wall metal layer 2
The via hole 18 in which the No. 4 is formed is formed (FIG. 2).
(D)).

In this embodiment, the inner wall metal layer 24 is formed on the inner wall of the via hole 18, but this is for the following reason. That is, when the inner wall metal layer 24 is not provided on the inner wall of the via hole 18, the electron shielding effect becomes more remarkable as the aspect ratio of the via hole 18 becomes larger. Positive charge-up occurs. If the charges thus charged flow into the wiring layer 12 at once, there is a risk that the device characteristics may be adversely affected, such as destruction of the gate oxide film of the MOS transistor connected to the wiring layer. However, if the inner wall metal layer 24 is formed on the inner wall of the via hole 18, the electrons are not trapped on the inner wall of the via hole 18 and the inner wall metal layer 2 is formed.
This is because it is possible to prevent positive charge from being charged up in the contact portion by reaching the contact portion by using 4 as a bypass.

Therefore, in the process of etching the interlayer insulating film after etching the inner wall metal layer 24, the charge-up of the contact portion can be suppressed, so that the via hole 18 can be opened while suppressing the plasma damage. As described above, according to the present embodiment, by providing the inner wall metal layer in the via hole, the inner wall metal layer functions as a bypass for preventing the electron blocking effect generated in the via hole, so that the via hole is opened only by anisotropic etching. can do. As a result, plasma damage such as charge-up can be prevented without sacrificing the via hole diameter.

Further, in the above embodiment, the inner wall metal layer 24 formed on the inner wall of the via hole 18 was shown to be effective in etching the via hole 18, but it is also effective in the process after opening the via hole 18. There is. For example,
When forming a wiring layer connected to the wiring layer via the via hole 18, the contact portion may be cleaned with plasma. At this time as well, there is a possibility that an electron blocking effect may occur in the via hole 18, but due to the electron bypass effect described above, it is possible to prevent charge-up at the contact portion.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. 3 is a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIG. 4 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment. In the first embodiment described above, it was necessary to half-etch the interlayer insulating film in the step of etching the interlayer insulating film 14 before forming the inner wall metal layer 24. Therefore, it may be difficult to control the etching because it takes time to calculate the etching amount.

The semiconductor device according to the present embodiment is characterized in that the interlayer insulating film is formed of two layers of insulating films made of different materials. That is, the wiring layer 1 formed on the base substrate 10
On the upper part of the inner wall of the via hole 18 for connecting the wiring layer 16 formed via the interlayer insulating films 14a and 14b, the via hole 18 is formed on the upper surface of the via hole 18. An inner wall metal layer 24 is formed to prevent charge-up at the time of opening.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described. First, the interlayer insulating films 14a and 14b are continuously deposited on the wiring layer 12 formed on the base substrate 10. The interlayer insulating film 14a and the interlayer insulating film 14b are desirably as follows. That is, the interlayer insulating film 1
When etching 4b, a material is selected so that the interlayer insulating film 14a deposited in the lower layer functions as an etching stopper. For example, when a silicon oxide film is formed as the interlayer insulating film 14a, a silicon nitride film may be formed as the interlayer insulating film 14b.

Next, the resist 22 is patterned in the shape of the via hole 18 to be opened by a lithography process (FIG. 4A). Anisotropic etching is performed using the formed resist 22 as a mask to open the via hole 18 up to the interlayer insulating film 14b (FIG. 4B). After removing the resist 22, the metal film 20 is deposited (see FIG.
(C)) The metal film 20 is etched again by anisotropic etching. As a result, the inner wall metal layer 24 is formed on the inner wall of the via hole 18. Further, etching is continuously performed to leave the interlayer insulating film 14a remaining on the bottom of the via hole 18.
Is removed. Thus, the via hole 18 in which the inner wall metal layer 24 is formed is formed (FIG. 4D).

Since the inner wall metal layer 24 is formed on the inner wall of the via hole 18 when the interlayer insulating film 14a of the contact portion is etched, electrons are not trapped on the inner wall of the via hole 18 as in the above embodiment. , Inner wall metal layer 24
To reach the contact portion as a bypass to prevent positive charge from being charged up in the contact portion. Therefore, the via hole 18 can be opened while suppressing plasma damage.

As described above, according to the present embodiment, by providing the inner wall metal layer in the via hole, the inner wall metal layer functions as a bypass for preventing the electron blocking effect generated in the via hole, so that only anisotropic etching is required. Via holes can be opened. As a result, plasma damage such as charge-up can be suppressed without sacrificing the via hole diameter.

By forming the interlayer insulating film with two layers of insulating films having different etching characteristics, the end point can be detected at the interface between these insulating films when the via hole is opened, so that half-etching is not required. The insulating film can be left on the contact portion. Further, this makes it possible to easily control etching.

Further, in the above embodiment, it was shown that the inner wall metal layer 24 formed on the inner wall of the via hole 18 is effective in etching the via hole.
It is also effective for the process after opening the. For example, when forming a wiring layer connected to the wiring layer via the via hole 18, the contact portion may be cleaned using plasma. At this time as well, there is a possibility that an electron blocking effect may occur in the via hole, but the electron bypass effect described above can prevent charge-up at the contact portion.

Although the via hole 18 is formed without performing half-etching by forming the interlayer insulating film in a two-layer structure in the above embodiment, it is sufficient if the interlayer insulating film has a film functioning as an etching stopper. The interlayer insulating film is not limited to the two-layer structure and may have a three-layer structure or more. For example, the interlayer insulating film may be formed by a three-layer structure in which the silicon nitride film 14c is sandwiched between the silicon oxide films 14d and 14e and deposited (FIG. 5).

Next, a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 7 to 9 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. In the semiconductor device according to the present embodiment, as in the second embodiment, since the inner wall metal layer is left on the inner wall of the via hole without half-etching the interlayer insulating film,
The feature is that the interlayer insulating film is formed by a three-layer structure in which a metal film is sandwiched by insulating films.

That is, the gate electrode 38 is formed in the element region defined by the element isolation film 32 formed on the semiconductor substrate 30.
Substrate 40 on which a MOS transistor having a
A wiring layer 46 is formed on the interlayer insulating film 42. The interlayer insulating film 48 and the metal film 5 are formed on the wiring layer 40.
0 and the interlayer insulating film 52 are stacked to form the interlayer insulating film 5
An inner wall metal layer 60 for preventing charge-up at the time of opening the via hole 58 is formed on the inner wall upper part of the via hole 58 for connecting the wiring layer (not shown) formed on the wiring layer 2 and the wiring layer 46. There is.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described. The element isolation film 32 is formed on the semiconductor substrate 30 by a normal LOCOS process. A gate oxide film 34 of, eg, about 8 nm is grown on this semiconductor substrate 30. Then, a polysilicon film 36 to be a gate electrode
Is deposited, for example, to a film thickness of about 160 nm (FIG. 7A).
The polysilicon film 36 may be an amorphous silicon film.

After patterning the resist in the lithography process, the polysilicon film 36 is processed by dry etching using Cl and O ₂ gas, and the gate electrode 3 is formed.
8 is formed (FIG. 7B). On the semiconductor substrate 30 on which the gate electrode 38 is formed, for example, the film thickness is 50 to 100.
Insulating film 42 of about nm thickness is deposited by atmospheric pressure chemical vapor deposition (CVD: Ch
A contact hole 44 for connecting the gate electrode 38 to the upper wiring layer is opened (FIG. 7C).

After depositing an Al alloy film by a sputtering method, Al is formed by a lithography process and an etching process.
Wiring layer 46 for processing the alloy film and connecting to the gate electrode 38
Are formed (FIG. 7D). In this way, an oxide film having a film thickness of about 50 to 100 nm is grown on the underlying substrate 40 on which the wiring layer 46 is formed by the atmospheric pressure CVD method to form the interlayer insulating film 48. Then, an Al alloy film having a thickness of about 100 nm is deposited by a sputtering method, and a metal film 50 processed into a pattern similar to that of the wiring layer is formed by a lithography process and an etching process.

An oxide film having a film thickness of about 50 to 100 nm is again grown on the metal film 50 by the atmospheric pressure CVD method to form an interlayer insulating film 52 (FIG. 8A). Next, a resist 54 to which a pattern corresponding to a via hole to be opened is transferred is formed by a lithography process, and the interlayer insulation is performed by anisotropic etching using Ar / CF ₄ / CHF ₃ gas using the resist 54 as a mask. The film 52 is processed. Continuously, the metal film 50 is processed by anisotropic etching using, for example, BCl ₃ / Cl ₂ gas. As a result, the upper layer of the interlayer insulating film 48 is opened.

In this embodiment, the metal film 50 is provided between the interlayer insulating film 48 and the interlayer insulating film 52, so that the metal film 50 serves as an etching stopper when the interlayer insulating film 52 is etched. Since the inter-layer insulation film 48 can function as an etching stopper when etching is performed, the inter-layer insulation film 48 can be left on the wiring layer 46 in the contact portion without performing half etching (FIG. 8B). ).

After removing the resist 54, for example, a TiN film having a film thickness of about 10 to 20 nm is deposited by the reactive sputtering method to form a metal film 56 (FIG. 9).
(A)). When forming the inner wall metal layer in the via hole having a large aspect ratio, it is effective to use a material having excellent step coverage, easy sputtering, and excellent process matching. For example, Ti described above
It is desirable to use an N film.

After that, the metal film 56 and the interlayer insulating film 48 are etched by anisotropic etching using Ar / CF ₄ / CHF ₃ + SF ₆ gas. This makes the via hole 5
The inner wall metal layer 60 is left only on the inner wall of 8, and the via hole 58
The interlayer insulating film 48 remaining on the bottom of the is removed. Thus, the via hole 58 in which the inner wall metal layer 60 is formed on the upper portion of the inner wall is formed (FIG. 9B).

Since the inner wall metal layer 60 is formed on the inner wall of the via hole 58 when the insulating film 48 in the contact portion is etched, electrons are not trapped on the inner wall of the via hole 58 as in the above-described embodiment. The inner wall metal layer 60 is used as a bypass to reach the contact portion to prevent positive charge from being charged up in the contact portion. Therefore, the via hole 58 can be opened while suppressing plasma damage.

When the wiring layer is formed after the via hole is opened, the metal film 50 formed as a stopper for etching the interlayer film is connected to the wiring layer. However, the metal film 50 is the wiring layer 46. Since the pattern is processed in the same manner as above, there will be no inconvenience on the circuit. As described above, according to the present embodiment, by providing the inner wall metal layer in the via hole, the inner wall metal layer functions as a bypass for preventing the electron blocking effect generated in the via hole, so that the via hole is opened only by anisotropic etching. can do. As a result, plasma damage such as charge-up can be suppressed without sacrificing the via hole diameter.

Further, by using a three-layer structure in which a metal film is sandwiched between insulating films as the interlayer insulating film of the via portion, the end points can be detected at the interface between the metal film and the insulating film when the via hole is opened. Therefore, the insulating film can be left on the contact portion without performing half etching. Further, this makes it possible to easily control etching.

In the above embodiment, the inner wall metal layer 24 formed on the inner wall of the via hole 18 was shown to be effective in etching the via hole.
It is also effective for the process after opening the. For example, when forming a wiring layer connected to the wiring layer via the via hole 18, the contact portion may be cleaned using plasma. At this time as well, there is a possibility that an electron blocking effect may occur in the via hole, but the electron bypass effect described above can prevent charge-up at the contact portion.

[0045]

As described above, according to the present invention, by providing the inner wall metal layer in the via hole, it functions as a bypass for preventing the electron blocking effect and the like which occur in the via hole when the semiconductor substrate is exposed to plasma. Therefore, when etching the via hole or cleaning the contact portion using plasma, it is possible to prevent charge-up at the contact portion.

Further, when the interlayer film is formed by a laminated film formed by laminating a plurality of insulating films having different etching characteristics, the etching of the interlayer film can be easily stopped on the way, so that the inner wall metal layer can be easily formed. Can be formed.
Further, by providing the inner wall metal layer in the via hole, the inner wall metal layer functions as a bypass for preventing the electron blocking effect generated in the via hole, so that the via hole can be opened only by anisotropic etching. As a result, plasma damage such as charge-up can be prevented without sacrificing the via hole diameter.

Further, if the interlayer insulating film is formed of two layers of insulating films having different etching characteristics, the end point can be detected at the interface between these insulating films when the via hole is opened, so that the contact can be made without performing half etching. The insulating film can be left on the part. Further, this makes it possible to easily control etching. Also,
Since the endpoints can be detected at the interface between the metal film and the insulating film when the via hole is opened, the insulating film can be left in the contact portion without performing half etching. Further, this makes it possible to easily control etching.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the manufacturing method of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a schematic sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a process sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the structure of a semiconductor device according to a modification of the second embodiment.

FIG. 6 is a schematic sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a process sectional view (1) showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 8 is a process sectional view (2) showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a process sectional view (3) showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a diagram for explaining a problem in the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 10 ... Base substrate 12 ... Wiring layer 14 ... Interlayer insulating film 16 ... Wiring layer 18 ... Via hole 20 ... Inner wall metal layer 22 ... Resist 24 ... Metal film 30 ... Semiconductor substrate 32 ... Element isolation film 34 ... Gate oxide film 36 ... Polysilicon Film 38 ... Gate electrode 40 ... Base substrate 42 ... Interlayer insulating film 44 ... Contact hole 46 ... Wiring layer 48 ... Interlayer insulating film 50 ... Metal film 52 ... Interlayer insulating film 54 ... Resist 56 ... Metal film 58 ... Via hole 60 ... Inner wall metal layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H01L 21/3213

Claims (5)

[Claims] 1. A first wiring layer formed on a base substrate, an interlayer film formed on the first wiring layer, a second wiring layer formed on the interlayer film, A semiconductor device comprising: a via hole formed in an interlayer film and connecting the first wiring layer and the second wiring layer; and an inner wall metal layer formed on an upper portion of an inner wall of the via hole. 2. The semiconductor device according to claim 1, wherein the interlayer film is formed by laminating a plurality of insulating films having different etching characteristics. 3. An interlayer insulating film depositing step of depositing an interlayer insulating film on a first wiring layer formed on a base substrate, a second wiring layer deposited on the interlayer insulating film, and the first wiring layer. A resist patterning step of forming a resist patterned so as to form a via hole for connecting a wiring layer; a first etching step of partially etching the interlayer insulating film using the resist as a mask; A metal film deposition step of depositing a metal film on the interlayer insulating film, and a second etching step of etching the metal film by anisotropic etching to leave the metal film only on the inner wall of the via hole opened halfway. The interlayer insulating film in the via hole opened halfway is etched up to the first wiring layer to completely open the via hole. The method of manufacturing a semiconductor device characterized by having an etching process. 4. The method for manufacturing a semiconductor device according to claim 3, wherein in the step of depositing an interlayer insulating film, a first interlayer insulating film in contact with the first wiring layer and a first interlayer insulating film are in contact with each other. A second interlayer insulating film is deposited, in the first etching step, the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, and in the third etching step, A method of manufacturing a semiconductor device, which comprises etching the first interlayer insulating film. 5. A first interlayer insulating film depositing step of depositing a first interlayer insulating film on a first wiring layer formed on a base substrate, and a first interlayer insulating film depositing step on the first interlayer insulating film. First to deposit metal film
And a second interlayer insulating film is deposited on the first metal film.
And a resist forming a resist patterned so as to form a via hole for connecting the second wiring layer deposited on the second interlayer insulating film to the first wiring layer. A patterning step; a first etching step of etching the second interlayer insulating film up to the first metal film by using the resist as a mask; and a first metal film of the first pattern by using the resist pattern as a mask. A second etching step of etching up to the first interlayer insulating film, a second metal film depositing step of depositing a second metal film, and a step of etching the second metal film by anisotropic etching A third etching step of leaving the second metal film only on the inner wall of the via hole opened up to, and the first interlayer insulation in the via hole opened halfway A first etching until the wiring layer, a method of manufacturing a semiconductor device, characterized in that it comprises a fourth etching step of fully opening the via hole.