JPH08148828A - Thin film multilayer circuit board and method for manufacturing the same - Google Patents

Abstract

(57) [Summary] [Objective] Improved by a complete batch stacking method, which eliminates the drawbacks of the conventional successive stacking method and allows thin film multi-layer circuit boards with a large number of layers to be manufactured with a high yield and a short turnaround time. Provided are a multilayer circuit board and a method for manufacturing the same. [Structure] An organic resin sheet (inner layer circuit unit 12) having both fine thin film wiring and a conductor via having a bonding metal film formed on the surface thereof is aligned with each other, and a plurality of sheets are stacked to form a sheet. Form a temporary assembly for the stack. Then, the surface layer unit 11 is temporarily fixed to the upper portion of this sheet laminated body, and the base substrate connecting unit 13 is temporarily fixed to the lower portion thereof, and the laminated body 15 is formed.
To form. The temporary fixing laminated body 15 is mounted on the wiring substrate 14 such as a ceramic substrate to form the temporary fixing laminated body 17, and the temporary fixing laminated body 17 is collectively heated and pressed by hot pressing.
As a result, the electrical connection between the layers is performed by diffusion bonding between the via and the wiring by the bonding metal film, and at the same time, the organic resin layers are welded and fixed to each other to form an integrated structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board for mounting electronic parts and a method for manufacturing the same, and more particularly to a multilayer circuit board suitable for a thin film multilayer wiring circuit board using an organic resin insulating film as an interlayer insulating material and the same. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Conventionally, as the processing capability of an LSI device has become higher, the number of pins of the LSI has increased, and the rising and falling speeds of signals have become much faster, so that high-speed performance has been required for signal transmission circuits. In order to meet these demands, for example, in an ultra-high-speed system typified by a large computer or a supercomputer, the form of mounting a single chip package on a printed circuit board has been eliminated, and
Multi-chip mounting using a multi-layer co-sintered substrate made of metal conductor as the mounting substrate has become mainstream.

As means for further improving the performance of the mounted circuit board, an organic resin having a low dielectric constant is used as the interlayer insulating material, copper having a high electric conductivity is used as the wiring conductor, and a wiring pattern is formed to increase the wiring density. Methods such as high-precision photolithography have been studied.

Further, in order to increase the density of the wiring, it is necessary to make the circuit multi-layered, and in order to achieve both the increase of the wiring density and the reduction of the wiring resistance, it is necessary to increase the aspect ratio of the wiring cross section. Becomes In addition, impedance matching is strongly required due to the requirement for high-speed signal transmission characteristics, and therefore, even though it is a thin film, the interlayer insulating film is required to have a thickness of 20 μm or more.

By the way, a thin film multilayer circuit board using an organic resin as an interlayer insulating layer is conventionally generally formed by a sequential stacking process in which conductive wiring layers and insulating layers are alternately stacked. In this sequential stacking method, a conductor material is first formed into a film by a vacuum process such as sputtering or EB vapor deposition, and a conductor wiring is formed by a subsequent photoetching process. Then, the organic resin insulating film is applied by a method such as spin coating of varnish and dried and cured by heat treatment to form a final interlayer insulating film.

The connection between the upper and lower wiring layers is achieved by via processing of the organic insulating film by wet etching or dry etching and subsequent sputter film formation of the upper wiring metal material. The sequential lamination method repeats the above series of steps for the required number of layers, and requires an extremely long process time. In addition, a defect such as a disconnection or a short circuit occurs due to statistical establishment every time each layer is formed. Since the yield of the final multilayer circuit board is a multiplication of the process yield of each layer, it becomes more and more difficult to secure the yield as the wiring becomes finer.
In addition, when the number of wiring layers is large, the warp caused by the difference in the coefficient of thermal expansion between the organic resin and the underlying substrate adversely affects the pattern resolution in the photolithography process in the thin film process, so that the wiring layer There is a limit to the number. further,
If a resin with a high thermosetting temperature such as polyimide is used for the interlayer insulating film, the lower insulating layer will be repeatedly subjected to high-temperature treatment for a long time, causing problems such as deterioration of the mechanical properties of the insulating film. It's easy to do.

Therefore, proposals have been made to improve the drawbacks of the thin-film multi-layer circuit board manufacturing process by the sequential stacking method as described above. For example, in Japanese Unexamined Patent Publication (Kokai) No. 5-206643, a laminated structure of a plurality of thin film wiring layers is made into one block, which is formed on a temporary substrate, and each block is connected by soldering with solder. . But,
The thin film wiring in each block is still formed by the conventional sequential stacking method, and it is not easy to secure a necessary interlayer insulating film thickness while maintaining a sufficient wiring density.

Further, Japanese Patent Laid-Open No. 4-162695 discloses a sheet laminating system using a laminated body of a sheet-shaped photosensitive polyimide and a metal foil. That is, a via is formed by photolithography at a desired position of the sheet-shaped photosensitive polyimide, the via is filled with a conductor by electroplating, and then the metal foil is processed by photoetching to form a wiring. A plurality of photosensitive polyimide sheets with wiring patterns made in this way are laminated and thermocompression bonded under heating at least 350 ° C to form a multilayer wiring film in advance, and this is mounted on a ceramic substrate to form a multilayer wiring film. It is intended to manufacture a wiring board. In this case, there is a concern that miniaturization of the via size is limited due to the resolution limit of the photosensitive polyimide. Further, since it includes the step of mounting the multilayer wiring film on the ceramic substrate, it is difficult to say that it is a complete batch lamination method. Furthermore, since the heat treatment temperature of the photosensitive polyimide sheet laminate with a wiring pattern is high, there is a problem of residual thermal stress. Occurs.

[0009]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems in manufacturing a conventional thin film multilayer circuit board and to provide an improved method for manufacturing a thin film multilayer circuit board by a complete batch lamination method. To provide. That is,
The object of the present invention is to eliminate the drawbacks of the sequential stacking method and realize a method for manufacturing a multilayer circuit board capable of manufacturing a thin film multilayer circuit board having a large number of layers with a high yield and a short turnaround time.

More specifically, the present invention solves the following problems in the conventional manufacturing process of a thin film multilayer circuit board. That is, 1) Low yield. (The problem that the yield of the final product is determined by multiplying the yield of each layer forming process) 2) Long process time. (Long turnaround time) 3) Due to residual thermal stress, the number of laminated layers is limited. 4) Deterioration of material properties due to repeated high temperature heat treatment processes.
(Reliability degradation)

[0011]

As means for solving the above problems, each layer of a thin film multilayer circuit is formed as an independent unit (hereinafter, referred to as "thin film circuit unit"), and each thin film circuit unit is manufactured. Only non-defective non-defective products are inspected, the non-defective thin-film circuit units are aligned with each other, the connection points between the layers are surely opposed to each other, and external energy such as pressure and heat is applied from above and below to each layer. It is effective to use the simultaneous batch lamination manufacturing process that simultaneously secures the electrical connection in the vertical direction between the wiring patterns and achieves the adhesion between the organic resins of the respective layers.

Therefore, the technical elements for establishing this collective lamination method are summarized below. That is, 1) A thin film circuit unit that constitutes a thin film multilayer circuit has a sheet made of an organic resin insulating film as a base material, and has a necessary wiring circuit pattern on at least one surface (lower surface) thereof,
Further, metal conductor vias that penetrate the organic resin sheet and reach the upper surface of the sheet are formed at desired positions of the wiring circuit pattern. 2) In order to electrically connect the wiring circuit patterns of the thin film circuit unit to each other at desired positions in the vertical direction, on the surface of the metal conductor via, the glass transition temperature (Tg) or more of the organic resin,
A bonding metal film capable of forming diffusion bonding with the constituent material of the wiring circuit by heat treatment at 250 ° C. or less.

3) The organic resin surface of the thin film circuit unit is
To be able to achieve sufficient mutual adhesive strength under the laminated thermocompression bonding conditions. 4) The sheet of the thin film circuit unit has an intermediate area (3 ppm / ° C or higher, 17 ppm or more) between the Si chip and the wiring conductor (copper).
/ C) or less), good dimensional stability in the lateral direction, and little pattern displacement during heat treatment. 5) As a starting material for the manufacturing process of the thin film circuit unit, an organic resin sheet having metal foils bonded to the front and back surfaces is used.
In particular, an organic resin sheet having different thicknesses of the metal foils on the front and back surfaces or different materials of the metal foils on the front and back surfaces is used.

6) A method for forming via holes prior to the formation of metal conductor vias is a method capable of forming holes with high precision and high aspect ratio regardless of the film thickness of the organic resin sheet. That is, the via hole processing is performed by dry etching or laser processing. A high-performance thin-film multilayer circuit board is realized with a high yield and a short turnaround time by a manufacturing process obtained by integrating the above technical elements.

The structure of the thin film circuit unit constituting the thin film multilayer circuit and the multilayer circuit board of the present invention having the main part as a main part will be described in more detail below. The thin film circuit unit includes an inner layer circuit unit and a surface layer unit. And a base substrate connecting unit.
The inner layer circuit unit is laminated by a required number of layers to form a main part of the thin film multilayer circuit, and the surface layer unit is laminated on the top of the inner layer circuit unit having a plurality of layers. A pad for mounting and mounting an electronic component such as an LSI is formed on the. In addition, the base substrate connecting unit mounts a laminated body of inner layer circuit units on a thick film multilayer wiring substrate such as a ceramic substrate or a glass substrate,
It becomes the connection medium when connecting, and the upper pad that electrically connects to the back surface of the inner layer circuit unit on the surface,
The lower surface has a lower bonding metal film connected to the matching pad on the wiring board.

In the thin film multilayer circuit board of the present invention, these units are sequentially laminated on a known thick film wiring board such as a ceramic board or a glass board in the order of a base board connecting unit, an inner layer circuit unit and a surface layer unit. Then, by applying external energy to this laminate, vertical electrical connection between the wiring patterns of each layer can be secured all at once, and adhesion between the organic resins forming the interlayer insulating film of each unit can be achieved. It is configured as an integrated structure.

As a sheet constituting each unit, an organic resin sheet having a front surface and a back surface laminated with a metal foil such as copper is used as a starting material. A typical example is a double-sided copper-clad laminated film, and examples of commercially available products include Teijin Technora copper-clad laminated film (trade name of Teijin Ltd.),
Examples include Toray copper-clad polyimide film (trade name of Toray Industries, Inc.). Further, a double-sided copper-clad laminated film in which a polyimide adhesive film, for example, a product name "AS-2210" manufactured by Hitachi Chemical Co., Ltd. is laminated on both sides of a low thermal expansion polyimide film and further copper foil is adhered on both sides can be used. In addition, this type of organic resin sheet,
A sheet having a glass transition temperature (Tg) of 250 ° C. or lower and composed only of a resin component is preferable, and a sheet including an inorganic glass cloth base material used as a base material of a printed circuit board is processed by via processing. It is sometimes better to avoid it, as residue remains in the via holes.

Further, the tip of a via provided in the inner layer circuit unit and the base substrate connecting unit by copper plating or the like is slightly projected from the surface of the organic resin sheet, and a bonding metal film is formed on the surface by plating. In the case of the base substrate connecting unit, this bonding metal film is also formed as an upper bonding metal film on the upper connection pad. As the bonding metal film for electrically connecting the units, a metal that can be diffusion bonded at a relatively low temperature of not less than the glass transition temperature of the resin and not more than 250 ° C. is desirable. Low melting point alloys such as Sn-Ag alloys and Sn-Pb alloys are suitable. Note that Au—Sn alloys and the like have a high eutectic temperature of 280 ° C., which is not preferable. Also,
The thickness of the bonding metal film is not particularly limited,
Practically, about 1 to 10 μm is preferable.

On the pad provided on the surface of the surface layer unit, a metal film is formed as a surface metallization by electrolytic or electroless plating. This metal film is not a bonding metal film for connecting the units. Since it has a different role and is used for connection when mounting and mounting electronic components, it must act as a barrier against solder materials and must also satisfy the characteristics such as repair resistance and wire bondability of components such as LSI. For example, electroless Ni-B
It is desirable to form the plating film or the electroless Ni-P plating film to the required film thickness.

In order to obtain the multilayer circuit board of the present invention, the base board connecting unit, the inner layer circuit unit, and the surface layer unit are sequentially laminated on the board while aligning the wiring patterns, and then thermocompression bonded to form an integrated structure. However, this thermocompression bonding is performed using a hot press machine. The hot pressing conditions include, for example, a vacuum degree of 10 to 60 torr, a hydrostatic pressure of 15 to 30 kg / cm ² , a glass transition temperature of the resin sheet constituting the base material of the unit or higher, and a maximum attainable temperature of 250.
It is desirable to carry out press molding at a temperature of preferably 0 to 250 ° C.

[0021]

The bonding metal film formed on the vias or pads for electrically connecting the top and bottom of each unit is the temperature at which the laminated body of each unit is hot pressed, for example,
Good diffusion bonding is achieved at a preferable temperature of 180 to 250 ° C. In addition, the organic insulating films that form the base of each unit in this temperature range also have sufficient bonding strength as a multilayer circuit board by integrating the interfaces by fusing and adhering to each other, and It ensures reliability.

According to the invention described above, the manufacturing process of the thin film multilayer circuit board, which has been limited in the range of application as a mass production technology because of the remarkably long process and the low yield, has been greatly rationalized, and the use of the thin film multilayer circuit can be improved. To expand.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. <Embodiment 1> FIG. 1 is a sectional view showing a manufacturing process of an inner layer circuit unit 12 of a thin film circuit unit which constitutes a main part of a thin film multilayer circuit board.

As shown in FIG. 1 (a), as a starting material, a double-sided copper-clad laminated film (a glass foil having a glass transition temperature of 194 ° C., an organic resin insulating film 112, which is a base material of the unit, was laminated with copper foils 111 and 113. Prepare a sheet). As the double-sided copper-clad laminated film, one in which the film thickness of one copper foil is equal to or less than half the film thickness of the other copper foil (hereinafter, referred to as "asymmetric copper-clad resin film") is used. In this example, the upper copper foil 111 has a film thickness of 9 μm and the lower copper foil 113 has a film thickness of 18 μm. However, practically, the upper copper foil 111 has a film thickness of 3 to 18 μm and the lower copper foil 113 has a film thickness of 3 to 18 μm. It is desirable to be in the range of 5 to 35 μm. If the upper copper foil 111 is thinner than this film thickness range, the resistance as a mask for dry etching or laser processing in a subsequent via hole processing step may be insufficient, and if it is thick, the photo as a via processing mask may be insufficient. The etching processing accuracy becomes insufficient.
Further, if the lower copper foil 113 is thinner than this film thickness range, the resistance value when processed into wiring may be too high, and if it is thick, fine wiring processing becomes difficult.

As shown in FIG. 1B, the thicker copper foil (lower copper foil 113) surface of this asymmetric copper-clad resin film is covered with a protective film 114 with an adhesive.

Thereafter, as shown in FIG. 1C, a mask pattern 115 for processing a via hole is formed in the thinner copper foil (upper copper foil 111). That is, the upper copper foil 111
The portions where the vias are formed are removed by the photoetching process. Although illustration is omitted, specifically, a photoresist is applied on the upper copper foil 111, exposed through a predetermined mask for forming vias, and developed to form a resist pattern. Then, using the resist pattern as a mask, the upper copper foil 111 is selectively etched to remove the resist pattern. The etching solution for the copper foil is not particularly limited, and ammonium persulfate-based, ferric chloride-based,
Although a mixed acid of hydrochloric acid, phosphoric acid, nitric acid, and acetic acid can be used, ammonium persulfate system was used here.

As shown in FIG. 1D, the organic resin layer 1 is formed by using the pattern of the upper copper foil 111 formed here as a mask.
Via drilling is performed on 12. As a processing method, dry etching or laser processing, which has good vertical processing properties, is suitable. In this example, laser processing using an excimer laser was used. In the case of dry etching, reactive ion etching using oxygen or a mixed gas of oxygen and CF ₄ can be used. Further, as the laser processing, an ultraviolet laser, particularly an excimer laser or laser ablation using TEA-CO ₂ is effective. Thus, the organic resin 112 in the via portion 116 is removed by dry etching or laser processing,
The surface of the lower copper foil 113 is exposed at the bottom of the via. In addition, T
EA means a method of extracting a laser beam in a direction perpendicular to the discharge direction of the laser discharge tube.

As shown in FIG. 1E, the via processing mask pattern 115 is removed by wet etching.
At this time, the surface of the lower copper foil 113 at the bottom of the via is also etched to some extent, but due to the film thickness difference between the upper copper foil 111 and the lower copper foil 113, it does not penetrate to the bottom. That is, in consideration of the removal of the via processing mask pattern 115, the thickness of the lower copper foil 113 is determined to be thicker than that of the upper copper foil.

As shown in FIG. 1F, the lower copper foil 113
Is used as a power supply electrode (cathode), and copper plating 117 is applied to the via hole portion 116. At this time, the tip of the copper-plated via is made to slightly project from the surface of the organic resin 112. The amount of protrusion of the copper-plated via 117 from the organic resin surface is not particularly limited, but is preferably in the range of 1 to 10 μm. In this example, the protrusion amount was 1 μm. The joining metal thin film 118 is continuously plated on the tip of the copper plating via 117.
As the bonding metal, the glass transition temperature of the organic resin or higher, 2
It is important to select a metal that allows sufficient diffusion bonding at 50 ° C. or lower, preferably 180 to 250 ° C., for example, Sn, Zn simple substance, or Sn—Zn alloy, Sn—.
Alloys such as Ag alloys and Sn-Pb alloys are suitable. Although the film thickness of the bonding metal thin film is not particularly limited,
The range of 10 μm is desirable. In this example, Sn is 1 μm
Plated.

The surface of the connection metal thin film 118 may be coated with displacement gold plating or electroless gold plating to prevent oxidation.

As shown in FIG. 1 (g), the surface of the via 117 on which the bonding metal thin film 118 is formed is a protective film,
Alternatively, the back surface protective film 114 is removed by coating with a coating type protective resist 119. Here, protective resist 1
The same material as the protective film 114 with an adhesive was used as 19.

Lastly, as shown in FIG. 1H, the lower copper foil 113 is processed by photoetching to form a desired wiring pattern 120 on the back surface of the sheet. That is,
Although not shown, specifically, a photoresist is applied on the lower copper foil 113, exposed through a mask for forming a predetermined wiring pattern, and developed to form a resist pattern. Then, the lower copper foil 113 is selectively etched by using the resist pattern as a mask to form the wiring pattern 1
20 is formed and the resist pattern is removed.

As described above, it was possible to form an organic resin sheet having the bonding metal film 118 on the conductor wiring 120 and the conductor via 117, that is, a thin film circuit unit. The thin film circuit unit described here constitutes the inner layer circuit unit 12 in the whole thin film multilayer circuit.

Example 2 This example shows an inner layer circuit unit 12 similar to that of Example 1, except that the metal foils 111 and 1 formed on both sides of the organic resin insulating film 112 are the same.
13 is composed of two different kinds of metal foils, and an organic resin sheet in which an aluminum foil having a film thickness of 3 to 18 μm is bonded to the upper surface of an organic resin film 112 and a copper foil having a film thickness of 5 to 35 μm is bonded to the lower surface thereof is used as a starting material. Use as material. In this example, an aluminum foil having a thickness of 5 μm and a copper foil having a thickness of 18 μm were used.

Most of the manufacturing process conforms to the contents of Example 1 shown in FIG. 1, but instead of using the copper foil pattern in Example 1 for the via processing mask 115 of FIG. This example is different in that an aluminum foil pattern is used.
That is, this aluminum foil takes on the role of the upper copper foil 111 of the first embodiment.

In the following, referring to the process chart of FIG. 1, first, the aluminum foil 111 is processed into a via processing mask pattern 115 by a photoetching process of exposing and developing through a predetermined mask. Then, the aluminum foil mask 115 is applied to the organic resin 1 by the same method as in Example 1.
It is used for processing 12 via holes 116 [corresponding to step (d) of FIG. 1]. After that, the aluminum foil mask 115 is diluted with dilute hydrochloric acid,
For example, it can be easily removed with 10 to 15% hydrochloric acid [Fig. 1
(Corresponds to step (e)]. At this time, since the surface of the lower copper foil 113 exposed at the bottom of the via 116 is hardly etched, the process management is advantageous.

That is, this embodiment has two characteristic points, one of which is that the process management is easy,
When dilute hydrochloric acid is used, the etching selectivity of the copper foil to the aluminum foil is large, and therefore the copper foil is not etched even if the aluminum foil mask is removed. Another point is that the lower copper foil 113 can be thinned because the copper foil is not etched. When forming the wiring pattern 120 in the step of FIG. 1H, a high-density fine wiring pattern can be easily formed. It has the effect that it can be formed.

<Embodiment 3> This embodiment shows an example of the structure and forming method of the surface layer unit of the thin film multilayer circuit board, and will be described below with reference to the sectional process drawing of FIG. The surface layer unit 11 is laminated on the outermost surface of the mounting circuit board, and its configuration is shown in FIG.
As shown in (f), at least a bonding pad for connecting an electronic component (a surface layer copper pad 122 covered with a surface metallization layer 123) is formed on the surface.
I plays a role of directly connecting and mounting other electronic components. Further, on the back surface, an electrode of the uppermost layer in which a plurality of inner layer circuit units 12 are stacked (projecting on the front surface and forming the bonding metal film 118)
A back surface connection pad 124 for connecting to the via 117) covered with is provided.

As the starting material for forming the surface layer unit 11, basically the same material as that of the first embodiment can be used, and the steps are also the same as the first embodiment.

FIG. 2A shows the first embodiment shown in FIG.
The state after the step (c), that is, the via processing mask pattern 11 is formed on the upper copper foil 111 by photoetching.
5 shows the state immediately after 5 is formed.

FIG. 2B shows a via processing mask pattern 1.
By 15 the via hole 1 in the same process as FIG.
16 shows a state in which 16 is formed.

FIG. 2C shows the following state.
That is, electrolytic copper plating is performed using the lower copper foil 113 as a cathode and the via holes 116 are filled with electrolytic copper while leaving the upper copper foil (111) that has become the via processing mask pattern 115. At this time, when the surface of the copper plating reaches the opening of the upper copper foil, the copper plating via 117 inevitably causes the upper copper foil (1
11), the copper plating film 121 grows on the entire upper surface of the sheet as a common electrodeposition surface. The plating is stopped when the upper electrolytic copper plating film 121 reaches a desired thickness. In this example, the upper electrolytic copper plating film 121 was formed to a thickness of 10 μm.

FIG. 2D shows a via processing mask pattern 1 obtained by processing the electrolytic copper plating film 121 and the upper copper foil 111.
2 shows a state in which the surface-side copper layer of 15 is processed by photoetching in the same step as FIG. 2A to form the surface-layer copper pad 122.

FIG. 2E shows the following state.
That is, the surface metallization 1 is applied to the surface of the copper pad 122.
23, a nickel plating film, for example, electroless Ni-B
A plating film or an electroless Ni-P plating film is formed to a required film thickness. Here, the electroless Ni-B plating film is
μm was formed. Then, the surface of this Ni-plated film is subjected to displacement gold plating, or displacement gold plating and electroless gold plating in order to secure the wettability of the solder material.

FIG. 2F shows the final step,
Surface metallization 12 similar to the step of FIG.
3 is covered with a protective film or resist 119 on the side having the surface layer copper pad 122, the back surface protective film 114 is peeled off (the process steps up to this point are omitted), and then the lower copper foil 113 is connected as shown. It is processed into the shape of the pad 124. The processing method is by ordinary photo-etching as in the step of forming the front surface copper layer pad 122 of FIG. The surface of the back surface connection pad 124 may be subjected to displacement gold plating or electroless gold plating in order to prevent surface oxidation.

Through the above steps, the surface layer unit 11 can be formed. Since the surface metallization 123 of the surface layer unit 11 is used for connecting terminals of electronic parts such as LSI, it plays a role of a barrier against the solder material, and also the repair resistance of the LSI (LS connected once to the wiring board).
I is removed and replaced, and then re-connected), and wire bonding properties and other characteristics are satisfied.

<Embodiment 4> As a thin film circuit unit,
As described above, there is a base substrate connecting unit in addition to the inner layer circuit unit and the surface layer unit. In this embodiment, the structure of this base substrate connecting unit and an example of its formation will be described. The base substrate connecting unit is a laminated body of a plurality of inner layer circuit units and a thin film multi-layer circuit section consisting of a surface layer unit laminated on the uppermost part thereof, when the ceramic multi-layer substrate or the rigid multi-layer printed wiring board is formed. It plays a role of connecting the base substrate and the thin film circuit section.

The structure of the base substrate connecting unit 13 will be described below with reference to the sectional view of FIG. As shown, the structure is similar to that of the inner layer circuit unit 12 shown in FIG.
It is similar to the configuration in which the front surface and the back surface are reversed. That is, the copper foil 113 is patterned on the surface by photoetching to form the upper connection pad 122a, and further the upper bonding metal film 118a is provided thereon. A copper-plated via 117 filled with copper plating is formed in the via hole 116, and a tip portion thereof slightly projects above the surface of the organic resin insulating film 112, and a lower bonding metal film 118b is formed on the surface. . As described above, it has a structure similar to that of the inner layer circuit unit of the first embodiment, but is characterized in that the joining metal thin films 118 are formed on both front and back surfaces of the connecting conductor portion.

The manufacturing process of the base substrate connecting unit 13 is basically the same as the manufacturing process of the inner layer circuit unit shown in FIG. 1 of the first embodiment. However, the upper and lower surfaces of the sheet in each process have opposite configurations. Then, in the step of FIG. 1H, instead of forming the wiring pattern 120 in the first embodiment, an upper connection pad pattern 122a is formed in the present embodiment, and a bonding metal is formed on the surface thereof as in the step of FIG. 1F. The lower bonding metal 118b is coated as a film.

<Embodiment 5> In this embodiment, the thin film circuit units prepared in the above Embodiments 1 to 4, that is, the inner layer circuit unit, the surface layer unit and the base substrate connecting unit are laminated on a substrate, FIG. 3 shows an example of realizing a thin film multilayer circuit board by integrally bonding the laminated bodies of 1) by thermocompression bonding. Hereinafter, an example of the structure of the thin film multilayer circuit board will be described together with the description of the manufacturing process with reference to FIGS.

FIG. 4 shows a manufacturing process diagram of a thin film multilayer circuit board. First, as shown in FIG. 1A, a matching pad 128 made of a copper film is formed on the surface of a ceramic 129 as the wiring board 14, and one end is internally provided with this pad 1.
A ceramic multi-layer wiring board is prepared in which thick film through-hole conductors 117a, each of which is connected to 28 and the other end of which is projected to the back surface, are provided. As the ceramic substrate 14, a mullite-W co-sintered multilayer wiring board or a glass ceramic-Cu co-sintered multilayer wiring board is usually used, but here, the latter glass ceramic-Cu co-sintered multilayer wiring board is used. Was used.

As shown in FIG. 7B, next, the laminated body 15 of the thin film multilayer circuit portion is formed as follows. Example 4
The base substrate connection unit 13 formed in step 1 is placed on a jig 16 made of a Teflon surface plate with a smooth surface with the upper connection pad 122a side facing upward, and an inspection is performed while performing optical pattern alignment on the jig 16. After passing through the process, the inner layer circuit unit 12 formed in the first or second embodiment is laminated, and the upper and lower layers are temporarily fixed with the instant adhesive at a minimum of four places on the edge of the sheet. Subsequently, the required number of inner layer circuit units 12 are sequentially installed from the bottom by repeating the steps of positioning, stacking and temporarily fixing. In this example, 20 inner layer circuit units 12 are stacked. Finally, the surface layer unit 11 formed in Example 3 is installed by the same method, and the temporary fixing laminated body 15 of the thin film multilayer circuit section is completed.

As shown in FIG. 6C, subsequently, the temporary fixing laminated body 15 of the thin film multilayer circuit portion is installed on the ceramic multilayer wiring substrate 14 with the matching pad while performing optical pattern alignment. Then, the temporarily fixed laminated body 17 is obtained.

As shown in FIG. 3D, the thin film multilayer circuit section-ceramic substrate temporary fixing laminate 17 is provided with a bottom mirror surface plate 21 which serves as a lower punch (heating plate) of a commercially available hot press device 20 with a vacuum suction mechanism. Placed on top of. At this time, a Teflon sheet 18 for preventing heat fusion was inserted between the upper and lower punches (heating plates) 21 and 22 and the laminated body 17. Using this hot press device 20, a vacuum degree of 10 to 60 torr,
Hydrostatic pressure 15 to 30 kg / cm ² , maximum temperature reached 250 ° C
Press molding was carried out under the conditions described above to obtain a ceramic multilayer circuit-thin film multilayer circuit composite substrate.

FIG. 5 shows the relationship between the hydrostatic pressure and the heating schedule during this hot pressing. In the figure, the left vertical axis represents temperature (° C.), the right vertical axis represents hydrostatic pressure (kg), and the horizontal axis represents time (minutes). The temperature condition during this pressing has a lower limit of at least the glass transition temperature (T
g) or higher (generally 180 ° C. or higher) and the upper limit is 250 ° C. or lower. Since the glass transition temperature (Tg) of the organic resin insulating film 112 used here is 194 ° C., the maximum attainable temperature of 250 ° C. sufficiently satisfies the temperature condition of this press. Therefore, the maximum temperature to be reached when using this resin is not limited to 250 ° C, and a desired temperature can be selected within the range of 194 to 250 ° C.

FIG. 6 is a sectional view showing the principal part of the ceramic multilayer circuit-thin film multilayer circuit composite substrate thus obtained. First, the electrical connection relationship of the composite substrate will be described. The connection between the base substrate 14 made of a ceramic substrate and the base substrate connecting unit 13 constitutes the matching pad 128 on the base substrate 14 and a part of the laminated body 17. With the lower bonding metal film 118b covering the copper plating via 117 of the base substrate connecting unit 13. The connection between the base substrate connection unit 13 and the inner layer circuit unit 12 is performed by connecting the upper bonding metal film 118a covering the upper connection pad 122a formed on the surface of the base substrate connection unit 13 and the wiring formed on the back surface of the inner layer circuit unit 12. This is performed with the pattern 120.

The connection of the inner layer circuit units 12 of 20 laminated layers is connected to the other wiring pattern 120 via the bonding metal film 118 covered with the copper plating via 117 on one side. The uppermost inner layer circuit unit 12 and the surface layer unit 11 are connected by the inner layer circuit unit 12
Of the bonding metal film 118 covered with the copper-plated via 117 and the back surface connection pad 124 of the front surface layer unit 11. A surface layer copper pad 122 covered with a surface metallization 123 is formed on the surface of the surface layer unit 11, and when mounting and mounting an electronic component, terminals of the electronic component are connected via the surface metallization 123. It

In addition, the connection between the respective units constituting the laminated body 15 of the thin film multi-layer circuit section is such that the interface of the organic resin insulating film 112 is heated to its glass transition temperature or higher by heating and pressure contact with a hot press. It is carried out by melting and welding each other. The organic resin insulating film 112 of the base substrate connecting unit 13 is also connected to the base substrate 14 by welding.

In this way, the units forming the thin film multilayer circuit section 15 and the connection between the base substrate connecting unit and the base substrate 14 are sufficiently connected by the electrical connection by the bonding metal film and the connection by the resin. A ceramic multilayer circuit-thin film multilayer circuit composite substrate having various connection strengths is realized.
In the figure, reference numeral 125 indicates the X-direction wiring of the inner layer circuit unit 12, and 126 indicates the Y-direction wiring.

FIG. 7 is an enlarged cross-sectional view of an essential part showing the connection relationship between the inner layer circuit units 12 of the ceramic multilayer circuit-thin film multilayer circuit composite substrate in more detail.
Indicates the state of the temporary fixing laminate 15 before the hot press treatment,
FIG. 3B shows the connection state after the hot pressing process. As is clear from FIG. 6B, the bonding metal film 118 on the copper-plated via 117 before connection diffuses into the wiring pattern 120 and the copper-plated via 117 to form an alloy to form the diffusion bonding forming portion 127. I am configuring. Also,
It can be seen that the organic resin insulating films 112 adjacent to each other have their interfaces melted and welded to each other.

Although this embodiment is an example in which the ceramic multilayer circuit board is used as the base substrate 14, the base substrate is not limited to this, and other rigid printed wiring boards, rigid multilayer printed wiring boards, etc. Can also be used. In addition, as a matter of course, only the laminated body 15 of the thin-film multilayer circuit portion may be similarly thermocompression-bonded by the hot press machine, and this alone may be used as the mounting substrate.

As described above, according to the present invention, each wiring layer constituting the thin film multilayer circuit board is individually manufactured as an independent unit, and each unit is preliminarily inspected to obtain only a defect-free product. It is obtained by selecting, stacking them by aligning them, and simultaneously subjecting them to hot press molding, and it is possible to achieve both a high yield and a short construction period.
Further, since the heat treatment time during all steps is significantly reduced and the process temperature is relatively lowered, there are few problems of thermal deterioration of materials and residual stress, and therefore there is no restriction on the number of wiring layers.

[0063]

As described above in detail, according to the present invention, the intended purpose can be achieved. That is, the drawback of the conventional thin film multilayer circuit board manufacturing process, low yield, long process time, the problem that the residual stress of the thin film limits the number of stacked layers,
Eliminating problems such as physical property deterioration of organic resin due to repeated high temperature heat treatment, we provide thin film multilayer circuit board manufacturing technology with high yield and short delivery time, and highly reliable thin film multilayer circuit board. Contributes to the performance improvement of advanced electronic systems.

[Brief description of drawings]

FIG. 1 is a sectional process view showing a process of forming an inner layer circuit unit according to an embodiment of the present invention.

FIG. 2 is a sectional process diagram showing a process of forming a surface layer unit.

FIG. 3 is a sectional process diagram showing a process of forming a base substrate connecting unit in the same manner.

FIG. 4 is a manufacturing process drawing of the same ceramic multilayer circuit-thin film multilayer circuit composite substrate.

FIG. 5 is a time schedule also showing the temperature-pressure profile of the hot press.

FIG. 6 is a sectional view of an essential part of the same ceramic multilayer circuit-thin film multilayer circuit composite substrate.

FIG. 7 is an enlarged cross-sectional view showing a state of diffusion bonding between the thin film wiring and the via, similarly.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Surface layer unit, 12 ... Inner layer circuit unit, 13 ... Base substrate connection unit, 14 ... Ceramic substrate (base substrate), 15 ... Temporary fixing laminated body of thin film multilayer circuit part, 16 ... Teflon surface plate, 17 ... Base substrate Temporary fixing laminated body mounted on top, 111 ... Upper metal foil, 112 ... Organic resin insulation film, 113 ... Lower copper foil, 114 ... Protective film, 115 ... Via processing mask pattern, 116 ... Via hole, 117 ... Electricity Copper-plated via, 117a ... Thick film sulfor conductor, 118 ... Bonding metal film, 118a ... Upper bonding metal film, 118b ... Lower bonding metal film, 119 ... Protective resist or film, 120 ... Wiring pattern, 121 ... Surface layer electrolytic copper plating film, 122 ... Surface layer copper pad, 123 ... Surface metallization, 124 ... Back surface connection pad, 122a ... Top connection pad De, 125 ... X-direction wiring, 126 ... Y-direction wiring, 127 ... spreading bonding portion, 128 ... matching pad.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ryohei Sato Inventor Ryohei Sato, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Institute of Industrial Science (72) Tomonbun Kawai Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Incorporated company Hitachi, Ltd., Production Technology Research Laboratory (72) Inventor Tetsuya Yamazaki Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture 292 Incorporated Company Hitachi, Ltd. Production Technology Laboratory (72) Inventor Shoji Fusatsu Totsuka, Yokohama, Kanagawa Prefecture 292, Yoshida-cho, Tokyo, Ltd., Production Engineering Laboratory, Hitachi, Ltd. (72) Inventor, Masayuki Kyoi, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture, Ltd., Production Engineering Laboratory, Hitachi, Ltd. (72) Hideki Sato, Kanagawa Prefecture 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Setsuo Ando 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi, Ltd.

Claims (16)

[Claims] 1. A base substrate connecting unit on a base substrate,
An inner layer circuit unit group in which a plurality of inner layer circuit units are laminated, and a surface layer unit are sequentially laminated to form a thin film multilayer circuit portion, which is a thin film multilayer circuit board, wherein each unit is an organic resin sheet. Forming electrical connection between the upper and lower wiring layers via the conductor vias arranged in
The interface of the organic resin sheet is melted and adhered to each other to form an integrated structure, and a pad coated with a surface metallization for mounting and connecting at least electronic components is arranged on the surface of the surface layer unit. On the surface of the inner layer circuit unit, a conductor via that slightly protrudes on the surface of the organic resin sheet and a bonding metal film that covers the surface of the conductor via are arranged, and the bonding metal film is formed. Electrical connection between the upper and lower wiring layers in the inner layer circuit unit group is formed by diffusing into both the underlying conductor via and the wiring pattern provided on the back surface of the inner layer circuit unit that is connected to the underlying via. And a thin film multilayer circuit board formed by the diffusion bonding section. 2. The thin film multilayer circuit board according to claim 1, wherein the conductor via and the wiring pattern are made of copper, and the joining metal film is made of a metal thin film which can be diffusion joined to copper at a temperature of 250 ° C. or less. 3. The thin film multilayer according to claim 1, wherein the bonding metal film is composed of a simple metal of any one of Sn and Zn or an alloy of any one of Sn—Zn, Sn—Ag and Sn—Pb. Circuit board. 4. The thin-film multilayer circuit board according to claim 1, wherein the organic resin material forming the organic resin sheet is composed of at least one resin selected from polyimide resin, polyamide resin and epoxy resin. 5. An organic resin sheet is used as a base material, and a conductor via that slightly protrudes at least on the surface of the organic resin sheet and a bonding metal film that covers the surface of the conductor via are arranged on the surface of the organic resin sheet. At the same time, a wiring pattern is provided on the back surface, the conductor vias and the wiring pattern are made of copper, and the bonding metal film is diffusion bonded to copper at a temperature of 250 ° C. or less and a glass transition temperature of the organic resin sheet or more. Inner layer circuit unit made of thin metal film. 6. An organic resin sheet is used as a base material, and a surface layer copper pad coated with a surface metallization for mounting and connecting at least electronic components is provided on the surface thereof, and a copper plating via is provided on the back surface through a copper plating via. A surface layer unit provided with a back surface connection pad electrically connected to the surface layer copper pad. 7. An organic resin sheet is used as a base material, an upper connection pad covered with at least an upper bonding metal film is disposed on the front surface, one end is connected to the upper connection pad on the back surface, and the other end is A copper-plated via that slightly protrudes from the surface of the organic resin sheet and a lower bonding metal film that covers the surface of the copper-plated via are arranged. The upper bonding metal film and the lower bonding metal film are formed of copper and 250 A base-substrate connecting unit composed of a metal thin film that can be diffusion-bonded at a temperature of ℃ or below and above the glass transition temperature of an organic resin sheet. 8. A step of preparing a thick film multilayer wiring substrate having a matching pad on the surface as a base substrate, and placing the base substrate connecting unit according to claim 7 on a surface plate having a smooth surface, A predetermined plurality of inner layer circuit units according to claim 5 and a surface layer unit according to claim 6 are sequentially laminated while performing optical pattern alignment, and these units are temporarily fixed to each other to temporarily fix the thin film multilayer circuit section. Forming the temporary fixing laminate, and connecting the base substrate of the temporary fixing laminate forming the thin film multilayer circuit section while performing optical pattern alignment on the thick film wiring substrate having the matching pad. A step of placing the back side of the unit and forming a temporary fixing laminate of the thin film multilayer circuit section-base substrate, and a temporary fixing by thermocompression bonding the thin film multilayer circuit section-base substrate temporary fixing laminate Method of manufacturing a thin film multi-layer circuit board comprising and a step of connecting fixing the laminate collectively. 9. The thin-film multi-layer circuit section-temporary fixing laminate of a base substrate is subjected to thermocompression bonding under a vacuum degree of 10 to 60 torr, a hydrostatic pressure of 15 to 30 kg / cm ² , and a glass transition temperature of an organic resin sheet constituting the unit or more. 9. The method for manufacturing a thin film multilayer circuit board according to claim 8, wherein the method comprises a hot pressing step performed at a temperature of 250 ° C. or lower. 10. An organic resin sheet as a base material of each unit is formed of at least one organic resin insulating film selected from polyimide, polyamide, and epoxy resin, and a base substrate is formed of a ceramic multilayer substrate. 9. The method for manufacturing a thin film multilayer circuit board according to claim 8. 11. A step of preparing an organic resin sheet in which copper foils having different thicknesses are bonded as upper and lower metal foils on both front and back surfaces of an organic resin insulating film, and an etching protection film is formed on a thick lower copper foil surface. In the formed state, the thin upper copper foil is processed by a photoetching process, a step of forming a via processing mask pattern, and a step of forming a via hole in an organic resin layer using the via processing mask pattern,
The process of removing the via processing mask pattern by wet etching, and copper plating is applied to the via hole using the lower copper foil as a power supply electrode, the via hole is filled with copper plating, and the tip of the copper-plated via is slightly smaller than the surface of the organic resin sheet. Stopping copper plating in a protruding state, subsequently plating the bonding metal on the tip of the copper plating via, and covering the sheet surface on which the via is formed with an etching protection film,
A method for manufacturing an inner layer circuit unit, which comprises a step of removing an etching protection film formed on a back surface and processing a lower copper foil exposed by the photo etching step to form a wiring pattern. 12. A step of preparing an organic resin sheet in which an aluminum foil is laminated as an upper metal foil on the front surface of an organic resin insulating film and a copper foil is laminated as a lower metal foil on the back surface, and the aluminum foil is processed by a photo-etching step. Forming a via processing mask pattern, forming a via hole in an organic resin layer using the via processing mask pattern, removing the via processing mask pattern by wet etching, and forming a lower metal foil on the back surface. Copper plating was applied to the via hole using the copper foil as a power supply electrode, the via hole was filled with copper plating, and the copper plating was stopped with the tip of the copper plated via slightly protruding from the surface of the organic resin sheet,
Subsequently, a step of plating a joining metal on the tip of the copper-plated via and a state in which the via-formed sheet surface is covered with an etching protection film, the copper foil on the back side is processed by a photo-etching step to form a wiring pattern. A method of manufacturing an inner layer circuit unit, which comprises: 13. The amount of protrusion of the tip of the copper-plated via protruding from the surface of the organic resin sheet is 1 to 10 μm, and the thickness of the joining metal plated on the tip of the copper-plated via is 1.
The method for manufacturing an inner layer circuit unit according to claim 11 or 12, wherein the inner layer circuit unit has a thickness of 10 μm. 14. The organic resin sheet is formed of at least one organic resin insulating film selected from polyimide, polyamide, and epoxy resin, and the bonding metal film is formed of copper and 250 ° C. or less. 13. The method for manufacturing an inner layer circuit unit according to claim 11 or 12, wherein the inner layer circuit unit is formed of a metal thin film capable of diffusion bonding at a temperature equal to or higher than the glass transition temperature. 15. The bonding metal film is a simple metal thin film of Sn or Zn, or Sn—Zn, Sn—A.
15. The method for manufacturing an inner layer circuit unit according to claim 14, wherein the inner layer circuit unit is formed of an alloy thin film of any one of g and Sn—Pb. 16. The step of forming a via hole in an organic resin layer using a via processing mask pattern is a dry etching step or a laser beam processing step.
13. The method for manufacturing an inner layer circuit unit according to 1 or 12.