JPH0813087B2 - Image reading device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image reading apparatus for reading image information of an image reading target by decomposing it into a plurality of lines, and more specifically, a plurality of photoelectric conversion units arranged side by side. The present invention relates to an image reading device that outputs read data in parallel from two or more photoelectric conversion units.

(Prior Art) A one-dimensional photoelectric conversion unit in which a large number of CCD elements (charge-coupled devices) are linearly arranged is not long in general due to manufacturing reasons, such as B5 and A4 sizes. It is usually a chip that is considerably shorter than the width of the original. Therefore, in order to read an image of the document width using such a short photoelectric conversion unit, an image sensor is configured by arranging a plurality of photoelectric conversion units for the document width.

By the way, conventionally, in the image reading of the image sensor including a plurality of photoelectric conversion units as described above, one by one is sequentially read from the photoelectric conversion unit at one end and the data is output. However, since the image reading time is determined by the data transfer rate of each CCD element, it takes a long time to read the image.

Therefore, there has been proposed a technique for increasing the speed of image reading by reading a plurality of photoelectric conversion units in parallel,
It is disclosed in Japanese Patent Publication No. 39961, 1987.

In this conventional example, a buffer having a plurality of storage units for writing read data from a plurality of photoelectric conversion units in parallel is used.
By individually providing data and reading and writing data alternately between the two buffers, the time required for reading one line of the image can be the time required for one photoelectric conversion unit to read the image. I have to.

Further, this conventional example will be specifically described with reference to FIG.

An image sensor is configured by arranging a plurality of photoelectric conversion units 41a, 41b, 41c, 41d. First, read data from the plurality of photoelectric conversion units 41a to 41d are written in parallel to the corresponding areas 43a, 43b, 43c, 43d of the first buffer 43 via the switch 42, respectively.

Next, the switch 42 is switched so that the data is written in each area 44a, 44b, 44c, 44d of the second buffer 44, and at the same time, the data previously written in the first buffer 43 is multiplexed. The data read by 45 is transmitted to the host computer (not shown) via the mixer 46.

Next, the switch 42 is switched again, and the first buffer is
Data is written in 43, and at the same time, the data previously written in the second buffer 44 is read by the multiplexer 47.

(Problems to be Solved by the Invention) However, the above conventional example has the following problems.

One of the buffers is writing data of all photoelectric conversion units and at the same time is reading from the other buffer. Therefore, two buffers 43 and 44 are required, and two buffers 43 and 44 are written. A device for switching between reading and reading is needed.

Therefore, the device is complicated and large, the manufacturing cost is increased, and the failure rate is increased.

An object of the present invention is to provide an image reading apparatus that realizes high-speed reading with a simple and small structure, thereby reducing the manufacturing cost and the failure rate.

Another object of the present invention is that photoelectric conversion units are arranged at anteroposterior intervals, and all data on the same line are collectively stored, so that data on the same line can be easily read in the arrangement order of the photoelectric conversion units. An object of the present invention is to provide an image reading device.

(Means for Solving the Problem) In order to achieve the above-mentioned object, the present invention provides a photoelectric conversion unit configured by linearly arranging a plurality of photoelectric conversion elements in a two-stage or multi-stage form in the sub-scanning direction. In an image reading device having a line image sensor arranged in a staggered pattern in the main scanning direction and reading the image information of an image reading target by dividing it into a plurality of lines, the photoelectric conversion units of the line image sensor are arranged in the same stage. The storage unit is divided into blocks for each photoelectric conversion unit to which it belongs, and has storage areas respectively corresponding to the respective blocks, and storage means for writing read data from the corresponding blocks to the respective storage areas; and writing to the respective storage areas, Start by sequentially delaying by the line interval between blocks and simultaneously write the read data from the corresponding block to each storage area. Then, the writing means for storing all the data of the same line of the image in the same bank of the storage means, and the bank of the written line before the n line when writing the data of the nth line by this writing means Readout output means is provided for reading out data in order of arrangement of the photoelectric conversion units at a speed equal to or higher than a value obtained by multiplying the writing speed by the number of blocks and transmitting the data to the outside. Item 1).

Instead of dividing the photoelectric conversion units of the line image sensor into photoelectric conversion units belonging to the same stage, the photoelectric conversion units belonging to the same stage of the photoelectric conversion units may be divided into a plurality of blocks ( Claim 2).

According to a third aspect of the present invention, the photoelectric conversion section is formed by linearly arranging a plurality of photoelectric conversion elements, and the photoelectric conversion sections are arranged in a staggered pattern in the main scanning direction in a two-stage configuration with a predetermined number of front-back intervals in the sub-scanning direction. In an image reading apparatus having an array of line image sensors and reading image information of an image reading target by dividing it into a plurality of lines, a photoelectric conversion unit of the line image sensor is blocked for each photoelectric conversion unit belonging to the same stage. In addition to dividing into blocks of preceding and succeeding blocks, a buffer having a storage area corresponding to each of the blocks, in which read data from the corresponding block is written to each storage area, and writing to each of the storage areas , The writing of data from the block in the succeeding row is started by delaying the writing of the preceding block by the predetermined number of lines, and the storage error is started. And writing means for simultaneously writing read data from the corresponding block to all the data in the same bank of the buffer and writing data of the nth line by the writing means. , Read-out means for reading the bank data of the written lines before the n-th line at a speed more than twice the writing speed in the order of arrangement of the photoelectric conversion units and transmitting the read data to the outside. It is a thing.

(Operation) In claim 1, on the premise of the line image sensor in which the photoelectric conversion units are arranged in two or more stages in the sub-scanning direction in a staggered manner in the main scanning direction, the same stage in the sub-scanning direction is assumed. It is divided into blocks for each photoelectric conversion unit belonging to. And
The read data from the photoelectric conversion units of the respective blocks are simultaneously written in the corresponding storage areas of the storage means. However, the writing means sequentially delays writing to each storage area by the line interval between blocks and simultaneously writes the read data from the corresponding block to each storage area, resulting in the image writing. All data on the same line are stored in the same bank of storage means.

Since the read data from the corresponding block is simultaneously written in each storage area, the time required for the writing is 1
Shorter than image reading lines in series.

The read output means reads the data of one line stored in the storage means in the order of arrangement of the photoelectric conversion units and transmits the data to the outside. The read data at this time is the data of the written line before the n-th line, assuming that the data of the n-th line is currently written in the storage means, and the read speed at this time is The speed is equal to or higher than a value obtained by multiplying the speed by the number of blocks. This eliminates the time lag that writing is parallel processing and reading is serial processing.

Further, the reading from the storage means is easily performed because all the data of the same line of the image are already stored in the same bank of the storage means.

 Such action and effect can be obtained also in claim 2.

The third aspect is premised on a line image sensor in which the photoelectric conversion units are arranged in a staggered manner in the main scanning direction in a two-step manner in the sub scanning direction. Then, the photoelectric conversion units belonging to the same stage in the sub-scanning direction are divided into blocks, divided into preceding and subsequent blocks, and the read data from the photoelectric conversion units of each block is stored in the corresponding storage area of the buffer. Write in. However, the writing means starts writing to each storage area by delaying the line interval between blocks to start writing data read from the corresponding block to each storage area at the same time, and as a result, the same line of the image is written. Store all data in the same bank of buffers. In other words, the bank position where the block in the subsequent row is written matches the position in the preceding block. Since the read data from the corresponding block is written in each storage area at the same time, the time required for the writing is shorter than the case of serially reading one line of the image, as in the first aspect.

The read output means reads the bank data of one line stored in the buffer in the order of arrangement of the photoelectric conversion units and transmits the data to the outside. The read speed at this time is 2 times the write speed.
Since the writing is performed in parallel and the reading is performed in serial, the time lag is eliminated because the writing is performed at a speed twice or more.
Further, the reading from this buffer is easily performed because the data of the blocks of the preceding and succeeding rows are already written in the same bank position.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 10.

First, the apparatus of this embodiment will be described with reference to FIG.

A motor 1 for driving the sensor unit is provided, and a drive belt 3 rotated by the motor 1 via a reduction gear 2 is provided. A sensor unit 4 is coupled to the drive belt 3 and the sensor unit 4 is the above-mentioned. The drive belt 3 reciprocates along the slide base 5.

An original surface 6 made of transparent glass is provided on the upper surface of the apparatus, and a light source 7 for irradiating an original as an image reading target is provided for the sensor unit 4, and the sensor unit 4 receives the reflected light and reads the image. Is supposed to do.

A home position sensor 8 for detecting that the position of the sensor unit 4 is at the home position is provided near the end of the slide base 5, and a reading start reference plate 9 is provided near the home position sensor 8. The sensor unit 4 is provided to read the read start reference data of the read start reference plate 9, and the sensor unit 4 moves by a predetermined number of steps of the read start reference data to start the image reading of the document.

Next, an outline of the circuit of the above device will be described with reference to FIG.

The sensor unit (see FIG. 2) has a large number of
Four chip-shaped photoelectric conversion units 10a, 10b, 10c, and 10d in which CCD devices (charge-coupled devices) are linearly arranged are arranged in a zigzag pattern in the document width direction (main scanning direction). The photoelectric conversion unit 10 converts light from a document into an electric signal. The preceding photoelectric conversion units 10b and 10d and the subsequent photoelectric conversion unit 10
As shown in FIG. 3, a and 10c have a predetermined line interval g (four line intervals in this example).

The reason for arranging the plurality of photoelectric conversion units in a zigzag pattern of two stages before and after without linearly bonding them in a line is that it is difficult to completely bond the photoelectric conversion units without impairing the image reading function. Is.

Then, the photoelectric conversion units 10a to 10d are moved in the sub-scanning direction orthogonal to the main scanning direction so that the image information of the document is divided into a plurality of lines and read.

The preceding two photoelectric conversion units 10b and 10d and the following two photoelectric conversion units 10a and 10c are divided into different blocks 11a and 11b, respectively. The preceding block 11a is an amplifier 12a for signal amplification and an A / D converter for analog-digital conversion.
13a, and is connected to the preceding block area 14a of the buffer 14 serving as buffer storage means. On the other hand, the subsequent block 11b is connected to the subsequent block area 14b of the buffer 14 via the amplifier 12b and the A / D converter 13b.

The buffer 14 is composed of 16 banks, and one line of data is sequentially written in each bank (see FIG. 7 below). Also, one bank has both areas 14a, 1a.
4b has addresses 0 to 1763, respectively.

Both areas 14a and 14b are connected to one synthesizing circuit 15, and the synthesizing circuit 15 reads out the data in the arrangement order of the photoelectric conversion units and synthesizes them. This synthesizing circuit 15 is connected to two parallel RAMs 16a and 16b, and simultaneously writes n lines of data into one of the RAMs, and simultaneously (n-1) from the other RAM.
The written data on the line is read out, and this operation is performed by alternating between the RAMs. This RAM 16a, 16b
Is connected to the host computer via interface 17.

In addition, conversion timing of the A / D converters 13a and 13b, writing to the preceding and succeeding block areas 14a and 14b,
A timing ROM 18 that stores timing data for controlling the read timing is provided.

Next, the buffer write / read control means will be described in detail with reference to FIG. First, the writing means is configured as follows.

Write-read switching gates 19a and 19b are provided in front of both areas 14a and 14b, respectively, and when these gates 19a and 19b are opened, they are written in the areas 14a and 14b, respectively.
The data is read from 4b and opened and closed alternately so that the write operation and the read operation are time-division controlled.
Then, as described later, two pieces of data are simultaneously buffered.
However, the data read from the buffer 14 is 1
Since one piece of data is written, two pieces of data are read at the time when one piece of data is written.

Leading and trailing blocks each have one photoelectric converter 10b, 1
Read data of 0a is 0 to 881 of both areas 14a and 14b at the same time.
Then, the read data of the other photoelectric conversion units 10d and 10c respectively in the preceding and succeeding blocks are simultaneously written in the addresses 882 to 1763 of both areas 14a and 14b.

Further, there is provided one write address counter 20 and its gate 21 for counting the addresses 0 to 881 and the addresses 882 to 1763 and alternately changing the photoelectric conversion units for inputting data.

Further, write bank counters 22a and 22b for counting write banks and gates 23a and 23b thereof are provided in both areas 14a and 14b, respectively. Then, the writing bank counter 22a for the preceding block is controlled to start the counting of the writing bank counter 22b for the succeeding block by the interval of the above four lines, that is, four banks later than the start of the bank count by the writing bank counter 22a for the same block. All data are written in the same bank.

The above timing ROM, write / read switching gates 19a and 19b, write address counter 20 and its gate 21, write bank counters 22a and 22b and its gate 2
Writing means is constituted by 3a and 23b.

At the same time as writing the data of the nth line, (n-
1) Data for which writing has been completed on the line 1 is read out, and one reading bank counter 24 and its gate 25 are provided in both areas 14a and 14b.

Further, the read output means for reading the data of one line stored in one bank in the order of arrangement of the photoelectric conversion units 10a to 10d and transmitting it to the outside is configured as follows. That is, the read address counters 26a and 26b and the gates thereof for counting the addresses at the time of reading in both areas 14a and 14b, respectively.
27a and 27b are provided, and the latter stages of both areas 14a and 14b are connected to data selection gates 28a and 28b, respectively, and the two data selection gates 28a and 28b are alternately opened and closed for the subsequent block area. 14b 0-881, preceding block area 14a 0-881, trailing block area 14b 882-
The address 1763 and the preceding block area 14a, addresses 882 to 1763, are read in this order. This data selection gate
28a and 28b are connected to the register 29, and the register 29 has 1
Each line data is stored. The data selecting gates 28a and 28b and the register 29 constitute the synthesizing circuit 15 (see FIG. 1). In addition, as described above, the read clock is set to twice the speed of the write clock (for example, byte / Sec) so that two data are read at the time when one data is written.

The embodiment configured as described above operates as follows.

Referring to FIG. 2, the rotation of the motor 1 is transmitted to the drive belt 3 via the reduction gear 2, and the sensor unit 4 connected to the drive belt 3 is moved along the slide base 5. The sensor unit 4 moves from the home position, the sensor unit 4 reads the reading start reference data 9 of the reading start reference plate 9, and the image reading of the document starts from the position moved by a predetermined number of steps of the reference data. That is, referring to FIG. 1, the photoelectric conversion unit 10 is arranged in the sub-scanning direction.
Move a to 10d to irradiate the original from the light source 7,
The photoelectric conversion units 10a to 10d convert the reflected light into electric signals (see FIG. 2).

Referring to FIG. 4, a gate for switching between writing and reading
Time division control is performed in which areas 19a and 19b are written in areas 14a and 14b when they are opened and are read from areas 14a and 14b when they are closed. By the way, since two data are written at the same time while reading is performed one data at a time, it is necessary to perform the read operation at a speed more than twice as fast as the write operation. Therefore,
As shown in FIG. 5, the read clock is twice as fast as the write clock, and two data are read at the time of writing one data.

With reference to FIG. 1, the signals from the preceding and following blocks 11a and 11b are respectively amplified by amplifiers 12a and 12b, converted from analog to digital by A / D converters 13a and 13b, and then buffer 14 Are input to both areas 14a and 14b.

Further, referring to FIG. 4, write bank counters 22a and 22b count the banks to be written in both areas 14a and 14b, respectively. However, the bank count by the write bank counter 22b for the succeeding block is started by the interval of four lines, that is, four banks later than the start of the bank count by the write bank counter 22a for the preceding block.

This will be explained with reference to FIG. 6 as well.
The next write bank (line) is counted when the D signal (readout end) pulse falls, and the RDEND signal (readout end) and the E1 signal (countable signal) are ANDed.
Then, the write bank counter 22b in the subsequent block area starts counting. Then, when the writing bank counter 22a of the preceding block area counts the fifth line, the E1 signal (countable signal) is set so that the writing bank counter 22b of the succeeding block area starts counting the first line. ) Is output. Also,
Referring to FIG. 7, the fifth line is written in the preceding block area 14a, and at the same time, the first line is started to be written in the succeeding block area 14b. Thereafter, all the data on the same line are sequentially written in the same bank. It is supposed to be crowded.

Referring to FIG. 4, the read data of the photoelectric conversion units 10b and 10a for each of the preceding and succeeding blocks are simultaneously written to addresses 0 to 881 in both areas, and the write address counter 20 counts the address 881. Then, the input photoelectric conversion units are replaced, and the preceding and succeeding blocks are replaced by the other photoelectric conversion units 10d, 1
The read data of 0c is simultaneously written to the addresses 882 to 1763 in both areas.

Then, at the same time when the data of n lines is written, (n−
1) The data for which the writing of the line 1 has been completed is read in a time division manner. Read bank to read bank counter
24 counts.

This will be described with reference to FIG. 6 together. For the read operation, the RDEND signal (read end) that counts the next read bank (line) at the fall and the E2 signal (countable signal) are ANDed. The bank counter 24 starts counting. Then, when the write bank counter 22b for the succeeding block counts the second line, the read bank counter 24 outputs the E2 signal (countable signal) so as to start counting the first line.

Next, referring to FIG. 4, two data selection gates are provided.
By 28a and 28b, the data of one line stored in one bank is arranged in the order of arrangement of the photoelectric conversion units 10a to 10d, that is, as shown in FIG. Area 0-881, Trailing Block Area 882-1763, Leading Block Area 8
The addresses 82 to 1763 are read out in order, and the register 29 synthesizes the data for each line in the arrangement order of the photoelectric conversion units (see FIG. 9).

The read address counters 26a and 26b count the addresses during the reading (see FIG. 4).

Referring to FIG. 1, next to the synthesis circuit 15, the data of the nth line is written into one of the RAMs 16a (16b), and at the same time, the other RAM 16b (16a) to the (n-1) th line is written. The written data is read out, this operation is alternately performed between the RAMs, and the data read out from this RAM is transmitted to the host computer via the interface 17.

The operation described above will be collectively described with reference to FIG.

WTGATE signal (write signal) for each image data
Is output, and this MCLK is twice the WTGATE signal (write signal).
A signal (readout signal) is output and two pieces of data are read at the time of writing one piece of data.

2 during the first high of the DENBL signal (data enable signal)
Write one read data to addresses 0 to 881 in both areas at the same time, write two read data to addresses 882 to 1763 in both areas at the same time during the next high of DENBL signal (data enable signal), and write the write address Address counter for counting.

Further, while the writing bank counter of the preceding block area is counting the writing of the (n + 4) th line, the writing bank counter of the succeeding block area is counting the writing of the nth line, and is simultaneously read. The bank counter for counting counts the reading of the (n-1) line.

While the DENBL signal (data enable signal) is high, RBSLCT
When the signal (address selection signal) is high, the read address counter counts the reading of addresses 0 to 881, and when the RBSLCT signal is low, the read address counter reads the addresses 882 to 1763, respectively. Is to count.

When the output of the two pulses of the DENBL signal (data enable signal) ends, the RDEND signal (read end) is output.

As described above, in this embodiment, the four photoelectric conversion units are divided into two blocks for every two leading and trailing lines, and read data from these two blocks are simultaneously written into one buffer, Write the data of the nth line to (n
-1) The data in the written line of the 1st line is read in the arrangement order of the photoelectric conversion units at a speed twice that of the writing. Therefore, high-speed reading can be realized with one buffer, the device can be simplified and downsized, and the manufacturing cost and the failure rate can be reduced.

In addition, since writing from the block in the subsequent row is started with a delay of four line intervals between the two blocks from the preceding block, all data on the same line can be written in the same bank, and data in the same bank is photoelectrically converted. Reading can be easily performed in the arrangement order of the conversion units.

It goes without saying that the present invention is not limited to the above embodiments, and examples such as those shown in FIGS. 11 to 14 are also included in the present invention. In FIGS. 11 to 14, reference numeral 31 is a photoelectric conversion unit, 32 is a buffer, and 33 is a synthesizing circuit.

In the above embodiment, two data are written simultaneously from two blocks, so the read speed is twice as fast as the write, but the read speed may be (write speed × number of blocks) or more. For example, in the case of FIG. 11, since eight photoelectric conversion units 31 are divided into four blocks and four data are simultaneously written from the four blocks, the reading speed is (writing speed × 4) or more. To

Further, the number of photoelectric conversion units is not limited to four, but may be any plural number, eight in FIG. 11 and six in FIGS. 12 and 13.
14 are illustrated in FIG. 14, respectively.

Also, the number of photoelectric conversion units in one block is not limited to two, and it may be plural or singular. For example, in FIG. 13, the number of photoelectric conversion units in one block is three, and in FIG. Is one.

Further, the arrangement of the photoelectric conversion units is not limited to the zigzag pattern of the front and rear two stages. For example, the one shown in FIG. 14 is linearly arranged in a line, and the one shown in FIG. 12 is arranged in the front and rear three stages.

Further, in the above-mentioned embodiment, since the arrangement of the photoelectric conversion units is two stages before and after, the writing of the data from the block in the subsequent line is started after the preceding block, which is shown in FIG. As described above, in the case where the blocks are arranged in the front and rear three stages, writing is started in sequence with the preceding block, the middle block, and the succeeding block.

Further, in the above-described embodiment, the data of the completed writing of the (n-1) th line is read simultaneously with the writing of the data of the nth line.
It suffices to read the data of the written line before the n line.

(Effects of the Invention) According to the invention described above, the following effects are obtained.

At the same time, the read data from the photoelectric conversion unit of each block is written in each corresponding storage area of the storage means, and when writing the data of the nth line, the bank data of the written line before the nth line is Since the photoelectric conversion units are read in the arrangement order at a speed equal to or higher than the value obtained by multiplying the writing speed by the number of blocks, high speed reading can be realized with one storage unit, and the device can be simplified and downsized. Therefore, reduction in manufacturing cost and failure rate can be achieved.

Writing to each storage area is sequentially delayed by the line interval between blocks, and the data read from the corresponding block is simultaneously written to each storage area. As a result, all of the same lines of the image are written. Data is stored in the same bank of the storage means. Therefore, all the data on the same line can be collectively written, and the data on the same line can be easily read in the arrangement order of the photoelectric conversion units.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a circuit of an embodiment of the present invention. FIG. 2 is a vertical sectional view of the apparatus of the above embodiment. FIG. 3 is a partially enlarged view of FIG. FIG. 4 is a circuit diagram of the write / read control means of the above embodiment. FIG. 5 is a time chart showing the writing and reading speeds in the above embodiment. FIG. 6 is a time chart for explaining the start of writing and reading in the above embodiment. FIG. 7 is an explanatory diagram of writing values and values in the above embodiment. FIG. 8 is a time chart for explaining the reading in the above embodiment. FIG. 9 is a time chart for explaining the reading in the above embodiment. FIG. 10 is a time chart for explaining the overall operation of the above embodiment. FIG. 11 is a circuit diagram of another embodiment. FIG. 12 is a circuit diagram of still another embodiment. FIG. 13 is a circuit diagram of still another embodiment. FIG. 14 is a circuit diagram of still another embodiment. FIG. 15 is a diagram showing a conventional example. 10a to 10d: photoelectric conversion unit 11a: preceding block 11b: succeeding block 14: buffer (storage means) 14a: preceding block area 14b: succeeding block area 15: combining circuit 19a, 19b: write / read switching gate 20 : Write address counter 22a: Write bank counter (first) 22b: Write bank counter (second) 24: Read bank counter 26a: Read address counter (first) 26b: Read address counter (second) 28 : Data selection gate 29: Register

Claims (3)

[Claims] 1. A line image sensor comprising a plurality of photoelectric conversion elements arranged linearly and arranged in a staggered manner in the main scanning direction in a two-stage or multi-stage manner in the sub-scanning direction. In an image reading device that reads the image information of the image reading target by decomposing it into a plurality of lines, the photoelectric conversion unit of the line image sensor is divided into blocks for each photoelectric conversion unit belonging to the same stage, and in each of the blocks. Each has a corresponding storage area,
Storage means for writing read data from the corresponding block to each storage area, and writing to each storage area are sequentially delayed by a line interval between the blocks and started to start each storage area from the corresponding block. The read data is written at the same time, and all the data of the same line of the image is stored in the same bank of the storage means, and when writing the data of the nth line by this writing means, the data before the nth line is written. Read output means for reading bank data of written lines at a speed equal to or higher than a value obtained by multiplying the writing speed by the number of blocks and transmitting the data to the outside in the arrangement order of the photoelectric conversion units. Characteristic image reading device. 2. The photoelectric conversion unit of the line image sensor is divided into blocks for each photoelectric conversion unit belonging to the same stage, and the photoelectric conversion unit belonging to the same stage among the photoelectric conversion units is divided into a plurality of blocks. The image reading apparatus according to claim 1, wherein the image reading apparatus is divided. 3. A photoelectric conversion section composed of a plurality of photoelectric conversion elements arranged linearly is arranged in a staggered pattern in the main scanning direction in a two-stage form with a predetermined number of front-back intervals in the sub-scanning direction. In an image reading apparatus having a line image sensor configured to read image information of an image reading target by dividing it into a plurality of lines, the photoelectric conversion unit of the line image sensor is divided into blocks for each photoelectric conversion unit belonging to the same stage. And divides into leading and trailing blocks, and has a storage area corresponding to each of the blocks,
A buffer to which the read data from the corresponding block is written in each storage area, and when writing to each storage area, writing the data from the block in the subsequent row is delayed by the predetermined number of lines from the writing in the preceding block. Starting from the same time, the read data from the corresponding block is written into each of the storage areas at the same time, and all the data of the same line of the image is stored in the same bank of the buffer. When writing data, the read output means for reading the bank data of the written line before the n line at a speed twice or more the writing speed in the order of arrangement of the photoelectric conversion units and transmitting it to the outside. An image reading apparatus characterized by being provided with.