JPH08129576A - Method for designing mask layout of semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce skew and delay values in semiconductor device layout design. [Structure] In a block arranging step 101, the size and shape of a wiring channel between blocks are estimated, block arranging processing is performed, and in a block arranging and wiring step 102, the inside of each block is arranged and wired. Hierarchical expansion step 103
Then, all the blocks of the semiconductor device are expanded, and clock wiring is performed in the clock wiring step 104 so that the skew from the clock generation source to the clock terminal of the expanded block is minimized. Extract. Using the extracted information about the clock wiring, the wiring within the block is performed again in the intra-block rewiring step 106, and the wiring between blocks is performed in the inter-block wiring step 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask layout design method for designing a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices become finer and higher in density,
The man-hours and processing time required for layout design increase exponentially as the scale increases. Therefore, it takes a huge amount of time and labor to layout the entire semiconductor device at once. In order to solve the above-mentioned problem, the semiconductor device is divided into a plurality of blocks according to the function and scale of the circuit, and the placement and routing is performed for each block except the predesigned macroblock, and then the wiring between the blocks is performed. A design method called "hierarchical design method" is widely used.

Further, as a large-scale and high-speed semiconductor device is developed, an increase in delay value accompanying an increase in wiring length cannot be ignored. In particular, when the delay value difference (skew) of the clock signals is large, a difference occurs in the arrival time of the clock input signals such as the flip-flops, and the semiconductor device does not move or malfunctions such as malfunction are caused. Therefore, a mask layout designing method, which is a method called "clock tree method", which eliminates the above-described adverse effects, has been proposed.

As a "clock tree method" mask layout designing method, for example, as a designing method for synchronizing the inside of a block, there is a known example "exact zero skew".
(Proceeding IEEE Int. Conference on Comp
uter-Aided Design, pp336-339, 1991). In the well-known example "Exact Xeroscue", first, the related cells are divided into groups called clusters,
Clustering is performed by repeating the two-division processing so that the load capacities in each cluster are equalized, and the clock terminals in the cluster are routed in the shortest path. Further, by the recursive bisection processing, driver cells that minimize the delay are inserted into nodes between clusters to form a hierarchical tree structure. Then, in order from the lowest hierarchy, the branch point of the tree is minimized to minimize the wiring, and after the wiring for each hierarchy is completed, the skew or the skew is reduced or eliminated by changing the position or size of the buffer cell. To do.

As a concrete method, a design flow widely used in the prior art will be described with reference to FIG.

In the block arranging step 801, a block or a block arranging algorithm is manually used, and blocks other than predesigned macroblocks are sized and shaped based on information such as the number of cells and the number of nets included in the circuit connection information. Accurately estimate the wiring layer and position of external terminals. In addition, accurately estimate the size and shape of the wiring channel between blocks,
Determine the placement of blocks.

In the in-block placement / routing step 802, all circuit connections including the circuit connection information of the clock signal are used by using the in-block placement / routing algorithm having an algorithm capable of reducing the skew such as "clock tree method". According to the information, the blocks other than the macro block are arranged and wired, and the skew from the clock external terminal to the clock terminal inside the block is reduced or eliminated.

In the inter-block wiring step 803, the wiring of the clock signal is set so that the skew from the clock generation source to the clock external terminal falls within a predetermined range based on the information of each clock external terminal position and load. Make wiring other than clock signals.

FIG. 9 shows the result of layout performed according to the flow of FIG. In FIG. 9, in order to make the results of the clock wiring easier to understand, the blocks are expanded after layout and wiring other than the clock signal is omitted.

As shown in FIG. 9, according to the conventional mask layout designing method, the skew to each clock terminal 401 in blocks 204 to 208 can be reduced or eliminated. Two
Since the wiring paths to the clock terminal 401 inside each of the 08 and the number of the clock terminals 401 are different, it can be seen that the values of the clock signal loads of the blocks 204 to 208 are different. Optimal values such as the length of the clock signal wiring 906 between the blocks, the connection point of the clock signal wiring 906, the position of the clock distribution unit 905, and the clock external terminals 901 to 904 are obtained according to the load inside the block. Therefore, it is difficult to reduce the skew between the blocks.

Unless a specific wiring layer is used for the clock signal wiring 906, the inside of the block cannot be used as a wiring area between blocks, so that detour wiring must be performed between blocks. Further, in order to make the length of the wiring 906 for the clock signal between blocks to be the optimum length, it is necessary to perform processing such as wiring around the wiring. Therefore, redundant wiring occurs and the delay value of the clock signal increases.

[0012]

In the prior art "clock tree method", the skew inside each block is reduced,
Or it can be resolved. However, when considering the entire semiconductor device, skew and delay between blocks may occur due to differences in the wiring path from the clock source to the clock terminal of each block and differences in the load inside each block (for example, the number of flip-flops). It was very difficult to design a synchronous circuit to reduce the value.

An object of the present invention is to provide a mask layout method for a semiconductor device, which solves the problems of the above-described conventional design method and can easily realize a highly accurate and balanced clock wiring.

[0014]

In order to achieve this object, a block arranging step for estimating the size and shape of a block and a wiring channel between the blocks and arranging the blocks, and the block arranging step are designed in advance. The placement and routing of cells inside each block except for the specified macroblock, a step of placing and routing a block, a step of expanding the hierarchy of all blocks after the step of placing and wiring the block, and a step of expanding the layer. Later, a clock wiring process that extracts information such as clock pin positions and loads that require clock input, and performs only clock wiring to minimize skew from the clock generation source to each clock terminal, and a clock wiring process After that, a clock wiring extraction step of extracting information on the installed clock wiring,
After the clock wiring information extraction step, a block rewiring step that performs wiring processing inside the block with the extracted clock wiring information as a constraint condition, and after the intra-block rewiring step,
The wiring channel between the re-routed blocks is characterized by including an inter-block wiring step of wiring between blocks with the clock wiring information extracted in the clock wiring information extraction step as a constraint condition.

[0015]

According to the present invention, when a clock signal is wired in a hierarchical layout design, the block hierarchy is expanded, the clock signal is wired, and the information of the expanded clock signal wiring is displayed. It is possible to easily reduce the shift of the clock signal from the clock generation source to each clock terminal by using the method of reducing the skew inside the block by using the layout design again hierarchically.

[0016]

【Example】

Example 1 An example of the present invention will be described below with reference to the drawings.

The flow of the present invention will be described with reference to FIG. The present invention comprises a block placement process 101, a block placement and routing process 102, a hierarchical expansion process 103, a clock wiring process 104, a clock wiring information extraction process 105, an intra-block rewiring process 106, and an inter-block wiring process 107. .

The block arranging step 101 will be described with reference to FIG. FIG. 2 shows the semiconductor device 20.
1. A clock generation source 202 provided near the center of the upper side of the semiconductor device, a predesigned macroblock 203,
Blocks 204 to 208 in which internal placement and wiring are performed,
Wiring channels 209 between blocks are shown.

In the block arranging step 101, blocks 204 to 208 excluding the predesigned macroblock 203 are manually used or an interblock arranging algorithm is used.
For each of these, the size, shape, wiring layer and position of the external terminal are accurately estimated from information such as the number of cells and the number of nets included in the circuit connection information. Further, the size and shape of the wiring channel 209 between blocks are accurately estimated to determine the block layout.

In the in-block placement / wiring step 102, the area and total wiring length of each of the blocks 204 to 208 are minimized according to the circuit connection information excluding the circuit connection information of the clock signal using the in-block placement / wiring algorithm. Place and route.

The hierarchy expanding step 103 will be described with reference to FIG. FIG. 3 shows the outer frame 3 of each macroblock.
01, outer frames 302 to 3 of blocks in which the inside is arranged and wired
06, a cell column 307, and a cell 308 included in each cell column.

In the hierarchical expansion step 103, the predesigned macroblock 203 shown in FIG. 2 and the block 20 to which the internal layout and wiring have been applied in the intra-block layout and wiring step 102.
Information such as the outer frame 301 of the macroblock illustrated in FIG. 3, the outer frames 302 to 306 of the blocks 204 to 208, the cell row 307, and the cell 308 included in each cell row is displayed from all blocks 4 to 208. Extract and expand the block based on that information.

The clock wiring process 104 will be described with reference to FIG. FIG. 4 shows a clock terminal 401 and a clock signal wiring 40 each requiring a clock input.
2 shows a clock distribution unit 403 which is a connection point of the wiring 402 of the clock signal that minimizes the skew to each clock terminal 401.

In the clock wiring step 104, the conventional technique "on the basis of the position and load information of each clock terminal 401 which requires the clock input of the cell 308 inside the cell row 307 extracted in the hierarchical expansion step 103. By using a binary tree clock tree used in the "clock tree method", the clock signal is fed from the respective clock terminals 401 to the clock generation source 202 in a bottom-up manner according to the circuit connection information of the clock signal so as to minimize the skew. Wiring only.

The clock wiring information extraction step 105 will be described with reference to FIG. FIG. 5 shows clock external terminals 501 to 511, respectively. In the clock wiring information extraction step 105, based on the information of the outer frames 302 to 306 of the block extracted in the hierarchical expansion step 103, clocks are respectively applied to the intersections of the clock signal wiring 402 and the outer frames 302 to 306 of the block. The external terminals 501 to 511 are generated. Regarding the clock wiring inside the block, for each generated clock external terminal 501 to 511, the clock terminal 40 succeeding to each clock external terminal 501 to 511
1 and the information of the wiring 402 of the clock signal are extracted, and the circuit connection information of the extracted wiring is generated. Regarding the wiring 402 of the clock signal between the blocks, the clock external terminal 50
1 to 511, and the clock generation source 20
2 and information of the wiring 402 of the clock signal between the clock external terminals 501 to 511, respectively, and circuit connection information of the extracted wiring is generated.

In the intra-block rewiring step 106, the information and the circuit of the clock signal wiring 402 in the block extracted in the clock wiring information extraction step 105 are obtained with respect to the placement and routing result obtained in the intra-block placement and routing step 102. The wiring 402 for the clock signal is installed based on the connection information. If a design rule error occurs due to the provision of the clock signal wiring 402, the clock signal wiring 402
Does not change and improves the wiring result obtained in the in-block placement and wiring step 102. By improving the wiring result obtained in the in-block placement / wiring step 102, the cell row 307
If the wiring channel between them expands and the cell row 307 moves,
The clock signal wiring 402 is expanded and contracted by the amount of movement in the direction in which the cell row 307 moves, and fine adjustment is performed to prevent the clock signal wiring from being broken. In FIG. 6A, the block placement and wiring process 10 is performed.
The wiring 402 of the clock signal extracted in the clock wiring information extraction step 105 with respect to the placement and wiring result obtained in 2
FIG. 6B shows a result of performing the fine adjustment, as a result of improving the wiring result obtained in the in-block placement and wiring step 102, as a result of the establishment of the above. In FIGS. 6A and 6B, in order to clarify the result of the clock wiring in the intra-block rewiring step 106, wirings other than the clock signal wiring 402 are omitted.

In the inter-block wiring step 107, the block expanded in the hierarchical expansion step 103 is replaced with the block re-wired in the intra-block re-wiring step 106 or a predesigned macro block in which no hierarchy is expanded, Based on the clock signal wiring information and the circuit connection information extracted in the clock wiring information extraction step 105, the clock signal wiring 402 between the blocks is preliminarily provided as an initial wiring, and the blocks between the blocks except the circuit connection information of the clock signal are installed. Wiring processing is performed based on the circuit connection information. Since the clock signal wiring 402 is provided, the shape and size of the block are changed, and when the positions of the clock external terminals 501 to 511 are moved or the wiring channel 209 between the blocks is expanded, the wiring is prevented from being broken. The adjustment is performed by expanding and contracting the wiring 402 of the clock signal between the blocks according to the moving direction and the moving amount.

FIG. 7 shows the result of one embodiment in which the layout according to the present invention described above is performed. FIG. 7A shows a layout result of a semiconductor device having layers. Fig. 7 (b)
Shows the layout results of blocks 204 to 208, respectively. In FIGS. 7A and 7B, in order to clarify the result of the clock wiring, wirings other than the clock signal wiring 402 are omitted.

As shown in FIG. 7, during clock wiring,
By expanding the hierarchy, the clock signal wiring 402 is
It can be executed regardless of whether it is in a block or between blocks. Therefore, since the detour wiring and the wiring for skew adjustment are not required, the delay value can be reduced.

Since the clock external terminals 501 to 511 and the clock distribution unit 403 are arranged after the clock signal wiring which minimizes the skew is arranged, it can be arranged very easily and at an optimum position.

The wiring 402 for the clock signal uses the result of wiring so that the skew from the clock generation source 202 to each clock terminal is minimized, and the hierarchical layout design is performed again, so that a highly accurate clock is obtained. The signal wiring can be easily obtained.

In this embodiment, the clock wiring process 1
Although the skew is reduced by using the binary tree clock tree of the “clock tree method” in 04, other algorithms capable of reducing the skew may be used.

In the intra-block rewiring step 106, the placement information obtained in the intra-block placement and routing step 102 is used, and the clock signal wiring is performed based on the clock signal wiring information extracted in the clock wiring information extraction step 105. Is laid in advance as an initial wiring, and the in-block placement / wiring step 102
Wiring processing similar to the above may be performed.

The width of the wiring used for the clock wiring may be gradually reduced from the clock signal generation source 202 toward the clock terminal. In this case, the area is increased, but the delay of the clock signal can be reduced.

The wiring layer used for the wiring 402 of the clock signal is arbitrary. In order to clarify the clock distribution unit 403, an object is given to the clock distribution unit 403, but it need not be given.

[0036]

As described above, according to the synchronous circuit layout design method for a semiconductor device according to the present invention, in the hierarchical layout design, the block hierarchy is expanded when clock signal wiring is performed. It is easy to reduce the delay value and skew in the entire semiconductor device by wiring the clock signal and using the developed information of the wiring of the clock signal to perform hierarchical layout design again. You can

[Brief description of drawings]

FIG. 1 is a flow chart of a synchronous circuit layout design method for a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing an execution result of a block placement step 101 according to an embodiment of the present invention.

FIG. 3 is a diagram showing an execution result of a hierarchy expanding step 103 according to an embodiment of the present invention.

FIG. 4 is a diagram showing an execution result of a clock wiring process 104 according to an embodiment of the present invention.

FIG. 5 is a diagram showing an execution result of a clock wiring information extracting step 105 according to an embodiment of the present invention.

FIG. 6 is a block rewiring step 10 according to an embodiment of the present invention.
Figure showing the execution result of 6

FIG. 7 is a diagram showing a result of execution of an embodiment of the present invention.

FIG. 8 is a flow chart of a synchronous circuit layout designing method for a semiconductor device which is widely used in the related art.

9 is a diagram showing a result of executing layout according to the flow chart of FIG.

[Explanation of symbols]

 101 Block Placement Step 102 In-Block Placement / Wiring Step 103 Hierarchical Expansion Step 104 Clock Wiring Step 105 Clock Wiring Information Extraction Step 106 In-block Rewiring Step 107 Inter-block Wiring Step

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822 H01L 21/82 W 27/04 A

Claims (1)

[Claims] 1. A block arranging step of estimating a size and a shape of a wiring channel between blocks and arranging the blocks, and after the block arranging step, a cell inside each block excluding a predesigned macro block is arranged. In-block placement / routing step for performing placement and routing processing; Hierarchical unfolding step for unfolding all block hierarchies after the in-block placing / wiring step; and Clock terminal position requiring clock input after the hierarchical unfolding step Information such as load and load, and clock wiring process that performs only the wiring of the clock so that the skew from the clock generation source to each clock terminal is minimized, and the information of the installed clock wiring after the clock wiring process The clock wiring extraction process that is performed and the extracted clock distribution after the clock wiring information extraction process. The intra-block rewiring step for performing the wiring processing inside the block with the information as a constraint condition, and the clock wiring extracted between the rerouted wiring channels between the blocks in the clock wiring information extracting step after the intra-block rewiring step A mask layout designing method, characterized in that it includes an inter-block wiring step of performing wiring between blocks using information as a constraint condition.