JPH0812902B2 - Master-slice type semiconductor integrated circuit with built-in memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a master slice type LS such as a gate array.
The present invention relates to I, and particularly to a memory circuit such as ROM and RAM incorporated therein.

[Conventional technology]

Conventionally, as shown in FIG. 8, a memory circuit built in a master slice type LSI of this type selects a matrix of memory cells 1 by an address decoder 6 and a column selector 8 and inputs them by a sense amplifier 13 and a write amplifier 17. Various control signals such as address, read / write control, and chip select are output from the input terminal 21 to the control circuit 12 and added to the address decoder 6, column address decoder 7, sense amplifier 3, and write amplifier 17. The bit / word structure for each memory circuit is fixed, and it has been impossible to realize a memory circuit having an arbitrary bit / word structure.

[Problems to be solved by the invention]

The conventional master slice type integrated circuit (LSI) described above
The built-in memory circuit is 1 memory circuit (1 block)
Since the bit and word configuration per hit is fixed,
It is impossible to realize a memory circuit (block) having an arbitrary bit / word structure. In an LSI with multiple memory blocks, some bit blocks can be combined in a memory by combining some memory blocks. In this case, control of the memory blocks to be combined is, for example, Since the gate array is performed by a logic circuit composed of basic cells, there are many uncertain factors such as the layout, position, and wiring length of the logic circuit until the layout design is actually completed, and it is very difficult to design the timing. Becomes Further, if the control logic circuit and the memory block are separated from each other, the access time is increased.

[Means for solving problems]

The memory circuit incorporated in the master slice type semiconductor integrated circuit of the present invention is used to change the configuration (bit × word) of the memory circuit separately from the transistor elements constituting the memory circuit, or to combine several memory circuit blocks. It has a basic cell for forming a control logic circuit of the memory circuit block. Therefore, according to the present invention, the memory circuit is controlled by using the basic cells prepared in advance in the memory circuit, and the degree of freedom in the bit / word configuration is increased. Even when configuring a memory circuit having a bit / word structure, the memory can be controlled by a logic circuit formed by basic cells in the memory.

〔Example〕

Next, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a block diagram of a memory circuit incorporated in a master slice type semiconductor integrated circuit according to an embodiment of the present invention. A basic structure is a 4-bit × 64-word static RAM (hereinafter abbreviated as S-RAM) circuit. This is an example of changing to 1 bit × 256 words. Reference numeral 1 is a 1-bit memory cell, 2 is a first memory cell array, and is composed of 64 memory cells. Similarly, 3, 4 and 5 are the second, third and fourth memory cell arrays, respectively. A row address decoder 6 and a column address decoder 7 select a desired memory cell from the memory cell arrays 2 to 5 by address input of the input group 21 of the S-RAM. Column selectors 8 to 11 select columns 2 to 5 of the memory cell array selected by the decoder 7. Reference numerals 24 and 25 are basic cell arrays composed of a plurality of basic transistors. In 25, which of the column selectors 8 to 11 is selected by the newly added address inputs 22 and 23 in order to change the S-RAM from the basic structure of 4 bits × 64 words to 1 bit × 256 words. An address decoder for determining is configured. Numerals 26 to 29 are logic circuits for controlling the connection between the output of the column selector and the sense amplifiers 13 and the write amplifiers 17 by the signal of the address decoder 25, which are constituted by using the basic cell array 24.

FIG. 2 is a block diagram of the logic circuits 26 to 29 shown in FIG. 30
Is a connection terminal with the column selector, 31 is a sense amplifier,
Reference numeral 32 is a connection terminal with the write amplifier, and 32 is a connection terminal with the output of the address decoder 25. When the potential of the connection terminal 32 is "0" level, the transfer gate is off, the potential of the connection terminal 31 is high impedance, and when the potential of the connection terminal 32 is "1" level, the transfer gate is on state. The signal applied to the potential of the connection terminal 31
Output to

FIG. 3 shows the address decoder circuit 25 of FIG. 2
2 and 23 are newly added input signal terminals. Depending on the combination, one of the output terminals 33 to 36 becomes "1" level and any one of the connected logic circuits 26 to 29 becomes conductive. State, and sense amplifier 13 and write amplifier 17
Connected to

In this way, the S-RAM block of 4 bits × 64 words can be easily changed to the S-RAM of 1 bit × 256 words by the logic circuit constituted by the basic cell arrays 24 and 25.

FIG. 4 is a block diagram of an S-RAM circuit according to another embodiment of the present invention. Reference numeral 39 is a basic cell array composed of basic transistors, which constitutes the logic circuit of FIG. 5 or 6. FIG. 7 shows an example in which two S-RAMs of FIG. 4 are used to construct a 4-bit × 128-word S-RAM. 49,50 is 4
It is a basic S-RAM block of bits × 64 words and has logic circuits 51 and 52 each constituted by a cell array 39 therein. The outputs of the logic circuits 51 and 52 are connected to the chip select terminals of the basic S-RAM block, and the logic circuits 51 and 5 are connected.
The input terminal 46 connected to the first input of 2 is used as the fifth address input, and the second input terminal of the logic circuits 51 and 52 is used as the chip select terminal 47 of the entire S-RAM of 4 bits × 128 words. Is a 4-bit x 128-word memory circuit. Here, since the control logic circuit of the logic circuits 51 and 52 is configured inside the memory circuit, the logic circuits 51 and 52
The wiring length of the output of is reduced to prevent an increase in access time of the memory circuit. Further, as compared with the case where the logic circuits 51 and 52 are formed outside the memory circuit, that is, in the gate array section, there is an advantage that the delay time of the logic circuits 51 and 52 can be predicted before the layout processing, which facilitates the timing design.

〔The invention's effect〕

As described above, according to the present invention, in a memory circuit built in a master slice type semiconductor integrated circuit, a cell array composed of basic transistors is prepared in advance in the memory in addition to the transistor elements forming the memory basic circuit. The memory configuration can be changed by the logic circuit configured by using this cell, and it can be applied to a wide range of systems. Further, even when a plurality of built-in memory circuits are combined to realize a memory circuit having different bit or word configurations, the delay time is increased by forming a control logic circuit inside the memory circuit using this memory cell array. There is an effect that the above can be prevented and the timing design of the logic circuit using the memory circuit can be facilitated.

Further, in the present invention, the configuration of the memory block prepared in advance (1 word is n bits) itself is not changed,
Of the n bits output from the memory block, a desired bit is selected and used by the second column decoder. For this purpose, the second column decoder can be configured by combining basic cells (for example, inverters and NAND cells) prepared in advance according to the purpose, depending on how many bits of n bits are used. I chose Therefore, since it is not necessary to change the bit configuration of the memory block itself made in advance, no human error occurs due to the change of the bit configuration of the memory block. Therefore, the gate array product can be shipped in a short time. Produce the effect of.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory circuit according to an embodiment of the present invention,
2 and 3 are block circuit diagrams of a memory circuit control logic circuit configured by a basic cell array arranged in the memory circuit, and FIG. 4 is a block diagram of a memory circuit according to another embodiment of the present invention. 5 and 6 are block circuit diagrams of a memory circuit controlling logic circuit composed of a basic cell array arranged in the memory circuit, and FIG. 7 is a 4-bit structure using the embodiment of FIG. FIG. 8 is a block diagram of a memory circuit having a × 128 word structure, and FIG. 8 is a block diagram of a memory circuit (4 bits × 64 words) built in a conventional master slice type semiconductor integrated circuit. 1 ... Memory cell, 2,3,4,5 ... Memory cell array, 6
...... Row address decoder, 7 …… Column address decoder, 8,9,10,11 …… Column selector, 12 …… Address buffer and other control circuit unit, 13,14,15,16 …… Sense amplifier, 17, 18,19,20 …… Write amplifier, 21 …… Address, read / write control, Chip select input terminal, 22,23 …… Fifth and sixth address input terminals, 24,25…
... basic cell, 26, 27, 28, 29 ... logic circuit composed of basic cell 24, 30 ... column selector input terminal, 31 ... output terminal of logic circuits 26 to 29, 32 ... logic circuit 26 to 29 control input terminals, 33,34,35,36 …… second column address decoder output terminals, 37,38 …… logic circuit input terminals, 3
9 …… Basic cell array, 40,41 …… Output terminals of logic circuit,
43 …… data input, 44 …… address input, 45 …… read / write control terminal, 46 …… fifth address input, 47 …… chip select terminal, 48 …… RAM output terminal, 49,50 …… 4-bit x 64-word basic block, 51,52
...... RAM block control logic circuit.

Claims (1)

[Claims] 1. A word line composed of a row address decoder, a first column address decoder, and n memory cell arrays, selected by the row address decoder and commonly connected to the n memory cell arrays, and the first and second word lines. N in response to the output of the column address decoder 1
A memory block for selecting one bit from each of the memory cell arrays and outputting n-bit information; and a second column address decoder for selecting a desired bit from the n bits output from the memory block. , The second
2. A master slice type semiconductor integrated circuit with a built-in memory circuit, characterized in that the column decoder is constructed by combining a plurality of basic cell arrays prepared in advance.