JPH0812885B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory device.

[Conventional technology]

The recent development of non-volatile semiconductor memory devices is remarkable. Among them, the capacity of ultraviolet erasable programmable memory devices (hereinafter referred to as EPROMs) and the like is increasing due to the simple cell structure. This increase in capacity has been promoted by reducing the size of each component, but recently various obstacles have occurred.

One of them is an increase in diffusion layer resistance due to shallow junction. This phenomenon will be explained using a conventional ERPROM as an example. Seventh
FIG. 8 is a sectional view of a semiconductor chip showing a conventional EPROM, and FIG. 8 is a circuit diagram of the conventional EPROM. Here, 1 is a p-type semiconductor substrate, 2a and 2b are drain regions formed of n-type diffusion layers, 3 is a source region formed of n-type diffusion layers, 4 is a first gate insulating film, and 5 is a second gate insulating film. , 6 are floating gate electrodes, 7
Is a control gate electrode, 10 is an interlayer insulating film, 11 is a contact hole, and 12 is a metal wiring.

In FIG. 8, Q _{M11 to} Q _M22 are memory transistors,
Q ₁ , Q ₂ , Q ₃ , Q ₄ are MOS transistors, X _i , X _{i + 1} are word lines, D
_i , D _{i + 1} are bit lines, Y _i , Y _{i + 1} are bit line selection signal lines, V _PP
Is a program power supply, V _P , ▲ ▼ is a program read control signal, and SA is a sense amplifier. Such a conventional
In the EPROM, the source region 3 also serves as a part of the diffusion layer wiring, and the diffusion layer wiring is connected to the ground potential metal wiring G. Therefore, the parasitic resistance of the diffusion layer wiring is mainly the parasitic source resistance R.
Acts as. However, when reading or programming the EPROM cell, the channel current flows from the bit line through the memory cell transistor and the diffusion layer wiring of the source.
At this time, if the parasitic sorts resistance R is high, the potential of the source electrode rises, and the on-current of the memory transistor is lowered and the electron channel injection efficiency is deteriorated, that is, the programming speed is deteriorated. Due to this problem, it is difficult to make the source region shallow junction, which leads to an increase in parasitic source resistance, and the diffusion layer wiring width reduction, which hinders the reduction of the cell area.

[Problems to be solved by the invention]

The conventional non-volatile semiconductor memory device described above has a drawback that the parasitic resistance of the source region increases with the reduction of the memory cell area and the programming speed decreases.

[Means for solving problems]

A nonvolatile semiconductor memory device of the present invention includes a source region and a drain region in which a second conductivity type impurity is selectively introduced into a first conductivity type semiconductor substrate, and a channel region sandwiched between the source region and the drain region. A first gate insulating film provided to cover the surface of the channel region, and a floating gate electrode provided on the first gate insulating film,
A second gate insulating film provided to cover the floating gate electrode, a control gate electrode provided on the second gate insulating film, and a metal wiring connected to the drain region, In a nonvolatile semiconductor memory element in which a source region also serves as a part of a diffusion layer wiring, the source region is formed on a sidewall of a groove having a U-shaped cross section, which is dug in the first conductivity type semiconductor substrate by anisotropic etching. That is, the formed second conductivity type impurity layer is included.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor chip showing a first embodiment of the present invention, showing the source of two nonvolatile semiconductor memory elements connected to each other.

In this embodiment, a source region 3a and a drain region 2a are formed by selectively introducing an n-type impurity into a p-type semiconductor substrate 1 made of silicon, a channel region 13a sandwiched between the source region 3a and the drain region 2a, and A first gate insulating film 4 provided on the surface of the channel region 13 a, a floating gate electrode 6 provided on the first gate insulating film 4, and a second gate insulating film provided on the floating gate electrode 6. Of the control gate electrode 7 provided on the gate insulating film 5 and the metal wiring 12 connected to the drain region 2a, and the source region 3a also serves as a part of the diffusion layer wiring. In, the source region 3a is a cross section U dug in the p-type semiconductor substrate.
It is composed of an n-type impurity layer formed on the side wall and the bottom surface of the V-shaped groove 14. Then, the edge portion of the first gate insulating film 4 and the side wall surface of the trench 14 filled with the interlayer insulating film 10 'made of silicon oxide are substantially continuous.

Another nonvolatile semiconductor device is depicted symmetrically on the right side of FIG. 1, and the source regions of these two devices are trenches.
It is connected by an n-type impurity layer 15 (actually continuous with the source regions 3a, 3b) provided on the bottom surface of the layer 14.

The advantages of this embodiment are as follows. First, since the surface area of the source region 3a is larger than that of the conventional example, the parasitic resistance is small. Therefore, efficient writing is possible. Secondly, the occupation ratio of the source region to the cell area is small (referred to the main surface of the semiconductor substrate). This advantage occurs because the side wall surface of the trench, which is the main surface of the source region, is formed substantially continuously with the edge portion of the first gate insulating film. That is, the cross-sectional area viewed from the main surface of the semiconductor substrate is small.

 Next, the manufacturing method of this embodiment will be described.

FIG. 2 is a sectional view of a semiconductor chip in an intermediate step for explaining the manufacturing method according to the first embodiment of the present invention.

Here, 8 is, for example, a 150 nm thick silicon nitride film on the control gate electrode, 7 is a control gate electrode made of, for example, a 400 nm thick polycrystalline silicon film, and 6 is a floating gate electrode, for example, a 250 nm thick polycrystalline silicon film. Film, 4 is a first gate insulating film made of silicon oxide, 5 is a second gate insulating film, 1 is a p-type semiconductor substrate made of, for example, silicon, 9
Is a patterned resist film. Here, the silicon nitride film 8, the control gate electrode 7, the first and second gate insulating films 4 and 5, and the floating gate electrode 6 are patterned such that their edges are substantially aligned by a known technique in the previous step. Has been done. The resist film 9 covers half of this gate electrode pattern and the surface of the p-type semiconductor substrate 1 which will be the drain diffusion layer. At this time, the surface of the p-type semiconductor substrate 1 sandwiched by the gate electrode pattern is exposed. Next, the p-type semiconductor substrate 1 is etched by anisotropic etching such as reactive on etching. Since the silicon nitride film 8 on the gate electrode pattern serves as a mask against this etching, a groove 14 having a side wall surface almost continuous with the edge surface of the first gate insulating film 4 is formed. After that, the resist 8 is removed, and n-type impurities are diffused on the side wall surface and the bottom surface to form in-groove diffusion layers (source regions 3a, 3b, n-type impurity layer 15). As the impurity diffusion method, various methods such as an impurity diffusion method by heat treatment in an atmosphere of POCl ₃ or the like and an impurity diffusion method from a coating film of arsenic silicate glass or the like can be used.
The drain regions 2a and 2b may be formed simultaneously with the formation of the diffusion layer in the trench or separately. In the following, an interlayer insulating film 10, a contact hole 11 and a metal wiring 12 are formed according to a usual manufacturing method to obtain the structure shown in FIG.

FIG. 3 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

The difference from the first embodiment is that the source regions 3a and 3b are not connected in the groove 14. This structure is easily formed by replacing the resist film 9 in FIG. 2 with, for example, a silicon oxide film, introducing impurities into the groove, and then anisotropically etching the p-type semiconductor substrate 1 again. In this structure, the source regions of adjacent elements can be independently used as source selection lines. This source selection line corresponds to Z _k and Z _{k + 1} shown in FIG. 4 showing the circuit diagram. Now when programming Q _M11 here word line X _i
High voltage, the source selection line Z _k is set to the installation potential, the word line X _{i + 1 is set} to the ground potential, and the source selection line Z _{k + 1} is opened. Further, a high voltage is applied to the program control signal V _P and the bit line selection signal line Y _j . Memory transistor Q than this result V _PP
Memory transistor Q _M11 current flows through _M11 as the source select line Z _k is programmed. At this time, since the source electrode of the memory transistor Q _M21 is open, no parasitic transistor current flows through the memory transistor Q _M21 . Therefore, there is no voltage drop of the drain voltage of the memory transistor Q _M11 due to the above-mentioned parasitic current, and efficient programming is possible. In this way, this structure can separate the source lines without increasing the cell area, and as a result, a cell array structure can be obtained which can prevent the parasitic transistor current during programming.

FIG. 5 is a sectional view of a semiconductor chip showing a third embodiment of the present invention.

This embodiment is an example in which the source region 3a on the groove side surface is added to the conventional source region 3c simply in order to reduce the source resistance. In this case, there is an alignment interval between the edge of the control gate and the side wall surface of the groove, and the advantage of reducing the cell area as in the first embodiment is lost.

FIG. 6 is a sectional view of a semiconductor chip showing a fourth embodiment of the present invention.

In this embodiment, the surface of the groove is covered with a silicon oxide film 17 and then buried with a polycrystalline silicon layer 16b. The drain regions are low concentration and shallow first drain regions 2c and 2d and deep second drain region 2e. , 2f, and the second drain region 2
e and 2d are formed by diffusing from the polycrystalline silicon layers 16e and 16c,
The connection with the metal wiring is made through the polycrystalline silicon layers 16e and 16c.

The first feature of this embodiment is that the polycrystalline silicon layers 16a and 16b are used for flattening the interlayer film. That is, the polycrystalline silicon layer 16b fills the groove portion, and the 16a simultaneously realizes the step reduction of the step sandwiched between the floating gate 6 and the control gate 7. The second feature is the asymmetry of the drain region. The second drain region is used as a drain electrode when programming an EPROM using this nonvolatile semiconductor memory element, while the first drain region formed with a shallow and low impurity concentration is used as a drain electrode when reading. As a result, the drain electric field during programming is strong even under the same bias conditions as before.
On the contrary, the drain electric field at the time of reading can be weakened. This is understood by a mechanism similar to that of the LDD structure MOS transistor.

As described above, the memory device using this embodiment can increase the drain electric field difference between the time of programming and the time of reading, can effectively prevent programming from being mistakenly written during reading, and can be used for a long time. The time reliability can be improved.

〔The invention's effect〕

As described above, the present invention provides the occupancy ratio of the main surface of the semiconductor substrate by providing at least one of the source region and the drain region of the MIS type nonvolatile semiconductor memory element on the sidewall surface of the groove provided in the semiconductor substrate. Even if it is small, the resistance does not increase, and the nonvolatile semiconductor memory element suitable for high integration can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip in an intermediate step for explaining a manufacturing method of the first embodiment of the present invention. FIG. 3 is a sectional view of a semiconductor chip showing a second embodiment of the present invention, FIG. 4 is a circuit diagram of an EPROM using the second embodiment,
5 and 6 are sectional views of a semiconductor chip showing the third and fourth embodiments of the present invention, FIG. 7 is a sectional view of a semiconductor chip showing a conventional example, and FIG. 8 is a conventional example. 2 is a circuit diagram of an EPROM. 1 ... p-type semiconductor substrate, 2a, 2b, 2c, 2d ... drain region, 3,3a, 3b, 3c, 3d ... source region, 4 ... first gate insulating film, 5 ... second Gate insulating film, 6 ... Floating gate electrode, 7 ... Control gate electrode, 8 ... Silicon nitride film,
9 ... Resist film, 10, 10 '... Interlayer insulating film, 11 ... Contact hole, 12 ... Metal wiring, 13a, 13b ... Channel region, 14 ... Groove, 15 ... N-type impurity layer, 16a , 16b, 16c ……
Polycrystalline silicon layer, 17 ... Silicon oxide film, D _i , D _{i + 1} …
… Bit lines, Q _{1 to} Q ₄ …… MOS transistors, Q _{M11 to} Q _M22
... Memory transistors (nonvolatile semiconductor memory elements),
R ... Parasitic resistance, X _i , X _{i + 1} ... Word line, Y _i , Y _{i + 1} ... Bit line selection signal line, Z _k , Z _{k + 1} ... Source selection line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (2)

[Claims] 1. A source region and a drain region in which a second conductivity type impurity is selectively introduced into a first conductivity type semiconductor substrate, a channel region sandwiched between the source region and the drain region, and a channel region of the channel region. A first gate insulating film provided to cover the surface, a floating gate electrode provided on the first gate insulating film, and a second gate insulating film provided to cover the floating gate electrode, Nonvolatile semiconductor memory element having a control gate electrode provided on the second gate insulating film and a metal wiring connected to the drain region, and the source region also serving as a part of a diffusion layer wiring. In the above, the source region includes a second conductivity type impurity layer formed on a sidewall of a groove having a U-shaped cross section, which is dug in the first conductivity type semiconductor substrate by anisotropic etching. Volatile SEMICONDUCTOR MEMORY element. 2. The nonvolatile semiconductor memory element according to claim 1, wherein the second conductivity type impurity layers formed on both side walls of the groove are separated at the bottom surface of the groove.