JPH08124928A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit in which the degree of freedom is enhanced in the design and a high current can be fed to the element without increasing the chip size. CONSTITUTION: A power supply wiring 7 and a ground wiring 9 are formed independently from a signal wiring 4 on a semiconductor substrate 1. The power supply wiring 7 and the ground wiring 9 are formed over the entire surface of the semiconductor substrate 1 and connected individually with elements formed thereon. Since the element can be formed at an arbitrary position on the semiconductor substrate and the contacts 10, 11 thereof with the power supply wiring 7 and the ground wiring 9 can be arranged at arbitrary positions, the position or the region for arranging the signal wiring 4 or the element is not limited. This constitution enhances the degree of freedom in the design and to realize high integration of semiconductor integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having three or more wiring layers.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, in order to supply power to various elements formed on a semiconductor substrate,
It is necessary to connect the power supply wiring and the ground wiring. For this reason,
A plurality of power supply wirings and ground wirings are extended on the surface of a semiconductor substrate, and each element is electrically connected to these power supply wirings and ground wirings by branch wirings. FIG. 5 is a diagram showing an example of a conventional semiconductor integrated circuit. 21 is a semiconductor substrate, 22 is a transistor region, 23 is a wiring region, 24 is a power supply wiring, and 25 is a ground wiring. here,
The power supply wiring 24 and the ground wiring 25 are formed in the same lowest wiring layer, while the signal wiring not shown is formed in a plurality of wiring layers including the lowest wiring layer.

[0003]

In this semiconductor integrated circuit, since the power supply wiring 24 and the ground wiring 25 are formed in the lowest wiring layer, a part of the signal wiring formed in the wiring area 23 is formed in the lowest wiring layer. In order to form an electrical connection with the transistor by forming the wiring layer, the signal wiring needs to be arranged at a position where it does not interfere with the power wiring and the ground wiring. As a result, the transistor also has the power wiring 24 and the ground wiring 25. It is necessary to form in a region that does not interfere with. Therefore, it is necessary to divide the transistor region 22 and the wiring region 23 from the region where the power supply wiring 24 and the ground wiring 25 are formed, which causes a problem that the degree of freedom in designing the semiconductor integrated circuit is reduced. .

Further, when a large current is supplied to the transistor, the power supply wiring 24 and the ground wiring 25 need to have a large line width, and the power supply wiring having a different line width depending on the type of semiconductor integrated circuit having a different supplied current, There is a problem that it is necessary to design the ground wiring, which makes the design troublesome. Further, when the line width of the power supply wiring or the ground wiring is increased due to a large current, the area of the transistor region is reduced accordingly, the degree of integration is reduced, or the chip size is required in order to secure the required area of the transistor region. Must be increased, which is an obstacle to miniaturization of the semiconductor integrated circuit.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit capable of supplying a large current to an element without increasing the chip size while improving the degree of freedom in design.

[0006]

In a semiconductor integrated circuit of the present invention, an element is formed on a semiconductor substrate, and a plurality of wiring layers are formed on the semiconductor substrate, and these wiring layers are signal wirings connected to the element. , The power supply wiring and the ground wiring, the power supply wiring and the ground wiring are formed as independent wiring layers different from the signal wiring, and these power supply wiring and the ground wiring are formed over the entire surface of the semiconductor substrate, and respectively. The wiring and the element are individually connected.

Here, the power supply wiring and the ground wiring are formed in a laminated state on the upper layer of the signal wiring, and the wiring provided on the upper layer is electrically connected to the element via the contact in the space provided on the lower layer. It

For example, in the semiconductor integrated circuit of the present invention, elements are formed over the entire surface of a semiconductor substrate, and a wiring layer forming one or more signal wirings is formed on an upper layer of the semiconductor substrate via an insulating film. A wiring layer of power supply wiring is formed over the entire surface of the wiring through an insulating film, and a wiring layer of ground wiring is formed over the entire surface of the wiring through an insulating film, and the power supply wiring is a contact penetrating the signal wiring. Is connected to the element, and the ground wiring is connected to the element by a contact penetrating the signal wiring in a space provided in a part of the power supply wiring.

[0009]

By forming the power supply wiring and the ground wiring in different wiring layers with respect to the signal wiring, even if the power supply wiring and the ground wiring are formed over the entire surface of the semiconductor substrate, the signal wiring will not interfere with the power supply wiring or the ground wiring. It can be formed in any pattern without having to, and along with this, elements such as transistors can be arranged at any position over the entire surface of the semiconductor substrate,
The degree of freedom in design is improved.

Further, since the power supply wiring and the ground wiring are formed over the entire surface of the semiconductor substrate, even when a large current is supplied to the element, the wiring standard can be changed without changing the design.
In addition, the device can be dealt with without affecting the device, and high integration of the semiconductor integrated circuit can be achieved.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an embodiment of a semiconductor integrated circuit of the present invention, FIG. 2 is a sectional view of a main part thereof, and FIG. 3 is a partially exploded perspective view showing its schematic configuration. In these figures, reference numeral 1 denotes a semiconductor substrate, and transistor regions are arranged over substantially the entire surface of this semiconductor substrate, and various transistors 2 are formed. A first interlayer insulating film 3 is formed on the semiconductor substrate 1 on which the transistor 2 is formed, and a signal wiring 4 for electrically connecting the transistors to each other is formed. The signal wiring 4 has a plurality of layers, here, the first signal wiring 4
a and the second signal wiring 4b are formed over two layers, the signal wirings 4a and 4b are connected to the transistor 2 by the contact 5, and the signal wirings 4a and 4b are electrically connected to each other. Then, the power supply wiring 7 is formed on the second interlayer insulating film 6 which is an upper layer of the signal wiring, and the ground wiring 9 is formed thereon via the third interlayer insulating film 8. The power supply wiring 7 and the ground wiring 9 are respectively connected to the semiconductor substrate 1
Has been extended over the entire surface.

The power wiring 7 is the signal wiring 4
While avoiding the above, the transistor 2 is connected through the power contact 10 provided in the first and second interlayer insulating films 3 and 6. In addition, the space 1 where the wiring is removed is part of the power supply wiring 7.
2 is provided, and a ground contact 11 for connecting the ground wiring 9 to the transistor 2 is provided in this space 12 location. The ground wiring 9 is connected to the transistor 2 by the ground contact 11 while avoiding the power wiring 7 and the signal wiring 4. At this time, the ground contact 1
An insulating separation layer 13 is provided around 1 in order to avoid a short circuit with the power supply wiring 7.

In the actual manufacturing, the ground distribution contact 11 is used when the mask data for the power supply wiring is created.
The ground contact 11 can be formed separately from the power supply wiring 7 by removing the portion of the insulating separation layer 13 between and from the power supply wiring mask data. Further, in this case, the power supply contact 10 and the ground contact 11 are formed in advance for the transistor 2, and when the power supply wiring 7 and the ground wiring 9 are formed, each wiring is connected via each contact 10, 11. Are manufactured so as to connect a part of each of them to the transistor 2.

In this way, by forming the power supply wiring 7 and the ground wiring 9 in different wiring layers with respect to the signal wiring 4, the signal wiring 4 has a pattern for avoiding interference between the power wiring 7 and the ground wiring 9. It can be formed in any pattern without being restricted by the above, and accordingly, the transistor 2 can be arranged at any position over the entire surface of the semiconductor substrate 1, and the degree of freedom in designing the semiconductor integrated circuit is increased. be able to.

Further, since the power supply wiring 7 and the ground wiring 9 are formed over the entire surface of the semiconductor substrate 1, even when a large current is supplied to the transistor 1, the wiring width, length, etc. do not need to be changed and the design is unchanged. In this state, semiconductor integrated circuits of various standards can be dealt with. Further, at this time, since it does not affect the region where the transistors are formed, it is possible to arrange the transistors 2 at a high density,
As a result, high integration is possible. Further, in this embodiment, since the ground wiring 9 is formed in the uppermost layer, it is possible to obtain the ground shield effect for the transistor 2 and the signal wiring 4.

Here, in the present invention, as shown in FIG. 4, the contacts 10 and 11 of the power supply wiring 7 and the ground wiring 9 are respectively connected to a part of the signal wiring 4, and the signal wiring 4 and its contact 5 are interposed. A part of the signal wiring 4 may be configured as a power supply wiring or a ground wiring by connecting the signal wiring 4 to the transistor 2. In this configuration, when the signal wiring 4 has a multilayer structure, the contacts 10 and 11 of the power supply wiring 7 and the ground wiring 9 are connected.
Of the ground contact, in particular, the ground contact 11 for connecting the uppermost layer ground wiring 9 and the transistor 2 is prevented from becoming deep, and the connection failure in the ground contact 11 is eliminated.
And avoiding difficulties in manufacturing.

It is also possible to form the power wiring in the uppermost wiring layer and provide the ground wiring in the lower layer. Further, it goes without saying that the power supply wiring and the ground wiring are not limited to those in which the conductive film is present on the entire surface thereof, and that each wiring may be formed in a mesh shape or a grid shape.

[0018]

As described above, according to the present invention, the power supply wiring and the ground wiring, which are electrically connected to the element formed on the semiconductor substrate, are formed as independent wiring layers different from the signal wiring, and Since the power supply wiring and the ground wiring are formed over the entire surface of the semiconductor substrate and the respective wirings are individually connected to the element, the element can be formed at any position on the semiconductor substrate, and the power supply wiring and the ground can be formed. Since the contact between the wiring and the element can be arranged at any position on the semiconductor substrate, there is no restriction on the position or area where the signal wiring or the element is arranged, and the degree of freedom in design can be increased. Further, the elements can be arranged over the entire surface of the semiconductor substrate, and high integration of the semiconductor integrated circuit can be achieved. Furthermore, even when a large current is supplied to the element, it is not necessary to change the design of the power supply wiring and the ground wiring, and this does not limit the area where the element is arranged.

Further, in the present invention, the power supply wiring and the ground wiring are formed in a laminated state on the upper layer of the signal wiring, and the wiring provided on the upper layer is electrically connected to the element through the contact hole in the space provided on the lower layer. Is configured as
Even if the power supply wiring and the ground wiring are formed over the entire surface of the semiconductor substrate, both wiring layers do not interfere with each other.

Further, in the semiconductor integrated circuit of the present invention, a wiring layer constituting one or more signal wirings is formed on the upper layer of the semiconductor substrate via an insulating film, and the insulating film is entirely formed on the upper layer of this signal wiring. Since the wiring layer of the power wiring is formed and the wiring layer of the ground wiring is formed over the entire surface with the insulating film in between, the signal wiring can be grounded shielded by the ground wiring and the electrical characteristics can be stabilized. Becomes

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is an enlarged sectional view of a main part of FIG.

FIG. 3 is a schematic perspective view in which a part of FIG. 1 is disassembled.

FIG. 4 is an enlarged sectional view of a main part of another embodiment of the present invention.

FIG. 5 is a plan view of an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 semiconductor substrate 2 transistor (element) 4 signal wiring 5 contact 7 power wiring 9 ground wiring 10 power contact 11 ground contact

Claims (3)

[Claims] 1. An element is formed on a semiconductor substrate, and a plurality of wiring layers are formed on the semiconductor substrate, and these wiring layers include signal wiring, power supply wiring, and ground wiring connected to the element. In the semiconductor integrated circuit, the power supply wiring and the ground wiring are formed as independent wiring layers different from the signal wiring, and the power supply wiring and the ground wiring are formed over the entire surface of the semiconductor substrate, and the respective wiring and the wiring are formed. A semiconductor integrated circuit characterized by being individually connected to an element. 2. The semiconductor according to claim 1, wherein the power supply wiring and the ground wiring are formed in a stacked state on an upper layer of the signal wiring, and the wiring provided on the upper layer is electrically connected to the element through a contact in a space provided on the lower layer. Integrated circuit. 3. An element is formed on the entire surface of a semiconductor substrate, and a wiring layer constituting one or more signal wirings is formed on an upper layer of the semiconductor substrate via an insulating film, and an insulating film is formed on the entire upper layer of the signal wiring. A wiring layer of a power wiring is formed via, a wiring layer of a ground wiring is formed over the entire surface of the wiring layer via an insulating film, the power wiring is connected to the element by a contact penetrating the signal wiring,
The semiconductor integrated circuit, wherein the ground wiring is connected to the element by a contact penetrating the signal wiring in a space provided in a part of the power wiring.