JPH08124926A - Formation of wiring - Google Patents
Formation of wiringInfo
- Publication number
- JPH08124926A JPH08124926A JP25507494A JP25507494A JPH08124926A JP H08124926 A JPH08124926 A JP H08124926A JP 25507494 A JP25507494 A JP 25507494A JP 25507494 A JP25507494 A JP 25507494A JP H08124926 A JPH08124926 A JP H08124926A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- layer
- coating layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000001459 lithography Methods 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 3
- 239000011247 coating layer Substances 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 31
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000010949 copper Substances 0.000 abstract description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052802 copper Inorganic materials 0.000 abstract description 24
- 229910045601 alloy Inorganic materials 0.000 abstract description 10
- 239000000956 alloy Substances 0.000 abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 7
- 239000002344 surface layer Substances 0.000 abstract description 5
- 229910017945 Cu—Ti Inorganic materials 0.000 abstract description 4
- 229910021529 ammonia Inorganic materials 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000005368 silicate glass Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 5
- 239000011342 resin composition Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005121 nitriding Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- XLLIQLLCWZCATF-UHFFFAOYSA-N 2-methoxyethyl acetate Chemical compound COCCOC(C)=O XLLIQLLCWZCATF-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- RDOXTESZEPMUJZ-UHFFFAOYSA-N anisole Chemical compound COC1=CC=CC=C1 RDOXTESZEPMUJZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- FAYMLNNRGCYLSR-UHFFFAOYSA-M triphenylsulfonium triflate Chemical compound [O-]S(=O)(=O)C(F)(F)F.C1=CC=CC=C1[S+](C=1C=CC=CC=1)C1=CC=CC=C1 FAYMLNNRGCYLSR-UHFFFAOYSA-M 0.000 description 2
- 239000008096 xylene Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- UZKWTJUDCOPSNM-UHFFFAOYSA-N methoxybenzene Substances CCCCOC=C UZKWTJUDCOPSNM-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- -1 poly (di-t-butoxysiloxane) Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000276 potassium ferrocyanide Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- ZFAYZXMSTVMBLX-UHFFFAOYSA-J silicon(4+);tetrachloride Chemical compound [Si+4].[Cl-].[Cl-].[Cl-].[Cl-] ZFAYZXMSTVMBLX-UHFFFAOYSA-J 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- XOGGUFAVLNCTRS-UHFFFAOYSA-N tetrapotassium;iron(2+);hexacyanide Chemical compound [K+].[K+].[K+].[K+].[Fe+2].N#[C-].N#[C-].N#[C-].N#[C-].N#[C-].N#[C-] XOGGUFAVLNCTRS-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の製造等
で用いられる配線を形成する方法に関し、特に微細配線
の形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wiring used in the manufacture of semiconductor devices and the like, and more particularly to a method for forming fine wiring.
【０００２】[0002]
【従来の技術】半導体装置の高速動作および高集積化を
図るために、銅を用いた配線が検討されている。アルミ
ニウム配線などに比べ配線抵抗の低減が図れるからであ
る。しかし銅を用いる場合、銅が低温でシリサイド化し
易いこと、および、シリサイドや酸化膜中を容易に拡散
することから、被覆層によりこれらを防止する対策が必
要とされる。そこで、特開平２−２６０４２２号公報
（以下、文献Ｉという。）に開示の技術では、酸化膜上
にＴｉＮ膜、Ｃｕ膜およびＴｉＮ膜を順に積層し、次い
で、この積層膜表面上に所定のエッチングマスクを形成
し、そして、この積層膜を塩素、四塩化ケイ層、窒素お
よびアンモニアの混合ガスでかつ高温でエッチングして
いる。このエッチングにおいて非エッチング部分の側壁
にシリコン酸窒化膜が形成される。このため非エッチン
グ部分のＣｕ膜はその上下をＴｉＮよりなる被覆層によ
り覆われ、その側壁をシリコン酸窒化膜により覆われ
る。また、文献II（エム アール エス フ゛レティン(MRS BULLETIN),J
UNE 1993)には、銅とクロム、チタンまたはニオブとの
合金をパターニングした後にその表面をアンモニアによ
り窒化して、表面がクロム、チタンまたはニオブの窒化
膜で被覆された銅パターンを自己整合的に形成する技術
が開示されている。2. Description of the Related Art Wiring using copper has been studied for high-speed operation and high integration of semiconductor devices. This is because wiring resistance can be reduced as compared with aluminum wiring and the like. However, when copper is used, copper is likely to be silicidized at a low temperature, and since it easily diffuses in a silicide or an oxide film, it is necessary to take measures to prevent these by the coating layer. Therefore, in the technique disclosed in JP-A-2-260422 (hereinafter referred to as Document I), a TiN film, a Cu film, and a TiN film are sequentially stacked on an oxide film, and then a predetermined film is formed on the surface of the stacked film. An etching mask is formed, and this laminated film is etched with a mixed gas of chlorine, a tetrachloride silicon layer, nitrogen and ammonia and at a high temperature. In this etching, a silicon oxynitride film is formed on the side wall of the non-etched portion. For this reason, the Cu film in the non-etched portion is covered with a coating layer made of TiN on the upper and lower sides thereof, and its sidewall is covered with a silicon oxynitride film. In addition, Reference II (MRS BULLETIN, J
(UNE 1993), after patterning an alloy of copper and chromium, titanium or niobium, the surface of the alloy is nitrided with ammonia to self-align a copper pattern whose surface is coated with a nitride film of chromium, titanium or niobium. Techniques for forming are disclosed.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上述の
各技術には下記のような問題点が内在していると考え
る。However, it is considered that the above-mentioned respective techniques have the following problems inherent therein.
【０００４】まず、文献Ｉに開示の技術の場合、非エッ
チング部分の側壁に形成されるシリコン酸窒化膜の組成
は不定比である。つまり、非エッチング部分の側壁に形
成されるシリコン酸窒化膜からなる被覆層の組成は、下
地基板の種類やエッチング条件やパターン密度などの、
エッチングに関係した条件によって異なってくると考え
るのが妥当であり不定比となると考えられる。このた
め、形成されるシリコン酸窒化膜の、Ｃｕ配線に対する
被覆層（バリア層）としての性能は、必ずしも保証され
ているものではない。また、積層膜上にエッチングマス
クを形成して積層膜をエッチングするので、工程が煩雑
である。First, in the case of the technique disclosed in Document I, the composition of the silicon oxynitride film formed on the sidewall of the non-etched portion is nonstoichiometric. In other words, the composition of the coating layer formed of the silicon oxynitride film formed on the sidewall of the non-etched portion depends on the type of the base substrate, the etching conditions, the pattern density, etc.
It is reasonable to think that it will differ depending on the conditions related to etching, and it is considered that a non-stoichiometric ratio will result. Therefore, the performance of the formed silicon oxynitride film as a coating layer (barrier layer) for Cu wiring is not always guaranteed. Further, since the etching mask is formed on the laminated film to etch the laminated film, the process is complicated.
【０００５】また、文献IIに開示の技術の場合、合金を
用いるため銅がもっている低抵抗という利点を減じてし
まう。Further, in the case of the technique disclosed in Document II, since an alloy is used, the advantage of copper having low resistance is reduced.
【０００６】[0006]
【課題を解決するための手段】そこで、この発明の配線
の形成方法によれば、以下の（ａ）〜（ｄ）の工程を具
えたことを特徴とする。Therefore, the wiring forming method of the present invention is characterized by including the following steps (a) to (d).
【０００７】（ａ）配線を形成したい下地上に感光性Ｓ
ＯＧ（スピンオングラス）の膜を形成する工程。(A) Photosensitive S on the substrate on which wiring is to be formed
A step of forming a film of OG (spin on glass).
【０００８】（ｂ）該ＳＯＧの膜に形成したい配線パタ
ーンに対応した溝をリソグラフィにより形成する工程。(B) A step of forming a groove corresponding to a wiring pattern to be formed on the SOG film by lithography.
【０００９】（ｃ）該溝の形成が済んだ試料上にバリア
性および導電性を有した第１の被覆層と、配線主材料か
らなる層（以下、「配線主材層」ともいう。）と、バリ
ア性および導電性を有した第２の被覆層とをこの順にか
つこれら層が前記溝を埋めるよう形成する工程。(C) A first coating layer having a barrier property and conductivity and a layer made of a wiring main material (hereinafter, also referred to as "wiring main material layer") on the sample on which the groove has been formed. And a second coating layer having a barrier property and conductivity, in this order and so that these layers fill the groove.
【００１０】（ｄ）前記形成された第２の被覆層、配線
主材層および第１の被覆層を、前記溝周囲のＳＯＧの膜
の表面が露出するまで除去する工程。(D) A step of removing the formed second coating layer, wiring main material layer and first coating layer until the surface of the SOG film around the groove is exposed.
【００１１】この発明の実施に当たり、前記溝の形成が
済んだ後であって前記第１の被覆層を形成する前に、試
料上に化学気相成長によりケイ酸ガラス膜を形成する工
程をさらに設けても良い。このケイ酸ガラス膜は、配線
間の絶縁膜部分の耐湿性向上に寄与する。なお、化学気
相成長によるケイ酸ガラス膜を用いる場合であって、溝
の底部分の下地と配線とを接続したい場合は、このケイ
酸ガラス膜の溝底に当たる部分を除去する工程を設け
る。In carrying out the present invention, a step of forming a silicate glass film on the sample by chemical vapor deposition after the formation of the groove and before forming the first coating layer is further performed. It may be provided. This silicate glass film contributes to improving the moisture resistance of the insulating film portion between the wirings. When a silicate glass film formed by chemical vapor deposition is used and it is desired to connect the base of the bottom part of the groove to the wiring, a step of removing the part of the silicate glass film corresponding to the groove bottom is provided.
【００１２】なお、この発明の配線の形成方法は、種々
の材料から成る配線の形成に利用できる。特に、低温で
シリサイド化し易くかつシリサイドや酸化膜中を容易に
拡散し易い材料から成る配線、例えば銅の配線を形成す
る場合などはこの発明を適用して特に好適である。その
場合、前記配線主材料を銅とし、前記第１および第２の
被覆層を銅および高融点金属の合金層とするのが好適で
ある。ただし、第１および第２被覆層は、設計に応じ、
同じ組成でも良く、異なる組成であっても良い。異なる
組成とは、具体的には、第１の被覆層と第２の被覆層と
を、それぞれ異なる種類の高融点金属と銅との合金で構
成する場合、或は、第１の被覆層と第２の被覆層とを、
それぞれ同一の高融点金属と銅との合金で構成するが組
成比が異なる場合などが挙げられる。The wiring forming method of the present invention can be used for forming wiring made of various materials. In particular, the present invention is particularly applicable to the case of forming a wiring made of a material that is easily silicified at a low temperature and easily diffused in a silicide or an oxide film, for example, a copper wiring. In that case, it is preferable that the wiring main material is copper and the first and second coating layers are alloy layers of copper and a refractory metal. However, the first and second coating layers are
The composition may be the same or different. The different composition means, specifically, when the first coating layer and the second coating layer are made of alloys of different kinds of refractory metals and copper, respectively, or the first coating layer and the second coating layer are different from each other. A second coating layer,
For example, the alloys are composed of the same refractory metal and copper, but have different composition ratios.
【００１３】[0013]
【作用】この発明の構成によれば、下地上に感光性ＳＯ
Ｇ（スピンオングラス）の膜を形成し、これに配線パタ
ーンに対応した溝をリソグラフィにより形成する。次
に、この溝の形成が済んだ試料上に第１の被覆層、配線
主材層および第２の被覆層を形成する。次に、第１の被
覆層、配線主材層および第２の被覆層の溝内以外の部分
が除去される。このため、配線間の絶縁層および配線を
リソグラフィおよび所定の除去工程のみで簡易に形成出
来、しかも、各配線の底面、側面および上面をバリア性
能が保証されたかつ配線の一部をも構成する被覆層で覆
うことができる。また、配線の主な部分は配線主材料そ
のもので（例えば銅そのもの）で構成出来る。また、第
１および第２の被覆層がバリア層としてのみでなく配線
の一部をも構成するものであるので、微細配線の配線抵
抗低減に有利である。According to the structure of the present invention, the photosensitive SO is formed on the substrate.
A G (spin on glass) film is formed, and a groove corresponding to the wiring pattern is formed in the film by lithography. Next, a first coating layer, a wiring main material layer, and a second coating layer are formed on the sample on which the groove has been formed. Next, the portions of the first coating layer, the wiring main material layer, and the second coating layer other than the inside of the groove are removed. Therefore, the insulating layer between the wirings and the wirings can be easily formed only by the lithography and a predetermined removal process, and the bottom surface, side surface, and upper surface of each wiring are guaranteed to have barrier performance and also constitute a part of the wiring. It can be covered with a coating layer. Further, the main part of the wiring can be composed of the wiring main material itself (for example, copper itself). Further, since the first and second covering layers form not only the barrier layer but also a part of the wiring, it is advantageous for reducing the wiring resistance of the fine wiring.
【００１４】[0014]
【実施例】以下、図面を参照してこの発明の配線の形成
方法の実施例について説明する。なお、説明に用いる各
図はこの発明を理解出来る程度に各構成成分の形状、寸
法および配置関係を概略的に示してあるにすぎない。ま
た、以下の説明中で述べる使用材料、処理方法、成膜方
法および、膜厚、温度、時間、材料の使用量などの数値
的条件は、この発明の範囲内の一例にすぎない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the wiring forming method of the present invention will be described below with reference to the drawings. It should be noted that each of the drawings used for the description only schematically shows the shape, size, and arrangement relationship of each component so that the present invention can be understood. Further, the materials used, the processing method, the film forming method, and the numerical conditions such as the film thickness, the temperature, the time, and the amount of the material used, which will be described in the following description, are merely examples within the scope of the present invention.
【００１５】１．第１実施例 図１および図２はこの発明の配線の形成方法の第１実施
例の説明に供する工程図である。いずれの図も、下地の
配線が形成される部分を、配線が延在する方向と直交す
る方向に沿って切った断面図により示した工程図であ
る。1. First Embodiment FIGS. 1 and 2 are process diagrams for explaining a first embodiment of the wiring forming method of the present invention. Each drawing is a process diagram showing a cross-sectional view of a portion where a base wiring is formed, taken along a direction orthogonal to a direction in which the wiring extends.
【００１６】配線を形成したい下地１１として、この実
施例では、多数の半導体素子（図示せず）が形成されて
いる半導体ウエハ例えばシリコンウエハを用意する。In this embodiment, a semiconductor wafer having a large number of semiconductor elements (not shown) formed thereon, such as a silicon wafer, is prepared as the base 11 on which wiring is to be formed.
【００１７】この下地１１上に感光性ＳＯＧ（スピンオ
ングラス）の膜１３を形成する（図１（Ａ））。このた
めここでは、感光性ＳＯＧとして、この出願の出願人に
係る特開平５−２１６２３７号公報に開示のネガ型の放
射線感応性樹脂組成物を用いる。具体的には、ポリ（ジ
−ｔ−ブトキシシロキサン）０．５ｇと酸発生剤として
のトリフェニルスルホニウムトリフルオロメタンスルホ
ナート５０ｍｇとを溶剤としての２−メトキシ酢酸エチ
ル４ｍｌに溶解して構成した放射線感応性樹脂組成物を
用いる。そしてこの放射線感応性樹脂組成物の厚さ１．
２μｍの膜を下地１１上に回転塗布法により形成する。A photosensitive SOG (spin on glass) film 13 is formed on the base 11 (FIG. 1A). Therefore, here, as the photosensitive SOG, the negative-type radiation-sensitive resin composition disclosed in Japanese Patent Application Laid-Open No. 5-216237 filed by the applicant of the present application is used. Specifically, 0.5 g of poly (di-t-butoxysiloxane) and 50 mg of triphenylsulfonium trifluoromethanesulfonate as an acid generator were dissolved in 4 ml of 2-methoxyethyl acetate as a solvent to prepare a radiation-sensitive composition. A resin composition is used. The thickness of this radiation-sensitive resin composition is 1.
A 2 μm film is formed on the underlayer 11 by spin coating.
【００１８】次に、このＳＯＧの膜１３に、形成したい
配線パターンに対応した溝１５を、リソグラフィにより
形成する（図１（Ｂ））。このためここでは、先ず、Ｓ
ＯＧの膜（上記放射線感応性樹脂組成物の膜）１３に対
し、ＫｒＦエキシマステッパ（ＮＡ０．３５，１／５縮
小ステッパ）を用いて露光量１０ｍＪ／ｃｍ2 の条件で
選択的に露光する。次に、この露光済みの試料を１００
℃の温度で２分間ベークする。次に、この試料をアニソ
ールで現像し、次いで、キシレンでリンスし、次いで、
２００℃の温度で１０分間のポストベークを行なう。こ
れにより、ＳＯＧの膜１３に、深さ０．７μｍでかつ最
少線幅０．５μｍの溝１５を形成した。なお、ＳＯＧの
膜１３はこのリソグラフィ工程を経るとケイ酸系無機ガ
ラスとなる。Next, a groove 15 corresponding to a wiring pattern to be formed is formed in the SOG film 13 by lithography (FIG. 1B). Therefore, here, first, S
The OG film (film of the radiation-sensitive resin composition) 13 is selectively exposed using a KrF excimer stepper (NA 0.35, 1/5 reduction stepper) under the condition of an exposure amount of 10 mJ / cm 2 . Next, 100
Bake at a temperature of ° C for 2 minutes. The sample was then developed with anisole, then rinsed with xylene, then
Post bake at a temperature of 200 ° C. for 10 minutes. As a result, the groove 15 having a depth of 0.7 μm and a minimum line width of 0.5 μm was formed in the SOG film 13. The SOG film 13 becomes a silicate-based inorganic glass after this lithography process.
【００１９】次に、溝１５の形成が済んだ試料上にバリ
ア性および導電性を有した第１の被覆層１７と、配線主
材料からなる層１９（配線主材層１９）と、バリア性お
よび導電性を有した第２の被覆層２１とをこの順にかつ
これら層１７、１９、２１が前記溝１５を埋めるよう形
成する（図１（Ｃ）、図２（Ａ））。具体的は、この実
施例では、先ず、第１の被覆層１７として、反応性スパ
ッタリング法により膜厚が０．１μｍのＴｉＮ膜をコン
フォーマルに（下地形状に沿って均一な膜厚に）形成す
る（図１（Ｃ））。次に、配線主材層１９として、基板
にバイアスを印加したスパッタリング法により、膜厚
０．４μｍの銅（Ｃｕ）の膜を形成する。次に、第２の
被覆層２１として、上記銅の膜に連続して同様なスパッ
タリング法により膜厚０．４μｍのＣｕ−Ｔｉ合金膜
（Ｔｉを１０重量％含むもの）を形成する。ただし、こ
の実施例の場合の第２の被覆層２１は後の窒化処理によ
り本来の第２被覆層になる（詳細は後述する。）。Next, a first coating layer 17 having a barrier property and conductivity, a layer 19 made of a wiring main material (wiring main material layer 19), and a barrier property are formed on the sample on which the groove 15 has been formed. Then, a second coating layer 21 having conductivity is formed in this order and these layers 17, 19 and 21 fill the groove 15 (FIG. 1 (C), FIG. 2 (A)). Specifically, in this embodiment, first, as the first coating layer 17, a TiN film having a film thickness of 0.1 μm is conformally formed (having a uniform film thickness along the underlying shape) by a reactive sputtering method. (FIG. 1 (C)). Next, as the wiring main material layer 19, a copper (Cu) film having a film thickness of 0.4 μm is formed by a sputtering method in which a bias is applied to the substrate. Next, as the second coating layer 21, a Cu—Ti alloy film (containing 10% by weight of Ti) having a film thickness of 0.4 μm is continuously formed on the copper film by the same sputtering method. However, in the case of this embodiment, the second coating layer 21 becomes the original second coating layer by the subsequent nitriding treatment (details will be described later).
【００２０】次に、これら形成された第２の被覆層２
１、配線主材層１９および第１の被覆層１７を、溝１５
の周囲のＳＯＧの膜の表面が露出するまで除去する（図
２（Ｂ））。ここでは、この除去を、フェロシアン化カ
リウムを添加したシリカゲルのスラリー（ｐＨは６．５
に調整してあるもの）を用いた化学的機械的研磨法（Ｃ
ＭＰ法）により行なう。Next, the formed second coating layer 2 is formed.
1. The wiring main material layer 19 and the first coating layer 17 are provided in the groove 15
Is removed until the surface of the SOG film around the film is exposed (FIG. 2B). Here, this removal is performed by using a slurry of silica gel to which potassium ferrocyanide is added (pH is 6.5).
Chemical mechanical polishing method (C
MP method).
【００２１】次に、この実施例ではこの試料をアニール
炉に入れる。そして、このアニール炉にアンモニアガス
を供給しながら炉内温度を１００℃／分の割合で上昇さ
せ炉内温度が５５０℃に到達したところで１時間保持し
て第２の被覆層２１の表層を窒化し、この表層に自己整
合的にＴｉＮ膜２１ａ（キャップ層２１ａ）を形成す
る。これにより、配線主材層（Ｃｕ層）１９の上面もＴ
ｉＮ膜により被覆される。Next, in this embodiment, this sample is placed in an annealing furnace. Then, while supplying ammonia gas to this annealing furnace, the temperature inside the furnace is increased at a rate of 100 ° C./min, and when the temperature inside the furnace reaches 550 ° C., it is held for 1 hour to nitride the surface layer of the second coating layer 21. Then, a TiN film 21a (cap layer 21a) is formed on this surface layer in a self-aligning manner. As a result, the upper surface of the wiring main material layer (Cu layer) 19 also has T
Covered by iN film.
【００２２】次に、図示せずも試料上全面にＰＥ−ＴＥ
ＯＳ膜（plasma-ehanced TEOS(tetraethyl orthosilica
te) 膜）を表面保護膜として形成する。Next, although not shown, PE-TE was formed on the entire surface of the sample.
OS film (plasma-ehanced TEOS (tetraethyl orthosilica
te) film) is formed as a surface protective film.
【００２３】この後、さらに多層の配線を形成する場合
なら、図１（Ａ）〜図２（Ｃ）の工程を必要に応じ繰り
返す。After that, if more wirings are to be formed, the steps of FIGS. 1A to 2C are repeated as necessary.
【００２４】この第１実施例の説明から理解出来るよう
に、この発明によれば、微細な銅配線が、銅をエッチン
グ加工することなく、ＳＯＧ膜を加工することおよび所
定膜を除去（研磨）することにより形成出来る。このた
め、たとえばエッチングマスクを形成しこれをマスクと
して用いて銅を配線パターン形状に加工する場合（例え
ば文献Ｉ）に比べ工程の簡略化が図れる。また、Ｃｕか
ら成る主配線材層をバリア層としての性能が保証された
被覆層で被覆した配線構造が得られるので、銅本来の性
質を生かした配線が得られる。また、この第１実施例に
よれば、ＣＭＰ法および窒化処理により銅配線上面に自
己整合的に被覆層を形成出来る。As can be understood from the description of the first embodiment, according to the present invention, the fine copper wiring processes the SOG film and removes the predetermined film (polishing) without etching the copper. Can be formed by Therefore, for example, the process can be simplified as compared with the case where an etching mask is formed and copper is processed into a wiring pattern shape using the etching mask (for example, Document I). Further, since the wiring structure in which the main wiring material layer made of Cu is covered with the covering layer whose performance as the barrier layer is guaranteed, the wiring that makes the best use of the original properties of copper can be obtained. Further, according to the first embodiment, the coating layer can be formed in a self-aligned manner on the upper surface of the copper wiring by the CMP method and the nitriding treatment.
【００２５】２．第２実施例 感光性ＳＯＧとして、第１実施例で用いた感光性樹脂組
成物の代わりに、アライドシグナル社製のＡｃｃｕｇｌ
ａｓｓとトリフェニルスルホニウムトリフラレートとで
構成したネガ型の感光性ＳＯＧを用いる。そして、この
感光性ＳＯＧの膜を下地に回転塗布法により形成する。
次に、この膜に対し、ＫｒＦエキシマステッパ（ＮＡ
０．３５，１／５縮小ステッパ）を用いて露光量２０ｍ
Ｊ／ｃｍ2の条件で選択的に露光する。次に、この露光
済みの試料を１００℃の温度で２分間ベークする。次
に、この試料をＭＩＢＫ（メチルイソブチルケトン）で
現像し、次いで、キシレンでリンスし、次いで、３００
℃の温度で１０分間のポストベークを行なう。これによ
り、この実施例では、ＳＯＧの膜に深さ１．４μｍでか
つ最少線幅１．０μｍの溝を形成した。2. Second Example As a photosensitive SOG, instead of the photosensitive resin composition used in the first example, Accugl manufactured by Allied Signal Co., Ltd.
A negative photosensitive SOG composed of ass and triphenylsulfonium triflate is used. Then, this photosensitive SOG film is formed on the base by spin coating.
Next, a KrF excimer stepper (NA
0.35, 1/5 reduction stepper) using 20m exposure
Selectively expose under the condition of J / cm 2 . Then, the exposed sample is baked at a temperature of 100 ° C. for 2 minutes. The sample is then developed with MIBK (methyl isobutyl ketone), then rinsed with xylene and then 300
Post bake for 10 minutes at a temperature of ° C. As a result, in this example, a groove having a depth of 1.4 μm and a minimum line width of 1.0 μm was formed in the SOG film.
【００２６】次に、第１実施例と同様の手順で、第１の
被覆層、配線主材層および第２の被覆層の形成と、これ
らのＣＭＰ法による研磨と、第２の被覆層の窒化処理
と、表面保護膜としてのＰＥ−ＴＥＯＳ膜の形成とをそ
れぞれ行なう。ただし、この第２実施例では、配線主材
層（Ｃｕ層）の厚みおよび第２の被覆層（Ｃｕ−Ｔｉ合
金膜）の厚みは、それぞれ１μｍとしている。これによ
り所望の銅の配線が得られた。Next, in the same procedure as in the first embodiment, formation of the first coating layer, the wiring main material layer and the second coating layer, polishing of these by the CMP method, and formation of the second coating layer. The nitriding treatment and the formation of the PE-TEOS film as the surface protection film are performed. However, in the second embodiment, the thickness of the wiring main material layer (Cu layer) and the thickness of the second coating layer (Cu-Ti alloy film) are each 1 μm. This provided the desired copper wiring.
【００２７】この第２実施例から理解出来るように、市
販のシリコーン系材料と酸発生剤とで構成した感光性Ｓ
ＯＧを用いた場合にも、第１実施例と同様な効果が得ら
れることが分かる。As can be understood from this second embodiment, a photosensitive S composed of a commercially available silicone material and an acid generator is used.
It can be seen that even when OG is used, the same effect as in the first embodiment can be obtained.
【００２８】３．第３実施例 ＳＯＧと第１の被覆層との間に化学気相成長によるケイ
酸ガラス膜を介在させる例（第３実施例）を説明する。
この説明を図３および図４を参照して説明する。なお、
図３および図４は、図１および図２と同様な表記方法に
より示した工程図である。3. Third Example An example (third example) in which a silicate glass film formed by chemical vapor deposition is interposed between the SOG and the first coating layer will be described.
This description will be described with reference to FIGS. 3 and 4. In addition,
3 and 4 are process diagrams shown by the same notation method as in FIGS. 1 and 2.
【００２９】配線を形成したい下地１１上に第１実施例
と同様な手順で感光性ＳＯＧの膜１３を形成する（図３
（Ａ））。次に、このＳＯＧの膜１３に、第１実施例と
同様な手順で、形成したい配線パターンに対応した溝１
５を形成する。ただし、溝１５の形成に当たって、この
第３実施例ではこれに限られないが、ＰＥ−ＴＥＯＳ膜
２３（後に説明する。）の形成が済んだ状態において深
さ０．９μｍで最少線幅１．０μｍの溝が形成されるよ
うに、ＳＯＧの膜１３に対しリソグラフィを実施してい
る。次に、この第３実施例では、溝１５形成済みの試料
上に、化学気相成長によるケイ酸ガラス膜としてＰＥ−
ＴＥＯＳ膜２３を、ここでは０．２μｍの膜厚に形成す
る（図３（Ｂ））。A photosensitive SOG film 13 is formed on the base 11 on which wiring is desired to be formed in the same procedure as in the first embodiment (FIG. 3).
(A)). Next, the groove 1 corresponding to the wiring pattern to be formed is formed on the SOG film 13 by the same procedure as in the first embodiment.
5 is formed. However, the formation of the groove 15 is not limited to this in the third embodiment, but the PE-TEOS film 23 (described later) is formed in a state where the depth is 0.9 μm and the minimum line width is 1. Lithography is performed on the SOG film 13 so that a groove of 0 μm is formed. Next, in this third embodiment, PE-as a silicate glass film formed by chemical vapor deposition on the sample in which the groove 15 has been formed.
The TEOS film 23 is formed here to a film thickness of 0.2 μm (FIG. 3B).
【００３０】次に、溝１５の底部分のＰＥ−ＴＥＯＳ膜
２３を異方性エッチング技術により除去する（図３
（Ｃ））。ただし、配線が溝１５の底側の下地に接しな
くて良いものであったり接しなくても良い部分に当たる
場合は、この異方性エッチングは不要である。Next, the PE-TEOS film 23 at the bottom of the groove 15 is removed by the anisotropic etching technique (FIG. 3).
(C)). However, this anisotropic etching is not necessary when the wiring hits the bottom side of the groove 15 that does not need to come into contact with the underlying layer or does not have to come into contact with the underlying layer.
【００３１】次に、この試料上に、第１実施例同様な手
順および同じ材料により、第１の被覆層１７と、配線主
材層１９と、第２の被覆層２１とをこの順にかつこれら
層１７、１９、２１が前記溝１５を埋めるよう形成する
（図４（Ａ））。さらに、第１実施例と同様な手順で、
層１７、１９、２１のＣＭＰ法による除去（研磨）処理
をし（図４（Ｂ））、さらに第２の被覆層２１の窒化処
理をし（図４（Ｃ））、さらに表面保護膜であるＰＥ−
ＴＥＯＳ膜（図示せず）の形成を行なう。Next, a first coating layer 17, a wiring main material layer 19, and a second coating layer 21 are formed on this sample in this order and in the same procedure and using the same materials. Layers 17, 19 and 21 are formed so as to fill the groove 15 (FIG. 4A). Further, in the same procedure as in the first embodiment,
The layers 17, 19 and 21 are removed (polished) by the CMP method (FIG. 4B), and the second coating layer 21 is nitrided (FIG. 4C). PE-
A TEOS film (not shown) is formed.
【００３２】この第３実施例の場合第１実施例と同様な
効果が得られる。さらに、この第３実施例の場合、化学
気相成長によるケイ酸ガラス膜２３を設けた分、配線間
の絶縁膜の耐湿性が向上する。In the case of the third embodiment, the same effect as that of the first embodiment can be obtained. Further, in the case of the third embodiment, since the silicate glass film 23 formed by chemical vapor deposition is provided, the moisture resistance of the insulating film between the wirings is improved.
【００３３】上述においてはこの発明の配線の形成方法
の実施例について説明したがこの発明は上述の実施例に
限られない。Although the embodiment of the wiring forming method of the present invention has been described above, the present invention is not limited to the above embodiment.
【００３４】例えば上述の実施例では、第２の被覆層を
Ｃｕ−Ｔｉ合金膜で構成してその表層を窒化してＴｉＮ
膜から成るキャップ層２１ａを形成していたが、第２の
被覆層をＣｕと例えば他の高融点金属との合金膜で構成
してその表層を窒化して当該高融点金属の窒化物から成
るキャップ層を形成しても良い。例えば、タングステン
の窒化物や、モリブデンの窒化物などである。また、最
初から第２の被覆層自体をＴｉＮ膜など好適なもので構
成しても良い。また、第１の被覆層もＴｉＮ膜に限られ
ず他の好適なもので良い。For example, in the above-mentioned embodiment, the second coating layer is made of a Cu--Ti alloy film, and the surface layer thereof is nitrided to form TiN.
Although the cap layer 21a made of a film is formed, the second coating layer is made of an alloy film of Cu and, for example, another refractory metal, and its surface layer is nitrided to be made of a nitride of the refractory metal. A cap layer may be formed. For example, a nitride of tungsten, a nitride of molybdenum, or the like. Further, the second coating layer itself may be made of a suitable material such as a TiN film from the beginning. Further, the first coating layer is not limited to the TiN film and may be another suitable one.
【００３５】また、上述の実施例では銅配線の形成にこ
の発明を適用したがこの発明は他の材料の配線形成にも
適用できる。Further, although the present invention is applied to the formation of the copper wiring in the above-mentioned embodiments, the present invention can be applied to the wiring formation of other materials.
【００３６】また、上述の実施例では配線を形成したい
下地としてシリコンウエハを例示したが、下地は勿論こ
れに限られず配線を形成した種々のものであることがで
きる。Further, in the above-mentioned embodiment, the silicon wafer is exemplified as the base on which the wiring is desired to be formed, but the base is not limited to this, but may be various kinds of wiring.
【００３７】[0037]
【発明の効果】上述した説明からも明らかなように、こ
の発明の配線の形成方法によれば、下地上に感光性ＳＯ
Ｇ（スピンオングラス）の膜を形成し、これに配線パタ
ーンに対応した溝をリソグラフィにより形成する。次
に、この溝の形成が済んだ試料上に第１の被覆層、配線
主材層および第２の被覆層を形成する。そして、これら
第１の被覆層、配線主材層および第２の被覆層の溝内以
外の部分を除去する。このため、配線間の絶縁層および
配線をリソグラフィおよび所定の除去工程のみで簡易に
形成出来る。しかも、各配線の底面、側面および上面を
バリア性能が保証されたかつ配線の一部をも構成する被
覆層で覆うことができる。また、配線の主な部分は配線
主材料そのもので（例えば銅そのもの）で構成出来る。
したがって、低温でシリサイド化し易くかつシリサイド
や酸化膜中を容易に拡散し易い銅を用いても銅本来の特
性を生かした配線を簡易に形成出来る。As is apparent from the above description, according to the wiring forming method of the present invention, the photosensitive SO is formed on the base.
A G (spin on glass) film is formed, and a groove corresponding to the wiring pattern is formed in the film by lithography. Next, a first coating layer, a wiring main material layer, and a second coating layer are formed on the sample on which the groove has been formed. Then, the portions of the first coating layer, the wiring main material layer, and the second coating layer other than the inside of the groove are removed. Therefore, the insulating layer between the wirings and the wirings can be easily formed only by lithography and a predetermined removing process. Moreover, the bottom surface, the side surface, and the top surface of each wiring can be covered with the coating layer that guarantees the barrier performance and also constitutes a part of the wiring. Further, the main part of the wiring can be composed of the wiring main material itself (for example, copper itself).
Therefore, it is possible to easily form a wiring that makes use of the original characteristics of copper even if copper that is easily silicided at a low temperature and easily diffused in the silicide or the oxide film is used.
【図１】第１実施例の説明に供する工程図である。FIG. 1 is a process drawing for explaining a first embodiment.
【図２】第１実施例の説明に供する図１に続く工程図で
ある。FIG. 2 is a process diagram following FIG. 1 for explaining the first embodiment.
【図３】第３実施例の説明に供する工程図である。FIG. 3 is a process drawing for explaining the third embodiment.
【図４】第３実施例の説明に供する図３に続く工程図で
ある。FIG. 4 is a process chart following FIG. 3 for explaining a third embodiment.
１１：配線を形成したい下地 １３：感光性ＳＯＧ １５：溝 １７：第１の被覆層 １９：配線主材料から成る層（配線主材層） ２１：第２の被覆層 ２１ａ：第２の被覆層の窒化された部分 ２３：化学気相成長によるケイ酸ガラス膜 11: Base on which wiring is to be formed 13: Photosensitive SOG 15: Groove 17: First coating layer 19: Layer composed of wiring main material (wiring main material layer) 21: Second coating layer 21a: Second coating layer Part 23: Silica glass film by chemical vapor deposition
Claims (3)
（スピンオングラス）の膜を形成する工程と、 該ＳＯＧの膜に、形成したい配線パターンに対応した溝
をリソグラフィにより形成する工程と、 該溝の形成が済んだ試料上にバリア性および導電性を有
した第１の被覆層と、配線主材料からなる層と、バリア
性および導電性を有した第２の被覆層とをこの順にかつ
これら層が前記溝を埋めるよう形成する工程と、 前記形成された第２の被覆層、配線主材料からなる層お
よび第１の被覆層を、前記溝周囲のＳＯＧの膜の表面が
露出するまで除去する工程とを含むことを特徴とする配
線の形成方法。1. A photosensitive SOG is formed on a base on which wiring is to be formed.
A step of forming a (spin-on-glass) film, a step of forming a groove in the SOG film corresponding to a wiring pattern to be formed by lithography, and a barrier property and a conductivity on the sample in which the groove is formed. Forming a first coating layer having the same, a layer made of a wiring main material, and a second coating layer having a barrier property and conductivity in this order and so that these layers fill the groove; and Forming the second covering layer, the layer made of the wiring main material, and the first covering layer until the surface of the SOG film around the groove is exposed. .
て、 前記溝の形成が済んだ後であって前記第１の被覆層を形
成する前に、試料上に化学気相成長によりケイ酸ガラス
膜を形成する工程をさらに具えたことを特徴とする配線
の形成方法。2. The method of forming a wiring according to claim 1, wherein silicic acid is formed on the sample by chemical vapor deposition after the formation of the groove and before the formation of the first coating layer. A method of forming wiring, further comprising a step of forming a glass film.
て、 前記ＳＯＧの膜の表面を露出させるための前記除去を化
学的機械的研磨法により行なうことを特徴とする配線の
形成方法。3. The wiring forming method according to claim 1, wherein the removal for exposing the surface of the SOG film is performed by a chemical mechanical polishing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25507494A JPH08124926A (en) | 1994-10-20 | 1994-10-20 | Formation of wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25507494A JPH08124926A (en) | 1994-10-20 | 1994-10-20 | Formation of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08124926A true JPH08124926A (en) | 1996-05-17 |
Family
ID=17273780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25507494A Withdrawn JPH08124926A (en) | 1994-10-20 | 1994-10-20 | Formation of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08124926A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6174596B1 (en) * | 1997-02-13 | 2001-01-16 | Winbond Electronics Corp. | Process for fabricating dual damascene structure by applying an etch-differentiating technique on a light sensitive organic oxide layer |
| KR100327297B1 (en) * | 1998-03-24 | 2002-03-04 | 아끼구사 나오유끼 | Semiconductor device and fabricating method thereof |
| KR20020034373A (en) * | 2000-11-01 | 2002-05-09 | 박종섭 | Method for forming metal wire of semiconductor device |
| KR100399910B1 (en) * | 2000-12-28 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| JP2004514286A (en) * | 2000-11-15 | 2004-05-13 | モトローラ・インコーポレイテッド | Self-aligned magnetic cladding write line and method therefor |
| JP2004349572A (en) * | 2003-05-23 | 2004-12-09 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| CN114121793A (en) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | Multilayer metal wiring layer, preparation method thereof and packaging structure |
-
1994
- 1994-10-20 JP JP25507494A patent/JPH08124926A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6174596B1 (en) * | 1997-02-13 | 2001-01-16 | Winbond Electronics Corp. | Process for fabricating dual damascene structure by applying an etch-differentiating technique on a light sensitive organic oxide layer |
| KR100327297B1 (en) * | 1998-03-24 | 2002-03-04 | 아끼구사 나오유끼 | Semiconductor device and fabricating method thereof |
| KR20020034373A (en) * | 2000-11-01 | 2002-05-09 | 박종섭 | Method for forming metal wire of semiconductor device |
| JP2004514286A (en) * | 2000-11-15 | 2004-05-13 | モトローラ・インコーポレイテッド | Self-aligned magnetic cladding write line and method therefor |
| JP4846185B2 (en) * | 2000-11-15 | 2011-12-28 | エバースピン テクノロジーズ インコーポレイテッド | Semiconductor device and method for forming the same |
| KR100399910B1 (en) * | 2000-12-28 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| JP2004349572A (en) * | 2003-05-23 | 2004-12-09 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| CN114121793A (en) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | Multilayer metal wiring layer, preparation method thereof and packaging structure |
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| A300 | Withdrawal of application because of no request for examination |
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