JPH08116326A - Cell assembling device for asynchronous transfer mode communication system - Google Patents

Abstract

PURPOSE: To miniaturize a device by reducing redundancy when data is accumulated in the assembly of a cell. CONSTITUTION: A delay buffer part 10 delays the payload of the cell being analyzed by a header analysis part 12 for an analyzing period, add outputs it to a payload accumulation part 14. The header analysis part 12 Judges the effectiveness/ineffectiveness of the cell, and also, detects a scrapped cell. A write control part 22 writes only the payload Judged as an effective one by the header analysis part 12 on the payload accumulation part 14. A scrapped cell information accumulation part 26 accumulates the number of scrapped cells detected by the header analysis part 12 and the number of effective cells accumulated in the payload accumulation part 14 in sequence of occurrence. A readout control part 24 reads out the effective cell from the payload accumulation part 14 and dummy data from a dummy data pattern generating part 16 reacting according to an AAL user clock, and outputs AAL- SDU via a selector part 18 as fixed bit rate information. At this time. the readout control part 24 delays processing until the sum of the number of effective cells and that of scrapped cells exceeds a prescribed value, which absorbs cell delay fluctuation in a network. The insertion order of the dummy data is established by accurately inserting between the effective cells by cell information from the scrapped cell accumulation part 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell assembling apparatus in an asynchronous transfer mode communication system, and more particularly to a broadband service integrated digital network or an ATM LAN (Local Ar).
The present invention relates to a cell assembling apparatus in an asynchronous transfer mode communication method suitable for a receiving system connected to a network such as an ea network).

[0002]

2. Description of the Related Art In recent years, due to the digitization and integration of communication networks, the practical application of B-ISDN (Integrated Broadband Service Digital Network) capable of transmitting various media information including voice, data, and images has been progressively advanced. There is. One example of means for implementing this B-ISDN is ATM (asynchronous transfer mode).
Communication methods are known. The ATM communication system is a system in which various types of media information are divided into fixed-length cells called ATM cells and exchanged and transmitted in units of these cells.
By adopting this method, it is possible to unify networks and build a network that does not depend on various media.

In this case, ITU-TSS (International Telecommunication Union-
At the telecommunications sector, former CCITT)
Recommendation work on a protocol for mapping cells is underway. In particular, a protocol for cellizing and decelling various media into ATM cells is called ATM adaptation layer (hereinafter abbreviated as AAL), and its type is defined for each media and service.
Among them, for example, when transferring a signal from a conventional synchronous line, or when transferring a signal in the voice band,
In other words, constant bit rate (CBR: Continuous Bit Rat)
e) The ITU recommends AAL type 1 (hereinafter abbreviated as AAL1) as a protocol for converting information into ATM cells and converting information from ATM cells into fixed bit rate information. In this AAL1, division of user information into cells,
It provides various functions such as assembling, cell delay fluctuation absorption, cell loss and erroneous cell insertion processing, transmission side clock frequency recovery at the receiving side, and source data structure recovery at the receiving side.

For example, in the case where fixed bit rate information is converted into ATM cells on the transmission side, in so-called AAL1 cell decomposition, for example, voice information or the like is divided into 8-bit 1-unit AAL-SDUs.
Formed as (Service Data Unit), these AAL-
A service data unit is formed every 47 bytes as one cell division assembly sublayer service data unit (SAR-SDU). Furthermore, for one SAR-service data unit, consecutive sequence numbers SN (Seq
uence Number) and cyclic code check (C
RC: Cyclic Redundancy Check) 1-byte SAR-PD consisting of data and SN protection data including parity bit
Generate a U (Protocol Data Unit) header, combine this header with the 47-byte SAR-Service Data Unit to form a 48-byte AAL-Protocol Data Unit, that is, the information field of the ATM cell, and output it to the ATM network. . In an ATM network, that is, the ATM layer, an AAL-protocol data unit is added with a 5-byte ATM header including a destination code for transferring in the network, and is sequentially exchanged as a fixed-length 53-byte ATM cell. The transfer is repeated.

In the cell assembling device on the receiving side, the AAL-protocol data unit from which the ATM header is removed from the ATM cell transferred in the network is input, the header of the protocol data unit is extracted from this, and the cell is checked by parity check or the like. Judge valid / invalid, consider the cell with the missing number as a discarded cell by the consecutive number SN, and
Detects an erroneously inserted cell due to the order change, etc. In this case, the payload part, which is the actual information from which the header has been removed, is temporarily stored in the temporary buffer, and if it is valid according to the header determination, it is written to the FIFO memory. When the discarded cells are detected, the dummy data for the number of cells, for example, the dummy data which is a silent signal in the audio signal, is written in the FIFO memory, and then the payload following it is read from the temporary buffer and written in the FIFO memory. When an erroneously inserted cell is detected, the corresponding cell is idle-read from the temporary buffer and is not written in the FIFO memory. As a result, processing such as dummy data insertion and erroneous insertion cell elimination for cell loss in the network is executed.

When a predetermined number of data are written in the FIFO memory, that is, a delay amount for absorbing cell delay fluctuation in the network is inserted, and a user having a fixed bit rate similar to the bit rate on the transmission side is inserted. In response to the clock, the payload of cells containing dummy data is read in the input order from the FIFO memory, and the original fixed bit rate information is restored. In this way, the information for which the fixed bit rate is recovered and the data is reproduced is transferred to the synchronous transfer line or the voice terminal device.

[0007]

However, in the above-mentioned conventional technique, the cell assembling apparatus on the receiving side temporarily stores the payload of the cell in the temporary buffer, and selects the future data and the dummy data, In order to store these data in the FIFO memory, dummy data is stored in FI
There is a possibility that cells may arrive from the network while writing to the FO memory, and there is a problem that the capacity of the temporary buffer requires the capacity to store a plurality of cells including waiting cells and arriving cells. Further, in the FIFO memory, there is a problem that a relatively large capacity is required in order to store all the data including the payload from the temporary buffer and the dummy data. In other words, since the above-mentioned device has a configuration in which known information of a data pattern called dummy data is written in the FIFO memory, it has a high redundancy and is very inefficient. Therefore, in the above device, there is a problem that the device becomes large and expensive due to the two memories of the temporary buffer and the FIFO memory.

The present invention solves the above problems and realizes a memory configuration with less redundancy, thereby realizing a cell in an asynchronous transfer mode communication system which can realize a small and inexpensive device by reducing the hardware scale. An object is to provide an assembling device.

[0009]

In order to solve the above problems, a cell assembling apparatus in an asynchronous transfer mode communication system according to the present invention separates a payload of actual information from fixed length cells transferred in a network. When assembling fixed bit rate information, a fixed length cell is used in a cell assembling device in an asynchronous transfer mode communication system in which dummy data having a predetermined bit arrangement is inserted in place of a cell discarded in the network to restore the information. Header analysis means for extracting the protocol header of the cell division / assembly sub-layer from the cell to determine whether the cell is valid or invalid, and for detecting a discarded cell that has been delayed or lost in the network based on the serial number of the protocol header. And the fixed header with the protocol header removed when the header analysis means determines whether the cell is valid or invalid. Buffering means for temporarily delaying and accumulating the payload, which is the actual information of each cell, for each cell, and payload accumulating means for accumulating the payload from the buffering means sequentially when the validity of the cell is judged by the header analyzing means. A dummy data output means for outputting dummy data of a predetermined bit array in place of the discarded cell when the discarded cell is detected by the header analysis means, and a payload storage means and a dummy based on the analysis result from the header analysis means. The data output means is controlled to include control means for selectively outputting the payload and the dummy data. The control means includes discarded cell information storage means for storing discarded cell information from the header analysis means, and header analysis. The payload is read from the buffering means based on the determination result of the means and sequentially stored in the payload storage means. Payload write control means for writing a valid payload and the dummy data output means and the payload storage means are selectively controlled based on the discarded cell information from the discarded cell information storage means to insert dummy data between valid data. And a data read control means.

In this case, the discarded cell information storage means is formed by a FIFO memory that stores and reads out the discarded cell information from the header analysis means and the valid cell write information from the payload write control means in that order. Good. Similarly, the payload storage means may be formed by a FIFO memory that reads the payload from the buffering means in the writing order. The data read control means may control the payload storage means and the dummy data output means in response to the user clock to read the dummy data and the payload at a fixed bit rate according to the user clock.

On the other hand, the payload write control means may, upon receiving a signal indicating invalidity of the cell from the header analysis means, idle-read the payload from the buffering means and discard the erroneously inserted cell. The payload write control means sends cell write information to the data read control means every time the valid cell from the buffering means is written in the payload storage means, and the data read control means means the cell from the payload write control means. It is preferable to read the respective data when the total of the number of valid cells according to the write information and the number of discarded cells from the discarded cell information storage means reaches a predetermined number of cells. Further, the data read control means may stop the read when the total of the number of valid cells and the number of discarded cells is less than the predetermined number of cells.

[0012]

According to the cell assembling apparatus in the asynchronous transfer mode communication system of the present invention, when the fixed length cell transferred from the network is received, the header analysis means extracts the protocol header of the cell division assembling sublayer from the fixed length cell. do it,
Whether the cell is valid or invalid is determined, and the discarded cell is detected from the serial number included in the protocol header. If the cell is valid, the payload temporarily stored in the buffering means is read and sequentially written in the payload storage means. If the cell is invalid, it is regarded as an erroneously inserted cell and the payload from the buffering means is discarded by idle reading. When a discarded cell is detected by the header analysis means, the discarded cell information is stored in the discarded cell information storage means, and if the payload of the buffering means is valid at this time, it is immediately transferred to the payload storage means. . As a result, in the buffering means, the payload is read at a fixed delay accumulation time only during a predetermined period during which the cell is determined by the header analysis means, and only the valid payload is sequentially written in the payload accumulation means. . Next, the data read control means selectively controls the dummy data output means and the payload storage means based on the discarded cell information, and sequentially reads the dummy data or the valid payloads, so that the valid data is stored between the valid payloads. The fixed bit rate information in which the dummy data is inserted is restored and passed to the synchronous line or the terminal device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a cell assembling apparatus in the asynchronous transfer mode communication system according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of the cell assembling apparatus according to the present invention. The cell assembling apparatus according to the present embodiment is an ATM adaptation layer applied to a receiving system connected to an ATM network such as B-ISDN (Broadband Integrated Services Digital Network) that employs an asynchronous transfer mode (ATM) communication method. This is a level (hereinafter referred to as AAL) circuit. In particular, this device uses fixed bit rate information, such as voice band signals, for fixed length ATM at the transmission side.
AT received from the cell when it is divided into cells and transferred over the network
It is an AAL type 1 cell assembling device that assembles and restores the same fixed bit rate information from the M cell as the transmitting side.

Specifically, this apparatus has a 48-byte ATM adaptation layer protocol data unit after the 5-byte ATM header has been removed from the 53-byte fixed-length ATM layer cell transferred over the ATM network. AAL-PDU
Is entered. This AAL-Protocol Data Unit is
As shown in Fig. 2, the 1-byte cell division assembly sublayer protocol data unit (SAR-PDU) header containing the serial number SN and the SN protection data SNP consisting of CRC cyclic code check data and parity check, and the actual cell A 47-byte sublayer service data unit (SAR) that consists of a protocol data unit (SAR-PDU) payload that is information.
-SDU), and by extracting the payload part from each unit and outputting it with the same user clock as the transmitting side, the original 8-bit parallel ATM adaptation layer service unit (AAL-SDU) ) To restore the information. In particular, this equipment detects the number of discarded cells lost due to a large delay or loss during network transfer from the header of the protocol data unit (SAR-PDU), and the dummy data for that number of cells is used as valid cells. Insert in between to restore the original constant bit rate information.

More specifically, the cell assembling apparatus of this embodiment is shown in FIG.
As shown in, the delay buffer unit 10 and the header analysis unit
12, a payload storage unit 14, a dummy data pattern generation unit 16, a selector unit 18, and a control unit 20,
In particular, the control unit 20 of this embodiment includes a write control unit 22, a read control unit 24, and a discarded cell information storage unit 26. ATM adaptation layer protocol data unit AAL-PDU
Are supplied to the delay buffer section 10 and the header analysis section 12 as needed in the order of arrival.

The delay buffer unit 12 includes a protocol data unit AAL-PDU to a sublayer unit (SAR-PDU).
This is a buffer circuit that temporarily stores the sublayer payload SAR-SDU with the header removed for each cell, and the header analysis unit 1 for each sublayer payload SAR-SDU for each cell.
It is a delay circuit that delays by the time required for analysis in 2 and outputs. That is, the input cells are accumulated for each cell, and when the cell analysis by the header analysis unit 12 is completed, the accumulated sublayer payload SAR-SDU is read and the payload of the next cell is sequentially input together with the header analysis unit 12. It is an input buffer that repeats the operation of accumulating and accumulating and outputting again after a predetermined time has elapsed.

The header analysis unit 12 is a determination circuit that determines whether the arrival cell is valid or invalid by extracting the header of the sub-layer protocol from the protocol data unit AAL-PDU. Assigned serial number
This is a cell analysis circuit that detects the number of cells that have been delayed and lost during network transfer, that is, the number of discarded cells, by comparing the SN order. Specifically, the CR included in the SN protected data
Error detection of all header bits including the serial number SN in C data is performed, if there is no error, it is judged to be valid, if there is an error, it is corrected by parity check, and then the error is further detected and enabled. Or judge invalidity. When the parity check is enabled, it is determined that there are no discarded cells if they are consecutive compared to the previous cell serial number, and if there are no consecutive numbers, it is determined that the number of discarded cells has occurred. To do. If the serial number goes backward, it is determined as an erroneously inserted cell. When an erroneously inserted cell is detected and when the parity check is determined to be invalid, a cell write disable signal indicating an invalid cell is output from the first output I1 and when it is valid, a cell write indicating a valid cell is written. Output a ready signal. When the discarded cell is detected, the discarded cell information indicating the number of the discarded cell is output from the second output I2. The first output I1 is connected to the write control unit 22 of the control unit 20, and the second output I2 is connected to the write control unit 22 and the discarded cell information storage unit 26.

On the other hand, the payload accumulator 14 is a FIFO (First-in First-out) in which valid sub-layer payload SAR-SDUs from the delay buffer 10 are sequentially written and read in that order under the control of the controller 20. ) A storage circuit composed of a memory and having a capacity capable of storing payloads for a plurality of cells to absorb cell delay fluctuations. Specifically, the payload SAR-SDU output from the delay buffer unit 10 when the write control unit 22 of the control unit 20 is given a cell write enable signal indicating a valid cell from the header analysis unit 12 This is a payload storage circuit in which data is sequentially written to a predetermined address, and the payload is read by a read enable signal and an address signal from the read control unit 24 supplied in that order.

The dummy data pattern generation unit 16 is a pattern generation circuit which generates 47 bytes of dummy data for each cell in a predetermined pattern. For example, in the case of a voice signal, it generates dummy data of a silent signal pattern. It is a silent signal generating circuit.

The selector section 18 is a 2-input / 1-output selector circuit, which controls the payload of the actual information from the payload storage section 14 and the dummy data from the dummy data pattern generation section 16 under the control of the control section 20. This is a selection unit for switching and outputting. The output from the selector unit 18 is output as an ATM adaptation layer service data unit AAL-SDU that is restored to 8-bit parallel information.

The control unit 20 is a control circuit for selectively outputting the payload or dummy data by reading the payload from the payload storage unit 14 and switching the selector unit 18 based on the determination result from the header analysis unit 12, In particular, in response to the same AAL user clock as the transmitting side while absorbing the cell delay fluctuation by detecting the number of receiving buffer cells, that is, the number of incoming cells including the number of accumulated cells and the number of discarded cells in the payload accumulator 14, It is a synchronization control circuit that restores data at a fixed bit rate.

More specifically, the write controller 22 of the controller 20.
Is a data write control unit that gives a write address and a permission signal for sequentially writing the sub-layer payload SAR-SDU read from the delay buffer unit 10 to the payload storage unit 14. It is a payload control unit that supplies a write enable signal and a write address to the payload storage unit 14 only when it is detected, and sequentially stores only valid data in the payload storage unit 14. If the header analysis unit 12 detects an invalid cell,
The data from the delay buffer unit 10 is discarded as an erroneously inserted cell by idle reading and is not stored in the payload storage unit 14. When a valid payload is written in the payload storage unit 14, a 1-cell write signal is given as data write information to the discard cell information storage unit 26 via the third information output J3, and when a discard cell is generated. Is the read control unit 24 via the second information output J2 with the total of the number of discarded cells and the number of cells written in the payload storage unit 14 as the number of write completed cells.
Supply to.

The discarded cell information storage unit 26 includes a header analysis unit 12
Is an information storage unit that receives and discards the discarded cell information from the write control unit 22, accumulates the 1-cell write signal from the write control unit 22 and the discarded cell information in the order of their generation, and the reference signal from the read control unit 24. An order-controllable FI that reads stored information in the order of occurrence according to K2 and gives it to the read control unit 24.
Including FO memory. Especially when there are discarded cells,
Although writing of valid cells and discard cell information occur almost at the same time, valid cell write information is accumulated after the number of discard cells.

The read control unit 24 is a control unit that controls the reading of the payload from the payload storage unit 14 and the switching control of the selector unit 18, and counts the number J2 of write completed cells from the write control unit 22. The number of received cells is detected by the buffer, and when the number of cells reaches a predetermined number, the payload is read from the payload storage section 14 or the selector section 18 is switched in response to the AAL user clock to switch the dummy data output section.
A sequence control circuit that controls reading of dummy data from 16. In this case, the number of reception cell buffer cells to start reading is set as the read start reception cell number RSRC, and the number of reception cell buffer cells to stop reading is set in advance as the read stop reception cell number RERC.

The operation of the cell assembling circuit according to the present embodiment having the above-described structure will be described. First, the ATM network to the AT will be described.
When the M cell arrives, the ATM header of the receiving system (not shown) is removed and the ATM cell is input to this device. In this device, the protocol data unit AAL-PDU of the adaptation layer is received by the delay buffer 10 and the header analysis unit 12.

At this time, in the delay buffer unit 10, the payload of the protocol data unit obtained by removing the protocol header from the protocol data unit AAL-PDU, that is, the sub-layer service data unit SAR-SDU
Is temporarily stored. During this time, the header analysis unit 12 extracts the protocol header from the protocol data unit AAL-PDU and determines whether the cell is valid or invalid. If the cell is valid, a write enable signal representing a valid cell is sent to the write controller 22 of the controller 20 via the first output I1. The write control unit 22 that has received the write permission sends the write control signal and the address signal to the payload storage unit 14 in accordance with the delay time in the delay buffer unit 10. This enables the valid service data unit SAR- from the delay buffer unit 10.
The SDU is written in the payload storage unit 14. When the writing of the payload is completed, the writing control unit 22 causes the second
Also, a 1-cell write completion signal is supplied to the read control section 24 and the discarded cell information storage section 26 via the third information outputs J2, J3. The discarded cell information accumulating section 26 which has received the 1-cell write completion signal writes this to a predetermined address, and the reading control section 24 counts the number of received cell buffers by one.

On the other hand, when the header analysis unit 12 detects an invalid cell, the header analysis unit 12 supplies a write disable signal indicating the invalid cell to the write control unit 22 via the first output I1. In response to this, the write control unit 22 does not send a control signal to the payload storage unit 14. As a result, the invalid payload from the delay buffer unit 10 is idle read and discarded. This is the case when the cells are treated as erroneously inserted cells, for example, when the serial numbers SN are not added in the order of arrival.

If the header analysis unit 12 detects a discarded cell, for example, if the serial number SN is far from the previous number, the cell between them is regarded as a discarded cell during network transfer, Information corresponding to the number of cells, that is, the number of discarded cells is supplied to the write control unit 22 and the discarded cell information storage unit 26 via the second output I2. In this case, since the payload itself stored in the delay buffer unit 10 is valid, a write enable signal representing a valid cell is supplied from the first output I1 to the write control unit 22 to the payload storage unit 14. The write control signal and the updated address are supplied. As a result, the payload from the delay buffer unit 10 at that time is written in the payload storage unit 14. As a result, the second information output of the write controller 22 outputs write information representing the total value of the 1-cell write signal and the number of discarded cells, and the read controller 24 counts this. Discarded cell information storage unit 26
Is supplied with a 1-cell write signal via the third information output. As a result, the discarded cell information storage unit 26 stores the write information in the address next to the address in which the number of discarded cells from the header analysis unit 12 is stored.

As described above, the header analysis unit 12 repeatedly determines whether the payload is valid or invalid and detects the number of discarded cells for each input of the adaptation layer protocol data unit AAL-PDU. Thus, only a valid payload is stored in the payload storage unit 14 every one cell delay. At this time, the discard cell information storage unit 26 stores the write information and the discard cell information for each cell in the order of occurrence, and the read control unit 24 sequentially calculates the total value of the number of write cells and the number of discard cells. I will count. As a result, the read control unit 24
When the count value exceeds the read start reception cell number RSRC at, the reference signal K2 is sent to the discarded cell information storage unit 26, and the discarded cell information is sequentially read therefrom. In this case, the read control unit 24 executes the following two processes depending on the value of the number of dummy data cells.

First, when the value of the number of dummy data cells is significant, that is, when discarded cells are detected, a selector control signal is supplied to the selector section 18 to set the selector section 18 on the dummy data pattern generation section 16 side. Then, the dummy data is generated from the dummy data pattern generation unit 16 via the selector unit 18 to the service data unit AAL- of the adaptation layer.
SDU is transmitted at a fixed rate for the number of dummy data cells at the AAL user clock rate. Immediately after transmitting the dummy data, a selector control signal is sent to the selector section 18 immediately.
Is set on the output side of the payload storage unit 14, the payload is read from the payload storage unit 14 according to the read control and read address, and is fixed as one cell at the AAL user clock speed as the adaptation service unit AAL-SDU via the selector unit 18. Send at speed. When the reading of each data is completed, the count value is decremented by one.

When the value of the number of dummy data cells is 0, a selector control signal is sent to the selector section 18 to set the selector section 18 on the output side of the payload storage section 14. Next, the read control signal and the address signal are supplied to the payload storage unit 14, the payload is read from the payload storage unit 14, and the payload is read from the payload unit 14 as a service data unit AAL-SDU at the speed of the AAL user clock by one cell. Send at a fixed rate for minutes. When the reading of the payload is completed, the count down from the number of reception cell buffers is performed in the same manner as above.

As described above, the read control unit 24 is the write control unit.
When the value obtained by counting the write information and the discard cell information from 22 exceeds the read start reception cell number RSRC, the payload is sequentially read from the payload storage unit 14 according to the cell information of the discard cell information storage unit 26, and the selector unit 18 The constant bit rate information is restored by selectively reading the dummy data by switching in response to the AAL user clock. During this period, if there is a cell incoming to the delay buffer unit 10 and the header analysis unit 12, the write control unit
Writing of a valid payload in the payload storage unit 14 at 22 and detection of discarded cells are continued. As a result, the read operation of the read controller 24 is repeated in the same manner as above.

If the read operation is continued when the incoming cell is interrupted or has ended, the number of received cell buffer cells is continuously counted down to approach the set read stop receiving cell RERC. Then
The read control unit 24 reads the number of dummy data cells from the discarded cell information storage unit 26 in the same manner as above, and repeats the above operation again. When the number of reception cell buffer cells is less than the read stop reception cell number RERC, the discarded cell information storage unit 26
And reading from the payload storage unit 14 is stopped.
In this state, when the incoming cell is input again, the read control unit 24 starts counting again, waits for the number of received cell buffer cells to reach the read start number of received cells RSRC, and then reads the same as above. Start operation. In this way,
By monitoring the amount of cells stored in the payload storage unit 14 and the number of discarded cells by the read control unit 24 and repeating the start and stop of reading, the delay fluctuation of cells in the network is absorbed and the AAL user By outputting the service data unit AAL-SDU of the adaptation layer in synchronization with the clock, the data can be effectively restored with the same clock as the transmitting side.

As described above, according to the cell assembling apparatus of this embodiment, only the valid payload from the delay buffer unit 10 is written in the payload storage unit 14 and the selector unit 16 is used only when there is a discarded cell. Then, the dummy data from the dummy data pattern generator 16 is read and output as adaptation service data AAL-SDU. In this case, the insertion position of the discarded cell into the valid cell can be set accurately based on the information from the discarded cell information storage unit 14. Therefore, the memory configuration can be used to store only valid data, and a cell assembling system with almost no redundancy can be provided.

Next, in order to clarify the structure of this embodiment, a comparison with this embodiment will be made with reference to an example of a conventional cell assembling apparatus shown in FIG. In this figure, the same parts as those in the present embodiment are designated by the same reference numerals and the description thereof will be omitted. In this example, the output of the temporary buffer 50 that stores the protocol payload SAR-SDU and the output of the dummy data pattern generation unit 52 that outputs dummy data are the selector unit.
The output of the selector unit 18 connected to 18 and selecting one of them is connected to a data storage unit 60 formed of a FIFO memory. The control unit 70 receives the judgment result and the number of discarded cells from the header analysis unit 12 in the write control unit 72, reads valid data and invalid data from the temporary buffer, and discards them by switching control of the selector unit 18. The payload is read while inserting dummy data for the number of cells, and the data is sequentially written in the data storage unit 60. When the read control unit 74 receives the write information from the write control unit 72 and the data stored in the data storage unit 60 exceeds a predetermined number of cells, the read control unit 74 responds to the AAL user clock and outputs the data from the data storage unit 60. Is output as an adaptation layer service unit AAL-SDU.

As described above, in the example of FIG. 3, the output of the temporary buffer 50 and the output of the dummy data generating section 16 are output by switching the selector 18, so that the temporary buffer 50
In addition, at least a capacity for storing cells in the dummy data insertion period is required. Further, since the data of the fixed bit rate is restored with the dummy data stored in the data storage unit 60, the data storage unit 60 needs an extra capacity to store the dummy data. However, in the present embodiment, as described above, only the payload of one cell is stored in the delay buffer unit 10 and only the valid ones of the arriving cells are stored in the data storage unit 14. Can be formed. Further, the payload stored in the data storage unit 14 and the dummy data from the dummy data pattern generation unit 16 based on the discarded cell information are sent to the selector unit 18
Since the data is selected and output in step 3, only the valid cells can be stored in the data storage section 16, and the capacity can be reduced without storing extra data such as dummy data.
Therefore, the temporary buffer 50 required in the conventional cell assembly configuration becomes the delay buffer 10 with a fixed delay, and the hardware scale becomes very small. In addition, it was possible to realize an effective cell assembling method for writing only valid cells in the received cell data, which was a redundant configuration for directly writing dummy data.

In the above embodiment, the case where the present apparatus is applied to the receiving system connected to the B-ISDN has been described as an example, but the present invention can be applied to other ATM networks such as ATM LAN. Good. In the above embodiment, the selector section 18 is replaced by the control section.
The switching control is performed by the control signal from 20. However, in the present invention, the dummy data pattern generation unit 16 is directly turned on / off, and the signal from the payload storage unit 14 and the dummy data pattern generation unit 14 are controlled. Either of them may be output, for example, an OR circuit may be used for connection.

[0038]

As described in detail above, according to the cell assembling apparatus in the asynchronous transfer mode communication system of the present invention,
While storing valid cells in the payload storage means through the buffering means, when a discarded cell is detected, a dummy data pattern is output from the dummy data output means, and dummy data is output between the valid cells read from the payload storage means. Since only the effective data can be stored in the payload storage means, a cell assembly system with low redundancy and high efficiency can be executed. Therefore, there is an excellent effect that an inexpensive device having a small circuit scale can be formed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cell assembling apparatus in an asynchronous transfer mode communication system according to the present invention.

2 is a cell division assembly sublayer according to the embodiment of FIG.
It is a figure which shows a protocol data unit.

FIG. 3 is a block diagram showing a comparative example of the cell assembling apparatus of this embodiment.

[Explanation of symbols]

10 Delay buffer 12 Header analysis unit 14 Payload storage unit 16 Dummy data pattern generation unit 18 Selector unit 20 Control unit 22 Write control unit 24 Read control unit 26 Discarded cell information storage unit AAL-PDU ATM Adaptation layer-Protocol data unit SAR- SDU cell division assembly sublayer-service data unit AAL-SDU ATM adaptation layer service data unit

Claims (7)

[Claims] 1. When assembling fixed bit rate information by separating a payload of real information from fixed length cells transferred in the network, cells of a predetermined bit arrangement are replaced with cells discarded in the network. In a cell assembling apparatus in an asynchronous transfer mode communication system in which dummy data is inserted to restore information, the apparatus extracts a protocol header of a cell division assembling sublayer from a fixed length cell and determines whether the cell is valid or invalid. And a header analysis unit that detects a discarded cell that has been delayed or lost in the network based on the serial number included in the protocol header, and the header analysis unit determines whether the cell is valid or invalid. Buffering that temporarily stores the payload, which is the actual information of fixed-length cells from which protocol headers have been removed, for each cell A step, a payload storage unit that sequentially stores the payload from the buffering unit when the header analysis unit determines that the cell is valid, and a discard cell when the discarded cell is detected by the header analysis unit. In place of dummy data output means for outputting dummy data of a predetermined bit array pattern, and controlling the payload storage means and dummy data output means based on the analysis result from the header analysis means, and the payload and dummy data. And a control means for selectively outputting the discarded cell information storage means for storing the discarded cell information from the header analysis means, and the buffering means based on the determination result of the header analysis means. To read the temporarily stored payload and sequentially write the valid payload to the payload storage means. The payload writing control means to be loaded, and the dummy data output means and the payload storage means are selectively controlled based on the discard cell information from the discard cell information storage means to insert dummy data between valid data. A cell assembling apparatus in an asynchronous transfer mode communication system, comprising a data read control means. 2. The cell assembling apparatus according to claim 1, wherein the discarded cell information accumulating unit includes the discarded cell information from the header analyzing unit and the valid cell writing information from the payload writing control unit. Accumulate and read in order
A cell assembling apparatus in an asynchronous transfer mode communication system characterized by including a FIFO memory. 3. The cell assembling apparatus according to claim 1, wherein the payload accumulating unit reads the payload from the buffering unit according to a writing order.
A cell assembling apparatus in an asynchronous transfer mode communication system characterized by including an FO memory. 4. The cell assembling apparatus according to claim 1, wherein the data read control means controls the payload storage means and the dummy data output means in response to a user clock, and the dummy data and the payload are respectively fed with the user clock. A cell assembling apparatus in an asynchronous transfer mode communication system, which reads at a fixed bit rate according to. 5. The cell assembling apparatus according to claim 1, wherein said payload write control means idle-reads a payload from said buffering means when receiving a signal indicating invalidity of a cell from said header analysis means. A cell assembling apparatus in an asynchronous transfer mode communication system, characterized in that the misinserted cell is discarded. 6. The cell assembling apparatus according to claim 1, wherein the payload write control unit causes the data read control unit to write a cell to the data storage control unit each time the payload of the valid cell from the buffering unit is written in the payload storage unit. Write data is sent, and the data read control means sets the total of the number of effective cells according to the cell write information from the payload write control means and the number of discarded cells from the discarded cell information storage means to a predetermined number of cells. A cell assembling apparatus in an asynchronous transfer mode communication system, which is characterized in that each data is read out when reaching. 7. The cell assembling apparatus according to claim 6, wherein the data read control means is configured to store the payload storage means and dummy data when the total number of valid cells and the number of discarded cells is less than a predetermined number of cells. A cell assembling apparatus in an asynchronous transfer mode communication system, characterized in that reading of data from an output means is stopped.