JPH0810817B2 - Latch circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit with a set signal or reset signal input terminal in a current switching type logic circuit.

[0002]

2. Description of the Related Art Nowadays, as semiconductor devices are highly integrated, master slice type LSIs which can easily meet diversifying customer needs are becoming mainstream. In the manufacture of a master slice type LSI, first, a common substrate is formed by arranging a required number of basic cells in which the minimum necessary elements for forming various logic circuits are arranged in an array. Then, the common substrate is connected to form an internal cell portion. Then, the input / output section and the external terminal connecting section are formed so as to surround the outer periphery of the internal cell section.

FIG. 7 shows the configuration of a conventional latch circuit. This latch circuit consists of 12 transistors Q
201 to Q212 and six normal resistors R201 to R20
6 and two level shift resistors R207 and R208,
First and second power supply terminals 1 and 2, and first, second and third power supply terminals
Reference potential terminals 3, 4, and 5 and strobe signal terminal 6
, A data signal terminal 7, a reset signal terminal 8 and an output terminal 9.

The bases of the transistors Q201 and Q202 are connected to the data signal terminal 7 and the first reference potential terminal 3, respectively, and the collectors thereof are respectively connected to the resistor R201.
And connected to the first power supply terminal 1 via R202,
The emitters are connected to each other and the transistor Q20
It is connected to 6 collectors. These transistors Q
A differential logic circuit for inputting a data signal is constituted by 201 and Q202.

Transistors Q203 and Q204 are
The collectors are connected to the first power supply terminal 1 via resistors R201 and R202, respectively, and the emitters are connected to each other and to the collector of the transistor Q205. Also, at the base of the transistor Q203,
The collector potential of the transistor Q202 is fed back by the transistor Q212 and the resistor R208. The collector potential of the transistor Q201 is fed back to the base of the transistor Q204 by the transistor Q211 and the resistor R207. As a result, a differential logic circuit for holding a data signal is constructed.

The bases of the transistors Q205 and Q206 are respectively connected to the emitter of the emitter follower transistor Q208 for inputting the strobe signal and the second reference potential terminal 4, the emitters are connected to each other, and the transistor Q207 for constant current source is connected. Connected to the collector. As a result, a differential logic circuit for inputting and holding and switching the data signal by the strobe signal is formed.

The transistor Q209 has a base connected to the reset signal terminal 8 and a collector connected to the first power supply terminal 1
, And the emitter is connected to the emitter of the transistor Q208. Also, the transistor Q210 is
The base is connected to the reset signal terminal 8, and the collector and the emitter are connected to the collector and the emitter of the transistor Q204, respectively.

Next, the operation and action of the conventional latch circuit configured as described above will be described with reference to the truth table shown in FIG. When the strobe signal terminal 6 and the reset signal terminal 8 are in the low level state, the transistor Q205 turns off and the transistor Q206 turns on. At this time, the differential logic circuit including the transistors Q201 and Q202 forms a data through circuit from the data signal terminal 7 to the output terminal 9 (a low-level strobe signal sets the data through mode).

That is, when the data signal input terminal 7 is in the high level state, the transistor Q201 turns on and the transistor Q202 turns off. As a result, a constant current (hereinafter, constant current I) generated by the transistor Q207 and the resistor R203 passes through the path of the resistor R201, the transistors Q201 and Q206, and the potential of the power supply terminal 1 is applied to the base of the transistor Q212.
The output terminal 9 is in a high level state (case 1).

On the contrary, when the data signal terminal 7 is in the low level state, the transistor Q201 is turned off and the transistor Q202 is turned on, and the constant current I passes through the path of the resistor R202, the transistors Q202 and Q206, and reaches the base of the transistor Q212. Since this potential is lower than that in case 1, the output terminal 9 is in a low level state (case 2).

Next, from this state, the strobe signal terminal 6
Goes to the high level state (from the through mode to the latch mode), the transistor Q205 turns on and the transistor Q206 turns off, so that the level state of the output terminal 9, that is, the path of the constant current I, becomes
It is determined by the base potentials of 0, Q203 and Q204. As mentioned above, transistors Q203 and Q
The base potential of 204 is the transistor Q202.
Since the collector potential of Q201 and Q201 is fed back, if the reset signal terminal 8 is in the low level state, the current flowing through the resistor R201 or the resistor R202, that is, the level state of the output terminal 9 is the high level of the strobe signal terminal 6. The state (Qn) before the state is maintained (case 3).

In the above latched state, when the reset signal terminal 8 becomes the high level state, the transistor Q21
0 is turned on, and the base potentials of the transistors Q203 and Q204 are level-shifted to the lower side by the voltage drop of the resistors R208 and R207 from the normal level state of the input / output terminals. As a result, the transistors Q203 and Q204 are turned off, and the constant current I passes through the path of the resistor R202 and the transistors Q210 and Q205. As a result, the output terminal 9 is forced to be in the low level state (case 4).

After that, even if the reset signal terminal 8 is in the low level state, the output terminal 9 is in the state of the transistor Q2 as long as the strobe signal terminal 6 is in the high level state.
The low level state is held by turning on 03 and Q204 (case 5).

Even when the strobe signal terminal 6 is in the low level state, if the reset signal 8 is in the high level state, the transistor Q209 is turned on, and the strobe signal terminal 6 is in the same state as in the high level state. The state of the output terminal 9 becomes a low level state regardless of the state of the data signal 7 (case 6).

In the above circuit structure, the level shift resistors R207 and R208 lower the base potentials of the transistors Q203 and Q204 by a predetermined value from the potential of the power supply terminal 1, and the resistance values thereof are usually the above-mentioned values, respectively. Level shift amount is 1/3 of logic amplitude
It is set to be 1/4.

FIG. 9 shows a conventional latch circuit used in the master slice method.
The configuration of the basic cell 60 is shown. This basic cell 60
Includes eight transistors T1 to T8, fourteen normal resistors P1 to P14, and one level shift resistor P15.
A first power supply line 61, second power supply lines 62 and 66,
First, second and third reference potential lines 63 to 65 are formed in advance.

The transistors T1 to T8 respectively have contact holes for the collector C, the emitter E and the base B, are adjacent to each other, and are arranged in a substantially rectangular shape. The emitters E of the transistors T1 to T8 are 0.8 μm × 2.2.
Each transistor has a dimension of μm, and the area occupied by one transistor is 6.4 μm × 8.3 μm≈52 μm ² .

The normal resistors P1 to P14 each have a layer resistance of 1.3 KΩ / mm ² , a resistance value of 4 KΩ, and an occupied area.
2.6 μm × 9.9 μm≈26 μm ² . The normal resistors P1 to P4 are arranged on the right side of the basic cell 60 so that one terminal is connected to the second power supply line 62, and the normal resistors P1 to P4 are arranged.
7 to P14 are arranged on the left side of the basic cell 60 so that one terminal is connected to the second power supply line 66. Normal resistance P
5 and P6 are arranged between the transistors T3 and T8 so that one terminal thereof is connected to the first power supply line 61.

The level shift resistor P15 is a normal resistor P7.
Is arranged adjacent to P14. Level shift resistor P1
5 has a layer resistance of 1.3 KΩ / mm ² and a resistance value of 300
Ω, occupied area is 12.4 μm × 5.8 μm≈72 μm ²
Is formed. As described above, the level shift resistor P15 requires a larger area than the normal resistor because the resistance value is small and manufacturing accuracy is required. The occupied area on the substrate of the basic cell 60 configured as described above is 64
μm × 30 μm = 1920 μm ² .

Since the conventional latch circuit shown in FIG. 7 includes 12 transistors, 6 normal resistors and 2 level shift resistors, the basic cell 6 shown in FIG.
Master slice type LS by using two 0s
I is formed. FIG. 10 shows a state of a substrate to which basic cells 90a and 90b having the same structure as the basic cell 60 are connected. Further, FIG. 11 shows a state where wiring is actually provided on the substrate of FIG. Note that, in FIG. 11, transistors and resistors corresponding to those in FIG. 7 are denoted by the same reference numerals.

In the basic cell 90a, the transistor T
903, T904, T905, T906, T907 and T908 are transistors Q209, Q206 and Q20.
1, Q207, Q203 and Q211 respectively. The normal resistors P903 and P904 correspond to the resistor R203 by being connected in parallel, and the normal resistor P91
4 and P906 correspond to the resistors R205 and R201, respectively. The level shift resistor P915 corresponds to the resistor R207.

In the basic cell 90b, the transistors T921, T922, T923, T924, T925 and T928 are the transistors Q205, Q204. Q2
12, Q210, Q202, and Q208, respectively, and normal resistors P927 and P925 are resistors R204 and R2.
02, and the level shift resistor P935 corresponds to the resistor R208.

FIG. 12 shows a conventional master-slave D-type flip-flop with reset terminal using the conventional latch circuit shown in FIG. 7 on the master side. This circuit includes 22 transistors Q401-
Q422 and 11 normal resistors R401 to R407, R
409, R410, R412, R413, R419,
Two level shift resistors R407 and R408 are used.

The logical operation of the flip-flop circuit configured as described above is as shown in the truth table of FIG. In order to configure this master-slave D-type flip-flop circuit by the master slice method, three basic cells 60 shown in FIG. 9 are used as shown in FIG.

[0025]

However, the conventional latch circuit shown in FIG. 7 and the conventional master-slave D-type flip-flop circuit shown in FIG.
Level shift resistors R207, R for inputting the reset signal
208 (R407, R408) is required. Since this resistor is different from other ordinary resistors by its nature, in the case of a master slice type LSI, the level shift resistor R
It is necessary to incorporate 207 and R208 (R407 and R408) in the basic cell 60 separately from other normal resistors.

Therefore, the area occupied by the basic cell 60 on the semiconductor substrate is increased, and as a result, the area of the entire chip is increased. On the other hand, if the chip area is designed to be constant, there is a drawback that the number of wiring channels is reduced.

In view of the above-mentioned drawbacks, an object of the present invention is to provide a latch circuit which can keep the chip area small even when formed by the master slice method.

[0028]

The latch circuit of the present invention comprises:
A first ECL circuit which receives a data signal and outputs the true and inverse of the data signal, respectively; and amplifies the true and inverse levels of the data signal and positively feeds them back to each other to hold the data signal A second ECL circuit having a first current path connected in parallel to the flip-flop circuit and the flip-flop circuit; and receiving a strobe signal to switch the drive current to the first and second ECL circuits, A third ECL circuit for controlling the input and retention of the data by activating each; a first ECL circuit for receiving the control signal and flowing the drive current to the second ECL circuit through the first current path Switch means; a second current path connected between the second and third ECL circuits; before receiving the control signal and flowing to the first current path Wherein further diverting the drive current second
And a second switch means for flowing in the current path.

Further, the control signal may be a reset signal for setting the flip-flop circuit in a reset state.

[0030]

The present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a latch circuit according to the first embodiment of the present invention. This latch circuit includes 13 transistors Q101 to 108, Q110 to 112, Q
123, Q124 and seven normal resistors R101-10
5, R114, R116, the first and second power supply terminals 1 and 2, and the first, second and third reference potential terminals 3, 4,
5, a strobe signal terminal 6, a data signal terminal 7,
It is composed of a reset signal terminal 8 and an output terminal 9. That is, the latch circuit of the present embodiment is configured by removing the transistor Q209 and the level shift resistors R207 and R208 and adding the transistors Q123 and Q124 and the resistor R114 to the conventional latch circuit shown in FIG. It

The bases of the transistors Q101 and Q102 are connected to the data signal terminal 7 and the first reference potential terminal 3, respectively, and the collectors thereof are respectively connected to the resistor R101.
And connected to the first power supply terminal 1 via R102,
The emitters are connected to each other and the transistor Q10
It is connected to 6 collectors. These transistors Q
101 and Q102 form a differential logic circuit (first ECL circuit) for data signal input.

Transistors Q103 and Q104 are
The collectors are connected to the first power supply terminal 1 via resistors R101 and R102, respectively, and the emitters are connected to each other and to the collector of the transistor Q105. Further, the collector potential of the transistor Q102 is fed back to the base of the transistor Q103 by the transistor Q112 whose emitter is connected to the output terminal 9. The collector potential of the transistor Q101 is fed back to the base of the transistor Q104 by the transistor Q111. As a result, a differential logic circuit (second ECL circuit) for holding a data signal is formed.

Transistors Q105 and Q106 are
The bases are connected to the emitter of the emitter follower transistor Q108 for inputting the strobe signal and the second reference potential terminal 4, and the emitters are connected to each other and to the collector of the constant current source transistor Q107. As a result, a differential logic circuit (third ECL circuit) that inputs and holds and switches the data signal by the strobe signal is configured.

In the transistor Q110, the base is connected to the reset signal terminal 8 and the collector and the emitter are
Each is connected to the collector and the emitter of the transistor Q104.

The transistor Q123 has a base connected to the reset signal terminal 8, a collector connected to the first power supply terminal 1, and an emitter connected to the second power supply terminal 2 via the resistor R114. The transistor Q124 has a base at the emitter of the transistor Q123, a collector at the collector of the transistor Q104, and an emitter at the transistor Q10.
5 is connected to the emitter.

In the latch circuit having the above configuration,
The transistors Q101 to Q112 function similarly to the transistors Q201 to Q208 and Q210 to Q212 of the conventional latch circuit shown in FIG. Also, the resistor R1
01 to R105 function similarly to the resistors R201 to R205.

Next, the operation and action of the latch circuit of this embodiment constructed as described above will be described with reference to the truth table shown in FIG. In the latch circuit of this embodiment, when the reset signal is low level, the transistor Q
Since 124 is always in the off state, regarding the states of the strobe signal input terminal 6 and the data signal input terminal 7,
It operates exactly the same as the conventional latch circuit shown in FIG.

That is, when the strobe signal terminal 6 and the reset signal terminal 8 are in the low level state, the transistor Q105 turns off and the transistor Q106 turns on. At this time, a differential logic circuit (first ECL circuit) including the transistors Q101 and Q102 forms a data through circuit from the data signal terminal 7 to the output terminal 9 (a low-level strobe signal indicates a data through mode). Set). That is, the data signal input terminal 7
Is at a high level, the transistor Q101 turns on and the transistor Q102 turns off. This allows
A constant current (hereinafter, constant current I) generated by the transistor Q107 and the resistor R103 is
Since the potential of the power supply terminal 1 is applied to the base of the transistor Q112 through the paths of the transistors Q101 and Q106, the output terminal 9 is in the high level state (case 1).

On the contrary, when the data signal terminal 7 is in the low level state, the transistor Q101 turns off and the transistor Q102 turns on, and the constant current I passes through the path of the resistor R102, the transistors Q102 and Q106, and reaches the base of the transistor Q112. Since this potential is lower than that in case 1, the output terminal 9 is in a low level state (case 2).

Next, from this state, the strobe signal terminal 6
Goes to the high level state (from the data through mode to the latch mode), the transistor Q105 is turned on and the transistor Q106 is turned off, so that the level state of the output terminal 9, that is, the passage of the constant current I
It is determined by the base potentials of 10, Q103 and Q104. As described above, the base potentials of the transistors Q103 and Q104 are respectively set to the transistor Q10.
2 and the collector potential of Q101 are fed back, if the reset signal terminal 8 is in the low level state,
The current flowing through the resistor R101 or the resistor R102, that is, the level state of the output terminal 9 is determined by the strobe signal terminal 6
The state (Qn) before the high level state is maintained (case 3). That is, in this state, even if the state of the data signal terminal 7 changes, the level state of the output terminal 9 does not change.

When the strobe signal terminal 6 is in the high level state and the output terminal 9 is in the high level state in the latched state, the constant current I is the resistance R101 and the transistor Q10.
3 and the transistor Q105, the base potential of the transistor Q103 is in a high level state, and the base potential of the transistor Q104 is in a low level state.

In this state, when the reset signal terminal 8 changes from the low level state to the high level state, the transistor Q124 is turned on, so that part of the constant current I passes through the transistor Q124 and flows through the resistor R102. Become. As a result, the base potential of the transistor Q103 is level-shifted from the high level state to the low potential side by the voltage drop of the resistor R102. As a result, the base potential of the transistor Q103 becomes a low level state, and the transistor Q103 is turned off.

Further, since the base potential of the transistor Q110 is also in a high level state and is in an on state, the constant current I is applied to the transistors Q124, Q105 and its Q11.
The resistor R102 flows through the passage of 0, and as a result, the output terminal 9 is in a low level state (case 4). At this time, the base potential of the transistor Q104 is in the high level state.

When the reset signal terminal 8 changes from this state to the low level state, the transistor Q124 is turned off and the constant current I becomes equal to that of the transistors Q105 and Q.
104 and the resistor R102 through the output terminal 9
Holds the low level (case 5).

When the strobe signal terminal 6 is in the low level state and the reset signal terminal 8 is in the high level state, the constant current I is the transistor Q124 and the resistor R10.
The low level state of the output terminal 9 is maintained by passing through the passage 2 (case 6).

FIG. 2 shows the configuration of a basic cell 50 used when forming the latch circuit according to the above embodiment as a master slice type LSI. This basic cell 5
0 includes eight transistors T1 to T8, fourteen normal resistors P1 to P14, a first power supply line 51, second power supply lines 52 and 56, and first, second and third power supply lines. Reference potential line 5
3 to 55 are formed in advance.

In the figure, transistors T1 to T8 have contact holes for collector C, emitter E, and base B, respectively, and are arranged adjacent to each other and in a substantially rectangular shape.
These transistors T1 to T8 have an emitter E of 0.8.
The area occupied by the transistor is 6.4 μm × 8.3 μm≅52 μm ^2, which is molded to a size of μm × 2.2 μm.

The normal resistors P1 to P14 each have a layer resistance of 1.3 KΩ / mm ² , a resistance value of 4 KΩ, and an occupied area of 1
2.4 μm × 5.8 μm≈72 μm ² . The normal resistors P1 to P4 are arranged on the right side of the basic cell 50 so that one terminal is connected to the second power supply line 52, and the normal resistor P7 is provided.
P14 to P14 are arranged on the left side of the basic cell 50 so that one terminal is connected to the second power supply line 56. Normal resistance P5
And P6 have transistors T3 and T8 so that one terminal thereof is connected to the first power supply line 51.
Placed between.

The latch circuit (FIG. 1) according to the above embodiment is
Since it includes 13 transistors and 7 normal resistors, 7 is manufactured by connecting two basic cells 70a and 70b corresponding to the basic cell 50 shown in FIG. A configured common substrate is used (see FIG. 3).

FIG. 4 shows the common substrate (70a, 70a of FIG. 3).
The state where the wiring is actually applied is shown in b). In FIG. 4, transistors and resistors corresponding to those in FIG. 1 are designated by the same reference numerals.

In the basic cell 70a, the transistor T
701, T702, T704, T705, T706, T
707 and T708 are the transistors Q124 and Q of FIG.
123, Q106, Q101, Q103, and Q111, respectively. The one in which the normal resistors P703 and P704 are connected in parallel corresponds to the resistor R103, and the normal resistors P709, P714, and P706 are the resistors R114 and R1.
05 and R101, respectively.

In the basic cell 70b, transistors T721, T722, T723, T724, T725, and T725 are provided.
T728 is the transistor Q105, Q104,
Corresponding to Q112, Q110, Q102 and Q108 respectively, normal resistors P726, P732 and P725 are R11.
4, R116 and R112, respectively.

The area occupied by the latch circuit of the first embodiment of the present invention formed as described above is 1680 × 2 = 3.
The area occupied by the conventional latch circuit shown in FIG. 7 is 1920 × 2 = 3840 (μm ² ).
The occupied area on the chip can be reduced by 12.5% with respect to m ² ).

FIG. 5 shows the configuration of a circuit according to the second embodiment of the present invention. This circuit is a master-slave D-type flip-flop circuit with a reset terminal in which the latch circuit according to the first embodiment is applied to the master side. This circuit consists of 24 transistors Q3
01-Q324 and 12 normal resistors R301-R30
6, R309 to R314.

In this circuit, the transistor Q30
The reset signal 8 is input to the base 9 of the transistor 9, and the collector and the emitter thereof are connected to the collector and the emitter of the transistor Q308, respectively.

The operation of this circuit is similar to that of the conventional circuit shown in FIG. 12, and corresponds to the truth table of FIG. That is, on the master side, similarly to the latch circuit shown in FIG. 1, when the clock signal terminal 6 is in the high level state, it is in the latch state, and in the low level state, it is in the data through state. On the other hand, on the slave side, conversely, when the clock signal terminal 6 is in the high level state, it is in the data through state, and in the low level state, it is in the latch state. As a result, when the reset signal terminal 8 is in the high level state, the slave side is in the data through state.

In this circuit, the reset signal terminal 8
Since the transistor Q324 is always off when is in the low level state, the operation of a general master-slave D-type flip-flop that reads the state of the data signal terminal 7 when the clock signal terminal 6 rises is performed.

Next, when the reset signal terminal 8 is in the high level state, the master side performs the reset operation as shown in the first embodiment, the base potential of the transistor Q303 is in the low level state, and the base of the transistor Q304 is in the low level state. The potential is in a high level state.

At this time, the slave side has the transistor Q3.
09 is in the data through state because the base potential of 09 is high level, and the transistor Q319 and the resistor R3
The constant current I generated by 11 is applied to the transistor Q31.
8 and Q314 and the path of R310, the output terminal 9 becomes a low level state. When the reset signal terminal 8 changes from this state to the low level state, the slave side enters the latch state and the transistors Q315 and Q31
6, the low level state of the output terminal 9 is held.

FIG. 6 shows a configuration when the circuit shown in FIG. 5 is formed by the master slice method. Since the circuit shown in FIG. 5 uses 24 transistors and 12 normal resistors, the basic cell 50 shown in FIG.
It is configured by using individual pieces.

As with the first embodiment, the master-slave D-type flip-flop circuit according to the second embodiment of the present invention has a chip similar to that of the conventional circuit having the same function shown in FIG. 12.5% of the occupied area above
Can be reduced.

[0063]

As described above, according to the latch circuit of the present invention, since the level shift resistor is unnecessary, the basic cell area can be made small especially in the master slice type LSI, and the number of wiring channels is increased accordingly. Therefore, there is an effect that it is suitable for high integration of LSI.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a latch circuit according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an arrangement pattern of basic cells of the ECL circuit of the first embodiment.

FIG. 3 is a plan view showing a pattern of a common substrate in which two basic cells shown in FIG. 2 are arranged adjacent to each other.

FIG. 4 is a plan view showing a state in which wiring is provided on the substrate shown in FIG.

FIG. 5 is a circuit diagram showing a flip-flop of the present invention using the latch circuit of the first embodiment.

6 is a plan view showing an arrangement and connection pattern of the flip-flop circuit shown in FIG.

FIG. 7 is a circuit diagram showing a configuration of a conventional latch circuit.

8 is a truth table showing the operation of the latch circuit shown in FIGS. 1 and 7. FIG.

9 is a plan view showing an arrangement pattern of basic cells of the conventional latch circuit shown in FIG.

FIG. 10 is a plan view showing a pattern of a common substrate in which two basic cells shown in FIG. 9 are arranged adjacent to each other.

11 is a plan view showing a state where wiring is provided on the substrate shown in FIG.

12 is a circuit diagram showing a flip-flop using the conventional latch circuit shown in FIG.

FIG. 13 is a truth table of the flip-flop circuit shown in FIGS. 5 and 12;

14 is a plan view showing the layout and connection pattern of the flip-flop circuit shown in FIG.

[Description of Reference Signs] 1 first power supply terminal 2 second power supply terminal 3 first reference potential terminal 4 second reference potential terminal 5 third reference potential terminal 6 strobe signal terminal or clock signal terminal 7 data signal terminal 8 Reset Signal Terminal 9 Output Terminal 50, 60, 70a to 70c, 90a to 90c Basic Cell 51, 61, 71, 91 First Power Supply Line 52, 56, 62, 66, 72, 76, 92, 96
Second power supply line 53, 63, 73, 93 First reference potential line 54, 64, 74, 94 Second reference potential line 55, 65, 75, 95 Third reference potential line Q101 to Q108, Q110 Q112, Q123,
Q124, Q201 to Q212, Q301 to Q320,
Q323, Q324, Q401-Q420, T1-T
8, T701 to T708, T721 to T728, T90
1-T908, T921-T928 Transistors R101-R105, R114, R116, R201-
R206, R301 to R306, R309 to R314,
R401 to R406, R409 to R413 resistors P1 to P14, P701 to P714, P721 to P73
4, P901 to P914, P921 to P934 Normal resistors R207, R208, R407, R408, P15, P
715, P735, P915, P935 Level shift resistor

Claims (1)

[Claims] 1. A base receives a data signal and a collector
Is connected to the first power supply terminal via a resistor
And the base is connected to the first reference power supply terminal,
The collector is connected to the first power supply terminal via the second resistor.
And the emitter is connected to the emitter of the first transistor.
A first difference consisting of a second transistor connected to the
A dynamic logic circuit and a base connected to the collector of the second transistor.
The collector is connected to the first power supply terminal,
Is connected to the second power supply terminal via the third resistor
Both have a third transistor connected to the output terminal and
Is connected to the collector of the first transistor,
The collector is connected to the first power supply terminal and the emitter is
A first resistor connected to the second power supply terminal via a fourth resistor.
4 transistor and the base is the third transistor
Is connected to the emitter of the
A fifth transistor connected to the collector of the
Is connected to the emitter of the fourth transistor,
The collector is connected to the collector of the second transistor
The emitter is connected to the emitter of the fifth transistor.
Second differential logic consisting of a sixth transistor connected in series
The circuit and the base receive the strobe signal, and the collector receives the first signal.
Is connected to the power supply terminal of and the emitter is connected through the fifth resistor.
A seventh transistor connected to the second power supply terminal;
Is connected to the emitter of the seventh transistor,
The collectors are the emitters of the fifth and sixth transistors.
An eighth transistor connected to the
The collector is connected to the quasi power source terminal, and the collector is connected to the first and second
It is connected to the emitter of the transistor, and the emitter is
8th transistor connected to the emitter of the 8th transistor
Transistors and emitters of the eighth and ninth transistors
From a constant current source circuit connected to the second power supply terminal
And a third differential logic circuit
In the path, the base receives the reset signal and the collector receives the second signal.
And the collector of the sixth transistor, and the emitter
Connected to the emitters of the fifth and sixth transistors
And the base receives the reset signal, and the collector receives the first signal.
It is connected to the power supply terminal and the emitter is connected via the sixth resistor.
Eleventh transistor connected to the second power supply terminal
And the base is connected to the emitter of the eleventh transistor,
Collectors are collectors of the second and sixth transistors
And an emitter connected to the eighth and ninth transistors.
Has a twelfth transistor connected to the emitter of the
A latch circuit characterized in that