JPH0799637B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit read-only memory (ROM) having a high density.

[Prior Art] An example of a conventional semiconductor memory device is shown in FIG.
FIG. 1A shows an example of a pattern layout diagram of a memory array of a conventional MOS type ROM, and FIG. 1B shows an example of a circuit diagram of the memory array.

First, in FIG. 4 (a), W ₁ , W _2, ... W ₈ are, for example,
A word line made of polycrystalline silicon, which is used as a gate of a memory transistor. And 1
Is a channel region of the memory transistor. Further, b ₁ , b ₂ ... B ₆ are bit lines wired with, for example, aluminum metal, which is a portion where a memory transistor is formed, and forms a drain of the memory transistor through the contact hole 2. Connected to the diffusion layer 3. Reference numeral 4 denotes a diffusion layer forming the source of the memory transistor, and this diffusion layer 4 is connected to the source metal wiring S ₁ through the contact hole 2.

Next, in FIG. 4B, W ₁ , W ₂ and W 3 are word lines, and b ₁ , b ₂ and b ₃ are bit lines. The gates of the memory transistors are connected to word lines W _{1 to} W ₃ and the drains are connected to bit lines b _{1 to} b ₃ , respectively, and the source is GND (0V) in this circuit diagram.

Reading of a memory array arranged in this way is performed by reading a plurality of word lines W ₁ , W ₂ ... And bit lines b ₁ , b _2.
One line is selected from among the selected lines, and one memory transistor is selected at the intersection of the matrix of the selected word line and bit line. Then, depending on whether the threshold voltage of the selected memory transistor is lower or higher than the gate voltage, "0" or "corresponding to whether the memory transistor is ON in the conductive state or OFF in the non-conductive state. This is performed by reading 1-bit information of "1".

Therefore, writing to the memory transistor is performed by setting two kinds of threshold voltages, which are lower or higher than the gate voltage.

[Problems to be Solved by the Invention] Since the conventional semiconductor memory device, that is, the ROM memory array is configured as described above, when the memory array area is reduced, wafer manufacturing process parameters,
For example, the width and mutual spacing of polysilicon and metal wiring, the size of contact holes, etc. are only reduced by the improvement of the manufacturing precision, and the reduction rate is not higher than the proportional reduction by the improvement of the manufacturing precision. There was a problem.

On the other hand, the increase in memory capacity in recent years has been extremely rapid, and the rate of increase is larger than the reduction rate of the memory array described above. As a result, the chip area of the entire memory device, which occupies most of the memory array, increases the memory capacity. At the same time, it tended to increase.

And eventually, when the area of the integrated circuit chip increases,
There has been a problem that the yield rate of non-defective products per unit wafer decreases, and finally the manufacturing cost per non-defective product increases.

Now, the problem when the area of the memory array is reduced is further examined in depth as follows.

That is, when reducing the memory array area, the most difficult portion is the contact portion that connects the bit line to the diffusion layer forming the drain of the memory transistor. The contact hole is located at the mirror position of the two memory transistors that are mirror symmetrical, and also serves as the drain of the memory transistor paired by the mirror. The size of the contact hole itself and the distance between the contact hole and the gate are relatively smaller than those of other manufacturing parameters, and since only two memory transistors are used in common, the contact connected to the bit line is used. The number of holes is required to be half the number of word lines, and the increase in the number of word lines accompanying an increase in memory capacity simply causes a proportional increase.

The present invention has been made to solve the above problems, and has a memory array configuration in which the number of contact holes connected to a bit line of a memory is reduced, and the memory array area is more than a proportional reduction due to improvement in wafer process manufacturing accuracy. It is an object of the present invention to obtain a semiconductor memory device which is drastically downsized.

[Means for Solving the Problems] The semiconductor memory device according to the present invention has either a first threshold voltage or a second threshold voltage higher than the second threshold voltage. A matrix of a plurality of rows and a plurality of columns having a series body in which a plurality of transistors, which are set to a threshold voltage and serve as storage elements having storage information based on the set threshold voltage, are connected in series. The word arranged in the corresponding row when arranged above to receive the address signal and the received address signal indicates that all the transistors of the storage element group arranged in the corresponding row are in the non-selected state. The potentials of all the word lines in the line group are set to a first potential lower than the first threshold voltage, and one of the transistors in the memory element group arranged in the row corresponding to the received address signal is in the selected state. To show that The potential of the word line connected to the control electrode of the selected transistor in the word line group arranged in the corresponding row is set to the second threshold voltage between the first threshold voltage and the second threshold voltage. A plurality of word line selection circuits are provided to set the potential of the remaining word lines to the third potential that is higher than the second threshold voltage while setting the potentials.

[Operation] According to the present invention, since a plurality of transistors serving as storage elements are connected to a bit line in units of storage element groups each having a serial body connected in series, a contact hole for connecting to a bit line is provided in the storage element group. Only one is required for the multiple transistors that make up the.

When all the transistors of the memory element group are in the non-selected state, each word line selection circuit applies the first potential to the word lines to all the transistors and makes all the transistors non-conductive. That is, the third bit line has no effect on the bit line to which the storage element group is connected, and further, if any transistor of the storage element group is in the selected state, the word line for the unselected transistor is A potential is applied to bring a non-selected transistor into a conductive state so that the selected transistor is electrically connected directly between the bit line and the ground node, and the word line for the selected transistor is connected to the first line. 2 potential is applied, and the selected transistor is made conductive by the threshold voltage of the selected transistor. Occupies was read to the bit line information stored in the selected transistors tighten made conductive.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention. FIG. 1 (a) is a pattern layout diagram of a memory array and FIG. 1 (b) is a circuit diagram of the memory array. is there.

First, in FIG. 1A, W _1a , W _1b to W _4a , W _4b are word lines, and the word line W _{1a which} is the first word line and the word line W _1b which is the second word line. Is a word line group of a plurality of word line groups, and is arranged in the first row in this embodiment. Each of the two memory transistors connected in series is arranged in the first row. Used as a gate. Note that the same applies to W2a, W2b, ..., Each of which forms one word line group and is used as a gate of two memory transistors connected in series and arranged in a corresponding row.

In addition, each memory transistor is set to a threshold voltage of either the first threshold voltage or the second threshold voltage higher than the second threshold voltage, and the threshold voltage is set. The memory element functions as a memory element having memory information based on the threshold voltage, and two memory transistors connected in series constitute one memory element group. As is clear from FIG. Are arranged in a matrix of a plurality of rows and a plurality of columns.

Bits b ₁ to b ₆ are arranged in a plurality of columns, and each bit line is a drain that also serves as a bit line node through a contact hole 2 at one drain portion of a series-connected memory transistor arranged in a corresponding column. It is directly connected to the diffusion layer 3. The repetition of the contact hole 2 on the bit line is such that a pair of two memory transistors connected in series are arranged in a mirror-symmetrical manner so as to also serve as the contact hole 2, and eventually, four word lines are formed. The number of contact holes on the bit line is half that of the conventional example shown in FIG.

S ₁ is a metal wiring, and the metal wiring S ₁ is a source diffusion layer 4 which also serves as a ground node forming a source of the other memory transistor in which the contact hole of the drain of the two memory transistors connected in series is not formed. To the contact hole 2.

Next, in FIG. 1 (b), which is a circuit diagram of a memory array according to an embodiment of the present invention, W _1a , W _1b to W _3a , W _3b are word lines, and b ₁ to b ₃ are bit lines. is there. In the example of this figure, the source of the transistor on the side not connected to the bit line of the two memory transistors connected in series is set to the ground level (GND).

One memory element group composed of two memory transistors connected in series is arranged at the intersection of the word line group consisting of two word lines and the bit line, and each memory element group is a memory transistor. Each has 1-bit storage information, and as a result has 2-bit storage information. By connecting one of the drains of the two memory transistors connected in series to the bit line, the storage information of each of the two memory transistors of the storage element group can be read out to the bit line.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG.

FIG. 2 is a circuit diagram of a main part including a gate voltage generating circuit forming a memory array and a word line selecting circuit.

In FIG. 2, a portion 5 surrounded by a broken line is a NO that has been generally and conventionally used for selecting a word line.
In the R circuit decoder, the number of outputs is the same as the number of rows of the memory array, that is, the number of word line groups, and there are 2 ⁿ when receiving the address signals a ₁ to a _n .
A decoder unit corresponding to 2 ⁿ lines is provided, and one selected output, that is, the “H” level (voltage level of power supply voltage, for example, 5 V) is output from the decoder unit corresponding to the selected row. , The other (2 ⁿ -1) outputs, that is, the "L" level (GND level) is output from each of the decoder units corresponding to the unselected rows. Note that the word line is shown in FIG.
Only the decoder section provided corresponding to the word line group of the first row consisting of W _1a and W _1b is shown as a circuit diagram.

Then, two serially connected memory transistors, that is, memory element groups are selected by one selected by the NOR circuit decoder 5, and further, two memory transistors by another address signal (a _{0 in} FIG. 2) are selected. Two bits (2 bits (2
It is the stored information of "0" or 1 that each transistor has, and there are two types of stored information of "0" or 1) 1 bit information of the information can be obtained. The memory information of one of the transistors connected in series is obtained, and the memory information of the other transistor of the two transistors connected in series is obtained by the other of the two kinds of combinations, and as a result, 2-bit information is obtained. Will be done.

Therefore, from one bit line b ₁ , the total (2 ⁿ ×
2 = 2 ^{n + 1} ) bits of stored information will be obtained.

In the case of the fourth diagram of the above-mentioned conventional example (b), when the receiving the a _n from the address signal a ₀ as many this embodiment, 2 equal to this embodiment the number of word lines _{n + Since} it becomes one, 2 ^{n + 1} decoder outputs by the address signals a ₀ to a _n are given to the corresponding word lines, and 1-bit storage information is obtained by one memory transistor, so the total (2 ^{n + 1} The memory information of x1 = 2 ^{n + 1} ) bits is obtained from _one bit line b ₁ . That is, _assuming that the same number of address signals a ₀ to a _n are received also in this embodiment, the stored information obtained from one bit line is the same as that of the conventional example described above.

Next, in this embodiment, an operation of specifically obtaining information of 2 bits from two memory transistors connected in series forming one memory element group will be described.

An example is the combination table of the gate voltage generation circuit in the portion 6 surrounded by the broken line in FIG. 2 and the 2-bit information in the table below.

It should be noted that FIG. 2 shows the first line composed of word lines W _1a and W _1b .
Only the gate voltage generating portion provided corresponding to the word line group of the row is shown as a circuit diagram, and the gate voltage generating portion and the decoder portion of the NOR circuit decoder shown in FIG. This constitutes a word line selection circuit provided corresponding to the word line group.

The following table is for explaining the operation of the present invention. Input voltage (gate voltage) input to each gate of two series-connected memory transistors that constitute one memory element group.
7 is a table showing combinations of threshold voltages.

In this table, E ₁ = 1V, E ₂ = 3V, L ₁ = 2V, H ₁ = 5V.

Now, it is assumed that one of the memory transistors in the memory element group in the first row, which is connected in series, is selected by the address signals a ₀ to a _n . Then, the output N ₁ of the NOR circuit decoder becomes the selected line, and the output N ₁ becomes "H" level. The NAND circuit 7 that forms the gate voltage generation unit for the first row of the gate voltage generation circuit, to which the output N ₁ and the two inputs of the address signal a ₀ are input, has the output N ₁ at the “H” level. , An inverter circuit determined by the address signal a ₀ .

Then, the output 8 of the NAND circuit 7 and the output 10 of the inverter circuit 9 which receives the output 8 are input to the gates of two memory transistors connected in series, that is, to the word lines W1a and W1b.

Therefore, two kinds of gate voltages are applied to the two memory transistors connected in series by the address signal a ₀ , that is,
Either (H ₁ , L ₁ ) or (L ₁ , H ₁ ) shown in the above table is determined. Here, the important point of the present invention is the level of the second potential L ₁ . The conventional “H” level of the third potential H ₁ is 5 V, but the level of L ₁ is on the low threshold voltage side of the memory transistor (in this example, it means “0” of stored information). Second threshold voltage E ₁ (in this example, E ₁ = 1V) higher than the first threshold voltage E ₁ (in this example, meaning “1” of stored information). It must be lower than the threshold voltage E ₂ (E ₂ = 3V in this example).

Then, the L ₁ level voltage is applied to the NAND circuit 7 and the inverter 9
This can be realized relatively easily by adjusting the transistor size of the transistor forming the. In this embodiment, the second potential L ₁ = 2V and the third potential H ₁ = 5V are set.

Further, the threshold voltage of the memory transistor has a first threshold voltage E ₁ = 1V and a second threshold voltage higher than the first threshold voltage E ₁ = 1V.
The threshold voltage E _{2 of} E was set to 3V. This threshold voltage can also be realized relatively easily depending on the degree of ion implantation.

As described above, by combining the levels of the gate voltages of the two memory transistors connected in series and the levels of the threshold voltage of the memory transistors, as shown in the above table, the desired memory can be stored in each memory transistor. The following precautions should be taken when setting information, that is, writing.

That is, in the conventional one in which one transistor of 1-bit information is connected to the corresponding bit line, the threshold voltage of the corresponding one memory transistor is determined by the 1-bit stored information of 0 or 1. Bayoi is, in what is connected to a corresponding bit line as a single storage elements of two memory transistors connected in series of 2-bit information as described above embodiment, two bits determined by the address signal a ₀ (a 2 when ₀ is “L” and “H”
There are four combinations of threshold voltage levels of two memory transistors connected in series (as is clear from the above table (E ₂ , E ₂ ), (E ₁ ,
_{E 2), (E 2,} E 1), in one of four types) of (E _1, E _1), it is to be uniquely determined.

The threshold voltage setting method of one of the four types, that is, the writing method is shown in the example of the mask ROM by the ion implantation method. Remember the table, first, E _{1 for} all memory transistors
A mask is made so that the ion implantation can be applied only to the transistor that needs the threshold voltage of E ₂ by using one of the four types of writing that is based on the implantation amount that can be set to the threshold voltage of. After all, 1 injection mask
One of four types of threshold voltages can be set for two memory transistors connected in series that form one memory element group.

Therefore, as is clear from the above table, when (E ₂ , E ₂ ) is written, even if the address signal a ₀ is “L”, it is “H”.
In either case, either one of the two memory transistors connected in series is always in the non-conducting state, so that the bit line node (in other words, the bit line b ₁ ) of the memory element group composed of the two memory transistors connected in series is connected. And the ground node are turned off (non-conductive state).

When (E ₁ , E ₂ ) is written, the address signal a ₀ is “L”.
At this time, the transistor under the two memory transistors connected in series becomes non-conductive, so the bit line node of the storage element group and the ground node are in the OFF state (non-conductive state).
Therefore, when the address signal a ₀ is “H”, both of the two memory transistors connected in series become conductive, so that the bit line node of the storage element group and the ground node are turned on (conductive state).

When (E ₂ , E ₁ ) is written, the address signal a ₀ is “L”.
At this time, both of the two memory transistors connected in series become conductive, so that the bit line node of the storage element group and the ground node become ON (conductive), and the address signal a ₀
When "H" is "H", the upper transistor of the two memory transistors connected in series becomes non-conductive, so that the bit line node of the storage element group and the ground node are turned off (non-conductive state).

When (E ₁ , E ₁ ) is written, the address signal a ₀ is “L”.
In both the cases of "H" and "H", both of the two memory transistors connected in series become conductive, so that the bit line node of the storage element group and the ground node are in an ON state (conductive state).

In other words, when the address a ₀ is “L”, the gate voltage of the upper transistor of the two memory transistors connected in series is set to H ₁ , that is, the potential higher than the second threshold voltage, so that the upper memory is Since the transistor becomes conductive regardless of the set threshold voltage, the ON / OF state of the storage element group connected between the bit line node and the ground node
The F state is determined by the threshold voltage set in the transistor below the two memory transistors connected in series. Therefore, when the address a ₀ is “L”, it is equivalent to that the threshold voltage set in the lower memory transistor, that is, the stored information is read to the bit line b ₁ .

On the other hand, when the address a ₀ is “H”, the gate voltage of the lower transistor of the two memory transistors connected in series is set to H ₁ , so that the lower memory transistor is not affected by the set threshold voltage. Therefore, the memory element group connected between the bit line node and the ground node is turned on.
The N and OFF states are determined by the threshold voltage set in the transistor above the two memory transistors connected in series. Therefore, when the address a ₀ is “H”, it is equivalent to that the threshold voltage set in the upper memory transistor, that is, the stored information is read to the bit line b ₁ .

Therefore, 2-bit storage information is read by the address signal a ₀ from one storage element group composed of two memory transistors connected in series.

Next, the operation of the memory element group formed by two memory transistors connected in series in the non-selected line, that is, the non-selected row will be described.

Now, it is assumed that the two memory transistors connected in series in the memory element group in the first row are not selected by the address signals a ₀ to a _n . Then, the output N ₁ of the NOR circuit decoder becomes "L" level. The inverter 11 that constitutes the gate voltage generation unit for the first row of the gate voltage generation circuit that receives the "L" level of the output N ₁ gives the "H" level to the gate of the transistor 12, so that the transistor 12 is in the conductive state. Therefore, the gate voltages of the two memory transistors connected in series are both at the “L” level. As a result, the two memory transistors connected in series are turned off regardless of the set threshold voltage, are connected to the bit line b _{1, and} are connected to the bit line b ₁ of the storage element group located in the selected row. It has no effect on the reading to b ₁ .

The “L” level at this time is the lower one set in the memory transistor, that is, the first threshold voltage in this embodiment.
Transistor so that the first potential is lower than E ₁ = 1V
Twelve gate widths and gate lengths must be set.

In this way, one of the address signals related to the selection of the word line is used to determine the combination of two kinds of voltages applied to the gates of the memory transistors connected in series. As a result, two address signals are connected in series. It is used to select either one of the connected memory transistors, and writing of 2-bit storage information to two memory transistors connected in series is uniquely determined by the 2-bit information related to the one address signal. This is done by keeping the write information of one of the four types.

The decoder section of the NOR circuit decoder 5 and the gate voltage generating section of the gate voltage generating circuit 6 corresponding to the first row shown in FIG. a _{0 to} a _n indicate that all the transistors of the storage element group arranged in the corresponding row are in the non-selected state, and all the word lines W _{1a of} the word line group arranged in the corresponding row, The potential of W _1b is set to a first potential L lower than the first threshold voltage E ₁ of the memory transistor, and any of the memory element groups arranged in the row corresponding to the received address signal a _{0 to} a _n Indicates that the memory transistor is in the selected state, the potential of the word line connected to the gate electrode of the selected transistor in the word line group arranged in the corresponding row is set to the first threshold voltage of the memory transistor. E ₁ and the second threshold power Constitute a word line selection circuit for the potentials of the remaining word lines to a second third potential H ₁ higher than the threshold voltage E ₂ as well as to a second potential L ₁ between E ₂ It is a thing.

The circuit configuration of the gate voltage generating circuit 6 shown in FIG. 2 is an example, and the combination of the gate voltages of the two memory transistors connected in series by the address signal a ₀ needs to be limited to the above table. Instead, various circuit configurations are possible. What is required is that 2-bit information can be obtained by combining the gate voltage and the threshold voltage of two memory transistors connected in series.

As an example of another circuit configuration, an example in the case of a NAND circuit decoder is shown in FIG.

In Figure 3, those of Figure 2 and the same reference numerals indicate the corresponding parts, b ₁ is the bit _{line, W 1a, W 1b, W} 2a, W 2b is a word _{line, a 1, a 2, ......} a n Indicates an address signal.

The combinations of ON and OFF in the case of the circuit example shown in FIG. 3 are the same as those in the above table.

Although the threshold voltage of the memory transistor is set by the ion implantation method in FIG. 2, it is not limited to the ion implantation method as long as the threshold voltage can be changed. .

Furthermore, the combinations of signals in the table and L, L ₁ , H ₁ ,
Regarding the determination of the voltage levels of E ₁ and E ₂ , various combinations and voltage levels are conceivable as long as 2-bit information is obtained.
It is possible to have the same effect.

[Advantages of the Invention] As described above, the present invention provides a threshold voltage of either the first threshold voltage or the second threshold voltage higher than the second threshold voltage. And a storage element group having a series body in which a plurality of transistors, which are storage elements having storage information based on the set threshold voltage, are connected in series, are formed into a matrix of a plurality of rows and a plurality of columns. A word line group arranged in a corresponding row when arranged to receive an address signal and the received address signal indicates that all the transistors of the memory element group arranged in the corresponding row are in a non-selected state. The potentials of all the word lines are set to a first potential lower than the first threshold voltage, and one of the transistors of the memory element group arranged in the row corresponding to the received address signal is in the selected state. Is placed in the corresponding row The potential of the word line connected to the control electrode of the selected transistor in the selected word line group is set to the second potential between the first threshold voltage and the second threshold voltage, and Since the word line selection circuits for setting the potential of the word line to the third potential higher than the second threshold voltage are arranged in a plurality of rows, the contact hole for connecting to the bit line constitutes the memory element group. Only one is required for multiple transistors, contact holes can be reduced, the memory array area can be reduced, defects due to contact holes can be reduced, and all transistors in the memory element group are in the non-selected state. In this case, all the transistors are directly turned off by the corresponding word line selection circuit regardless of the set threshold voltage. It is connected to the bit line without adversely any effect on the corresponding bit line, and has the effect of reduction of the memory array area can be reduced also from this point.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing an extracted essential portion of the present invention, and FIG. 3 is a circuit showing another embodiment of the present invention. Figure, 4th
The figure shows an example of a conventional semiconductor memory device. 1 ... Memory transistor channel region, 2 ... Contact hole, 3 ... Drain diffusion layer, 4 ... Source diffusion layer, 5 ...
NOR circuit decoder, 6 ... Gate voltage generation circuit, 7 ... NAND
Circuit inverter, 9 and 11 ... inverter, 12 ... transistor, b ₁ ~b ₆ ... bit _{lines, W 1a, W 1b ~W 4a} , W 4b ... word lines, S ₁ ... source metal wiring.

Claims (2)

[Claims] 1. A plurality of rows and a plurality of columns are arranged in a matrix, each of which has a bit line node, a ground node, a first threshold voltage or a second threshold voltage higher than the first threshold voltage. And a series body in which a plurality of transistors serving as storage elements having storage information based on the set threshold voltage are connected in series. A plurality of storage elements, each series body being directly connected between a corresponding bit line node and a ground node, arranged in a plurality of columns, and a plurality of storage elements arranged in corresponding columns A plurality of bit lines directly connected to the bit line nodes of the group, arranged in a plurality of rows, each connected to a control electrode of a corresponding transistor of a plurality of storage element groups arranged in a corresponding row. Had multiple word lines The number of word line groups are arranged in a plurality of rows, each of which receives an address signal,
When the received address signal indicates that all the transistors of the storage element group arranged in the corresponding row are in the non-selected state, the potentials of all the word lines of the word line group arranged in the corresponding row are When the first potential lower than the first threshold voltage is set and the received address signal indicates that any one of the transistors of the memory element group arranged in the corresponding row is in the selected state, it is arranged in the corresponding row. The potential of the word line connected to the control electrode of the selected transistor in the provided word line group is set to the second potential between the first threshold voltage and the second threshold voltage. Also, a semiconductor memory device including a plurality of word line selection circuits that sets the potentials of the remaining word lines to a third potential higher than the second threshold voltage. 2. Each bit line is connected via a common contact hole to a bit line node of two storage element groups arranged adjacent to each other in the column direction of the corresponding column. The semiconductor memory device according to claim 1.