JPH0797806B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing apparatus.

[Conventional technology]

FIG. 10 is a control block diagram of a conventional image forming apparatus,
Reference numeral 51 denotes a reader, which is composed of an image pickup device 51a formed of, for example, a CCD, a buffer memory 51b holding an output of the image pickup device 51a, an image processing unit 51c, an image synchronization memory 51d, a control unit 51e, and the like.

Reference numeral 52 denotes a printer unit, which is a modulation circuit 52a that modulates the image signal output from the image synchronization memory 51d, and a laser that converts the modulation signal sent from the modulation circuit 52a into a drive signal for a laser (not shown), that is, an ON / OFF signal. Modulator 52b, controller
It is composed of 52c etc.

The optical image is read by the image pickup device 51a such as a contact CCD, and the read image data is serially stored in the memory, that is, the buffer memory 51b by the instruction of the control unit 51e, and further synchronized with the scanning drive system of the printer. Then, the image synchronization memory 51d for transmitting the read image is sequentially read from the buffer memory 51b, and the image signal is transmitted to the laser modulator 52b via the modulator circuit 52a of the printer unit 52, and the image is recorded on the recording medium, for example, recording paper. Is usually output.

In this case, read the image with a resolution of about 16dot / mm, and
If you try to achieve a throughput of 20 sheets per minute, 1 dot
The transfer time for each pixel is approximately 60 nsec. Image signals having such a transfer speed are sequentially sent out to the scanning drive system of the printer via each unit.

[Problems to be solved by the invention]

In the device configured as described above, it is necessary to check the communication state of the image signal. The reason is that during image signal transfer, particularly when converting parallel data to serial data in the buffer memory 51b, if noise is superimposed due to an external factor, for example, an image signal different from the read image is scan-driven by the printer. There is a problem that the image is transferred to the system and an unclear image effectively affected by noise is output. Therefore, when the above-mentioned symptoms appear in the image, a measuring instrument, for example, an oscilloscope or the like is connected to the main body of the apparatus, the input / output of the image signal is monitored, and the diagnosis of each unit is executed. As described above, the transfer time per dot of the image signal is about 60 nsec, and the image signal is uncertain, so that there is a problem that the accurate diagnosis of each unit cannot be performed. there were. In view of the above points, in the present invention, in converting image data input in parallel into serial image data,
A test signal for transmission error detection is synthesized with the image data,
Provided is an image processing device having a function of detecting a transmission error of an image signal, which is capable of minimizing a decrease in transmission efficiency of the image signal due to the test signal by removing a part of the test signal. The purpose is to do.

[Means for solving problems]

The image processing apparatus according to the present invention includes an input unit (corresponding to the contact type photoelectric device 1 in FIG. 1) that separates image data constituting one screen and inputs the image data in parallel through a plurality of channels, respectively. A plurality of synthesizing means (corresponding to the gate circuit 25 in FIG. 2) for synthesizing a predetermined test signal for transmission error detection with each of the image data input via the Converting means for converting the test signal into image data combined with the test signal, wherein at least a part of the test signal is removed and converted into serial image data including the test signal (FIG. 2). Gate circuit
26 and an OR gate 40) are provided.

[Embodiment] FIG. 1 is a block diagram of an image forming apparatus showing an embodiment of the present invention.
The analog signals V1 to V5 output from 1a to 1e are sent to the signal processing unit 2. The signal processing unit 2 samples and holds the analog signals V1 to V5, and outputs the analog signals V1 to V5 for five channels via the communication cable 3 to the image reading control unit 4.
Transfer to the A / D converter 4a. The connection memory 4b serves as a buffer, and aligns the A / D converted image signals. An image processing unit (IPU) 4c multivalues the image signal to convert it into a signal expressing a halftone, and also processes a color image signal, for example, image signal processing such as gamma conversion. Reference numeral 4d is a synchronous memory, which sends the image signal from the IPU 4c to the printer 5. A synchronous control circuit 4e controls I / O between the signal processing unit 2 and the connection memory 4b in accordance with a command from the control unit 4h. Four
f is a synchronization control circuit, which controls writing of the image signal read from the connection memory 4b to the IPU 4c. Reference numeral 4g is a synchronization control circuit, which controls writing of the image signal read from the IPU 4c into the synchronization memory 4d. It should be noted that the generic term of 1 to 4 is called a reader.

The printer 5 includes a modulation circuit 5a that modulates the image signal sent from the synchronous memory 4d, a laser modulation unit 5b that converts the modulation signal sent from the modulation circuit 5a into a laser drive signal (not shown), that is, a blinking signal, and a laser It is composed of a BD sensor 5c for detecting the scanning start position, a synchronization control circuit 5d, a control unit 5e and the like. An I / O port 6 is connected to the control unit 4h of the reader. An I / O port 7 is connected to the control unit 5e of the printer 5.

FIG. 2 is a block diagram showing the details of the connection memory 4b shown in FIG. 1. Reference numerals 11 and 12 denote bus switching ICs, and bus switching IC 1
An inverter 13 is connected between 1 and 12. Reference numerals 14 and 15 are buffer memories, and the inverter 16 and multiplexers 17 and 18 switch the read / write address of the image signal. A multiplexer 19 switches the channel select terminals CS of the buffer memories 14 and 15. A gate circuit 20 extracts only the test pattern portion of the output data. Reference numeral 21 is a gate circuit, which extracts only the reference pattern. Reference numeral 22 denotes a comparator, which compares the test pattern output from the buffer memories 14 and 15 with the reference pattern and extracts a signal that does not match, that is, an error portion. An error counter 23 counts an error portion output from the comparator 22. A latch circuit 24 holds the count value of the error counter 23 at the falling edge of a VSYNC signal (described later). A gate circuit 25 adds a test pattern. A gate circuit 26 removes the test pattern. 27 is an inverter circuit, 28 is a ROM, random data that is not aligned,
For example, a test pattern having a plurality of “01011” and “01100” is written in a small capacity. Reference numeral 29 is a ROM in which the reference pattern is written in the same manner as the test pattern. The random data written in the ROMs 28 and 29 are the same. Reference numeral 30 is a timing circuit forming the test pattern sending means of the present invention, which controls sending of random data written in the ROM 28 and inserts it in a section other than the image signal section in synchronization with the horizontal synchronizing signal (BD signal). A counter 31 counts the sub-scanning direction address of the test pattern in synchronization with the VSYNC signal. 32 and 33 are timing circuits,
Control the image effective area. 34 is a light counter, a bus
The write addresses of the buffer memories 14 and 15 are counted via 37. A read counter 36 counts the read addresses of the buffer memories 14 and 15 via the bus 35. 38 is an access controller, which is a buffer memory 14,1
5 access control. Reference numeral 39 is a main control unit which constitutes the signal judging means of the present invention, and judges the state of the transmission error from the preset error occurrence frequency from the count value input via the I / O port 6 and retransmits the test pattern. And the transmission quality is displayed on the display means of the operation unit (not shown). Further, the state of the transmission error is judged from the number of error occurrences set in advance, the possibility of restarting is judged, the sending of the image signal is suppressed, and the fact is displayed on the display means. Reference numeral 40 is an OR gate circuit, which sends the image signals for five channels input to the connection memory 4b to the printer 5. The connection memory 4b has the same structure as that of each channel, but only the channel 1a is shown for the sake of explanation.

In the image forming apparatus configured as described above, when the test pattern generated by the timing circuit 30 is written and transferred to the buffer memories 14 and 15 in synchronization with the image signal, the main control unit 39 causes the buffer memory 14 to operate. By determining the transmission error of the test pattern read from the test patterns 15 and 15 according to the procedure of the flowchart described later, the transmission state of the image data having a high transfer rate can be determined quickly and accurately.

Next, the operation of FIG. 2 will be described with reference to FIGS. 3 (a) to (c) and FIGS. 4 (a) to (h).

3 (a) to 3 (c) are buffer memories 1 shown in FIG.
6 is a time chart showing a relationship between an image signal written in 4, 15 and a test pattern.

In FIG. 3 (a), BD indicates a horizontal synchronizing signal sent from the BD sensor 5c, and in FIG. 3 (b), VIDEO is 5
The image signals for the channels are shown in FIG.
TP is a test pattern, which indicates the test pattern of the first line written in the ROM 28.

4 (a) to 4 (h) are the buffer memory 1 shown in FIG.
6 is a time chart showing the relationship between the image signals read from 4, 15 and a test pattern.

In FIG. 7A, CK is a read clock, which is input to the read counter 36. In FIG. 3B, CH ₁ is read data, and the test pattern TP is added to both sides of the analog signal V ₁ . In FIGS. 2B to 2F, CH ₂ and CH ₅ are read data, and each analog signal V 2 to V
The test pattern TP is added to both sides of 5. In the same figure (g), RV is the extracted image data, IPU4
sent to c. A test pattern is added to both sides of the extracted image data RV. In FIG. 7H, MV is effective image data and is sent to the synchronous memory 4d.

When the horizontal synchronization signal BD shown in FIG. 3 (a) is input to the synchronization control circuit 4e, the analog signals V1 to 1e output from the channels 1a to 1e of the contact photoelectric device 1 in synchronization with the horizontal synchronization signal BD. Random data of the first line of the test pattern written in ROM28 is added to both sides of the V5 section,
It is stored in parallel in the buffer memories 14 and 15. This operation is performed on the input image signal in synchronization with the horizontal synchronization signal BD. At this time, the test pattern TP is sequentially stored in the buffer memories 14 and 15 by adding different random data to the corresponding image signal from the ROM 28.

Then, in synchronization with the read clock CK (see FIG. 4A) input to the read counter 36, the buffer memory
Read data CH ₁ CH ₅ (see FIGS. 4B to 4F) read from channels 14 and 15 and corresponding to each of the channels 1a to 1e is transferred via the bus switching IC 12 and the gate circuit 20 to the comparator 22.
Entered in. On the other hand, the ROM
The reference pattern read out is input to the comparator 22 via the gate circuit 26. The reading of this reference pattern is controlled by the timing circuit 32, and the comparator 22 compares the test pattern TP which is the same random data. If the test patterns do not match as a result of this comparison, a predetermined pulse signal is output from the comparator 22. The error counter 23 counts this pulse signal, and the count value of the error counter 23 is held in the latch circuit 24 in synchronization with the VSYNC signal (see FIG. 5) indicating the end of the image in the sub-scanning direction. This latch output is judged by the main control unit 39 via the I / O port 6, and if the transmission error in one image is larger than a preset set value, the same image data is sent again and the memory 4b is connected. Command. Here, if the same transmission error is repeated a predetermined number of times, it is determined that the transmission error cannot be recovered,
This is displayed on the display unit of the operation unit (not shown) to warn the operator and stop the system. If the transmission error falls within the allowable range, the transmission of the image data is continued. This is to prevent the operation efficiency from being lowered by executing the image formation without stopping the system in the case of a transmission error to the extent that there is no problem in the output image.

It should be noted that the monitoring of the transmission error is configured so that the error count is not executed for an unnecessary area only in the image effective area (shown by diagonal lines) shown in FIG. Further, in FIG. 6, V1 indicates the sub-scanning range of the effective image area, V2 indicates the maximum sub-scanning range, H1 indicates the main scanning range of the effective image area, and H2 indicates the maximum main scanning range. .

Next, the system diagnostic control operation of the present invention will be described with reference to FIG.

FIG. 7 is a flow chart for explaining the system diagnostic control operation of the image forming apparatus showing the embodiment of the present invention. Note that (1) to (9) indicate each step.

First, waiting for the end of the copy-on determination routine (1), the test pattern written in the ROM 28 is added to both sides of the section of the analog signals V1 to V5, and the buffer memory 1
The test pattern sending routine for writing in the test patterns TP4, 15 is executed prior to the main image forming operation (2), and the test patterns TP are read from the buffer memories 14, 15 in synchronization with the read clock CK.
Is read out, the error counter 23 compares it with the reference pattern written in the ROM 29, and counts transmission errors. Next, after a lapse of a predetermined time, the main control unit 39 reads the number of transmission errors held in the latch circuit 24 (3), and determines whether the transmission error on the transmission path is within a preset allowable range. If YES (4), a normal copy operation is executed (5). At this time, buffers 14,1
5 has the test pattern T on both sides of read data CH _{1 to} CH _5.
It is stored with P added. Then, in parallel with writing to synchronous memory 4d of the read data CH ₁ to CH _5, it determines whether within the allowed range similar to that described above the transmission error is set in advance (6). In this judgment, if YES, return to step (1), and if NO,
It is judged whether or not a transmission error has occurred more than a preset number of times (7), the process returns to step (5) if NO, and proceeds to step (9) if YES.

On the other hand, in step (4), it is determined whether or not a transmission error has occurred more than a preset number of times (8). If NO, the process returns to step (2), and if YES, the display means (not shown) is displayed. The main control unit 39 displays a warning and judges that the transmission error recovery is not expected, and stops the system (9).

Next, the mutual operation of the reader unit and the printer 5 shown in FIG. 1 will be described with reference to FIG.

FIG. 8 is a flow chart for explaining the mutual operation of the reader unit and printer 5 shown in FIG. In addition, (1) ~
(8) shows each step.

The printer 5 first executes a communication routine for communicating image data from the reader unit (1), determines whether or not a print signal is sent from the reader unit (2), and if NO, stores the image data in a RAM (not shown). If YES, a transfer routine for starting transfer of image data is performed (3). Next, it is judged whether the transmission error of the image data is within the preset allowable range (4), YES
If so, the normal copy operation is executed and the process returns to step (1) (5). If NO, it is judged whether or not a transmission error has occurred more than a preset number of times (6). If YES, the reader communication routine fails. Then, a warning is displayed on the display means, a failure case for stopping the system is performed, and the control ends (7). On the other hand, if it is determined in step (6) that the transmission error is less than or equal to the preset number of times, the transmission error count is increased (8), and a request to transfer the image data from the reader unit is issued again to step (2). Return to and check the transmission error.

Although the case of a color image signal is not described in detail in the above embodiment, a transmission error can be similarly checked by providing a color separation filter on the contact photoelectric device 1 and converting the color signal into an RGB signal.

FIG. 9 is a cross-sectional view showing an embodiment of the image forming apparatus according to the present invention, 41 is a document, 42 is a reader section,
A platen glass 42a on which the document 41 is placed, a light source 42b for illuminating the document 41, a reflecting mirror 42c for collecting the light from the light source 42b, and a light source 42b.
A light converging lens 42d for condensing the original 41, a contact photoelectric conversion element 42e for converting the condensed light image into an electric signal, and a signal processing for waveform shaping the signal output from the contact photoelectric conversion element 42e. The circuit 42f, the transmission cable 42g for transmitting the signal output from the signal processing circuit 42f, the signal output from the signal processing circuit 42f is configured by an image reading control unit 42h that processes the signal and controls each part, and a wire. 44
The scanning table 43 connected to the shaft reciprocates in the arrow direction according to the rotation of the pulley 45. A motor 46 drives the pulley 45.

Reference numeral 47 denotes a printer unit, which is an interface circuit 47a for communicating signals output from the reader unit 42, and an interface circuit.
A laser modulator 47b that converts the signal output from 47a into a laser beam, a scanner unit 47c that scans the laser, a polygon mirror 47d that changes the direction of the scanned laser beam, a photosensitive drum 47e that forms a latent image by the laser beam, A charger 47f that charges the photosensitive drum 47e with electric charge, a developing device 47g that develops a latent image on the photosensitive drum 47e, a toner hopper 47h that supplies toner (development material) to the developing device 47g, a cassette 47i that stores recording paper, and a feeding device. Paper roller 47j, registration roller 47k for image alignment, transfer charger 47l for transferring toner image to recording paper, transport unit 47m for transporting recording paper on which toner is transferred, fixing transferred toner image and recording paper The fixing unit 47n includes a fixing unit 47n, a discharge tray 47o on which the fixed recording sheet is placed, a BD sensor 47p, and the like.

The image forming operation is based on a well-known electrophotographic method, and thus detailed description thereof is omitted.

〔The invention's effect〕

As described above, according to the present invention, it is possible to detect a transmission error of image data having a high transfer rate in each channel, and further remove at least a part of the test signal combined with the image data for detecting the transmission error. As a result, it is possible to minimize the decrease in the transmission efficiency of the image signal due to the test signal.

[Brief description of drawings]

1 is a configuration block diagram of an image forming apparatus showing an embodiment of the present invention, FIG. 2 is a configuration block diagram showing details of a connection memory shown in FIG. 1, and FIGS. 3 (a) to 3 (c) are A time chart showing the relationship between the image signal written in the connection memory shown in FIG. 2 and the test pattern, FIG.
(H) is a time chart showing the relationship between the image signal read from the connection memory shown in FIG. 2 and the test pattern, FIG. 5 is a time chart explaining the VSYNC signal that determines the effective image area, and FIG. 6 is effective. FIG. 7 is a schematic diagram illustrating an image area, and FIG. 7 is a flowchart illustrating a system diagnostic control operation of an image forming apparatus according to an embodiment of the present invention.
FIG. 8 is a flow chart for explaining the mutual operation of the reader unit and the printer shown in FIG. 1, FIG. 9 is a sectional view showing an embodiment of the image forming apparatus according to the present invention, and FIG. 10 is a conventional image forming apparatus. It is a control block diagram. In the figure, 1 is a contact-type photoelectric device, 2 is a signal processing unit, 3 is a communication cable, 4 is an image reading control unit, 4a is an A / D converter, 4
b is a connection memory, 4c is an image processing unit, 4d is a synchronous memory, 4e to 4g are synchronous control circuits, 4h is a control unit, 5 is a printer, 5a is a modulation circuit, 5b is a laser modulation unit, 5c is a BD sensor,
5d is a synchronous control circuit, 5e is a control unit, 11 and 12 are bus switching ICs, 1
3 is an inverter, 14 and 15 are buffer memories, 16 is an inverter, 17 to 19 are multiplexers, 20 and 21 are gate circuits, 22
Is a comparator, 23 is an error counter, 24 is a latch circuit, 28 and 29 are ROMs, 30 is a timing circuit, and 39 is a main controller.

Claims (1)

[Claims] 1. An input unit for dividing image data constituting one screen and inputting the image data in parallel through a plurality of channels, and a predetermined value for each of the image data input through a plurality of channels by the input unit. A plurality of synthesizing means for synthesizing a test signal for transmission error detection, which are input in parallel through the plurality of channels, and are connected by the plurality of synthesizing means to combine the respective image data and serialized. An image processing apparatus, comprising: a unit for converting into image data, and a conversion unit for removing at least a part of the test signal and converting into serial image data including the test signal.