JPH0795201A - Cell canceling method and circuit for atm transmission system - Google Patents

Abstract

(57) [Abstract] [Objective] Regarding a method and circuit for discarding error cells in an ATM transmission system, a delay circuit on the input side can be omitted, and space can be saved and cost can be reduced. And to provide a circuit. [Structure] On the write side of the dual port RAM 2, the header error is detected and the error detection result is written to the dual port RAM 2 together with the input cell, and on the read side of the dual port RAM 2, the dual port R
The read cell read from the AM2 is read to detect the header error occurring in the dual port RAM 2, and the error detection result before the write is also read.
The cells are collectively discarded based on the error detection result before writing to the dual port RAM 2 and the error detection result after reading from the dual port RAM 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and circuit for discarding transmission data, and more particularly to a method and circuit for discarding error cells in an ATM transmission system.

[0002]

2. Description of the Related Art The ATM transmission system uses a predetermined amount (53 octets) of a transmission unit called a cell, which is a head portion (header: 5).
Data required for control such as a transmission destination address is placed in octets, and original data is placed in the remaining portion (48 octets) for transmission.

Therefore, if an error occurs in the header portion for some reason, the cell may have a wrong transmission destination or may not be able to restore the original data. Therefore, in the ATM transmission method, it is detected whether or not an error has occurred in the header of the cell transmitted at the time of clock rearrangement (at the time of relaying), and the cell in which the error has occurred is discarded.

FIG. 4 is a block diagram showing a conventional error discard circuit, and FIG. 5 is a time chart thereof. In synchronization with the input cell enable signal Se ₀ (FIG. 5 (a)), the input cell D _{0 and the} input error detection circuit 1 together with the parity bit.
To the dual port RAM 2 and the error in the header generated on the transmission path is detected. When an error is detected by the input error detection circuit 1, the output error signal E ₀ (FIG. 5 (b)) becomes “0”, and the error signal E ₀ is input to the write controller 3.

In the write controller 3, the write enable signal We and the write address Wa (broken line in FIGS. 5D and 5E) are formed, while the input cell D ₀ is transferred to the dual port RAM 2 via the delay circuit 10. Unless an error is detected by the error detection means 1, it is written in a predetermined address of the dual port RAM 2 in accordance with the write enable signal We and the write address signal Wa. The delay time in the delay circuit 10 is the header processing time in the input error detecting means 1 as shown in FIG. 5 (f).

By the way, in the above configuration, when an error is detected by the input error detection circuit 1 and the error signal E ₀ becomes "0", the controller 3 does not form the write address Wa and the write enable signal We as shown in FIG. And in this case dual port RAM2
The above-mentioned error cell is not written in and is discarded.

When the input cell D ₀ is written in the dual port RAM 2 via the delay circuit 10, the parity bit Pa formed in the parity bit adding circuit 6 is added and written in the dual port RAM 2, and Used to detect header errors on read as described.

As described above, the dual port RAM 2
The parity bit Pa and the input cell D ₀ written in are read by the read address Ra formed by the read controller 4 and the read enable signal Re and become a read cell D ₁₀ (FIG. 5 (g)). Is input to the output error detection circuit 7.

Thus, the read cell D ₁₀ input to the output error detection circuit 7 is subjected to error detection here, and when there is an error, the error signal E which is the output thereof.
₁ (FIG. 5 (h)) is set to "0" and input to the mask circuit 9.

On the other hand, the read cell D ₁₀ read from the dual port RAM 2 is also input to the delay circuit 8 and the time during which the output error detection circuit 7 detects an error in the header portion (FIG. 5 (g)). (see (j)),
It is input to the mask circuit 9.

The mask circuit 9 receives "0" of the error signal E ₁ and receives the cell enable signal Se ₁ (FIG. 5 (i)).
Is set to "0", and the read cell D ₁₀ from the delay circuit 8 is masked.

When the error signal E ₁ is "1", the cell enable signal Se ₁ also becomes "1", the read cell D ₁₀ becomes the output cell D ₁ (FIG. 5 (j)), and the mask circuit 9 Will be output more.

The buffer monitoring means 5 in FIG.
The write address and the read address are instructed to the write controller 3 and the read controller 4 while monitoring the write amount and the read amount.

[0014]

According to the above-mentioned conventional circuit, the input circuit D ₀ written in the dual port RAM 2 and the processing in the error detecting means 1 in the input side delay circuit 10 is performed.
In addition to synchronizing with the input timing of
The delay circuit 8 on the output side performs the same processing.

Therefore, the delay circuits 10 and 8 are required on both the input side and the output side, which increases the mounting area and is disadvantageous in terms of cost. In addition, a relatively high frequency is generally used for the transmission speed on the transmission line,
In the signal processing circuit, the circuit operation cannot follow unless the frequency is lower. Therefore, a plurality of clock shifting circuits are prepared in parallel for one transmission line so that they can cope with the above speed differences. Therefore, the delay circuit 10,
Naturally, the number of 8 also increases, and the above disadvantages in terms of mounting and cost further increase.

The present invention has been proposed in view of the above conventional circumstances, and of the input side and output side delay circuits which have a large mounting area and are expensive, the input side delay circuit can be omitted, It is an object of the present invention to provide a cell discarding method and circuit of the ATM transmission method which can achieve space saving and cost reduction.

[0017]

The present invention employs the following means in order to achieve the above object. That is, FIG.
As shown in, dual port R for clock replacement
A dual cell discard method in an ATM transmission system, which includes an AM2, detects header errors of an input cell written in the dual port RAM 12 and a read cell read from the dual port RAM 2, and discards the cell in which the error occurs. On the write side of the port RAM2, the header error is detected and the dual port R
Write the error detection result to the AM2 together with the input cell,
The read side of the dual port RAM 2 detects the header error generated in the dual port RAM 2 from the cells read from the dual port RAM 2 and
The error detection result before the writing is also read, and the cells are collectively discarded based on the error detection result before the writing to the dual port RAM 2 and the error detection result after the reading from the dual port RAM 2. Is.

To implement the above method, the present invention uses the following apparatus. That is, the above dual port RA
The input error detecting means 1 read from the dual port RAM 2 is configured so that the detection result of the input error detecting means 1 can be written in M2 corresponding to the input cell.
And the masking means 9 for collectively discarding the cells in error based on the detection result by the output error detecting means 7 and the detection result by the output error detecting means 7.

The mask means 9 has the dual port RAM 2 showing the detection result of the input error detecting means 1.
The read error signal E ₁₀ read from the output error signal E ₁ indicating the detection result by the output error detection means 7
And the read cell D ₁₀ read from the dual port RAM 2 must be input at the same time.

[0020]

The detection result of the input error detecting means 1 is written in the dual port RAM 2 together with the input cell D ₀ .
However, in this case, the error signal E ₀ indicating the detection result is written to the input cell D ₀ with a delay of a predetermined time (processing time of the input error detecting means 1).

Input cell D from dual port RAM 2
At the time of reading ₀ , the output error detecting means 7 is the same as the conventional one.
The error signal is detected by the error signal E _{1 and the} error signal E ₁ indicating the detection result is input to the mask means 9. At the same time when the input cell is read from the dual port RAM 2, the error signal E ₀ detected before writing to the dual port RAM 2 is also read and input to the mask means 9.

The read cell D ₁₀ read from the dual port RAM 2 is input to the mask means 9 at the same time as the output side error signal E _{1 after} delaying the processing time by the output error detection means 7. On the other hand, since the error signal E ₀ on the input side is written with a delay of the processing time in the error detecting means 1 when being written in the dual port RAM 2, it is read with the same time delay when being read from the dual port RAM 2. As a result, the mask means 9 has a read cell D ₁₀ , an error signal E ₀ ,
E ₁ is input at the same time.

As a result, the mask means 9 receives an input error.
Signal E₀Or output error signal E ₁One of the Ella
Is displayed (when it is “0”),
Masked and not output (discarded).

[0024]

FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is the time chart. Input cell D₀(Fig. 3
(b) is the cell enable signal Se₀Synchronized with (Fig. 3 (a))
Input to the input error detection means 1 and the header error is detected here.
Error is detected and error signal E₀(Fig. 3 (c))
Input to the report port RAM2. Here, the error signal E ₀
Is "0" when there is a header error. Meanwhile, input
Cell D₀Is input to the dual port RAM2
To the input cell D₀Parity corresponding to each octet of
The parity bit Pa added by the bit adding means 6 is also
It is input to the dual port RAM 2. In this way
The parity bit input to the dual port RAM2
Input cell D₀, Error signal E₀Is the above cell
Bull signal Se₀Write controller that operates in synchronization with
Write enable signal We output from the means 3,
Based on the write address Wa (Figs. 3 (d) and (e)), the du
It is written in the Alport RAM 2.

Here, the input error detecting means 1 detects the error in the header portion of the input cell D ₀ and then outputs the error signal E.
Outputs ₀ . Therefore, the error signal E ₀ is written in the dual port RAM 2 with a delay of the header (5 octets) with respect to the input cell D ₀ .

On the other hand, as described above, the dual port R
Input cell D ₀ and error signal E ₀ written in AM2
Is read based on the read enable signal Re and the read address Ra generated by the read controller 4, and becomes a read cell D ₁₀ (FIG. 3 (f)) and a read error signal E ₁₀ .

The parity bit Pa and the read cell D ₁₀ read from the dual port RAM 2 are input to the output error detection means 7, where an error is detected and an error signal E ₁ (FIG. 3 (f)) is output. Then, the error signal E ₁ is input to the mask means 9. Here, when an error has occurred, the error signal E ₁ becomes "0".

On the other hand, the read cell D ₁₀ is a delay circuit 8,
The header detection processing time in the output error detection means 7 is delayed and input to the mask means 9. Further, the read error signal E ₁₀ is directly input to the mask means 9.

Since the error signal E ₀ is delayed by the header error detection processing time in the input error detection means 1 (the same as the processing time in the output error detection means 7) at the time of writing, the mask means 9 reads out the error signal E _0. Error signal E
₁₀ (FIG. 3 (g)), the read cell D ₁₀ delayed by the delay circuit 8, and the output error signal E ₁ are simultaneously input.

As a result, the masking means 9 considers that the corresponding read cell D ₁₀ is defective when either the read error signal E ₁₀ or the output error signal E ₁ becomes "0", and masks the cell. At the same time (discard), the output cell enable signal Se _{1 is set} to “0”. Therefore, when a header error occurs on either the input side or the output side, the cell in which the error has occurred is discarded.

The above processing is carried out in parallel due to the difference in transmission speed and processing speed in the circuit of the present application, and when there is a defective cell, the plural information is collected by the alarm information collecting means 20 to issue an alarm or the like. To be

[0032]

As described above, according to the present invention, since the delay circuit on the input side can be omitted, the device can be downsized and the cost can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a principle view of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a time chart of the present invention.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a time chart of a conventional example.

[Explanation of symbols]

1 Input Error Detection Means 2 Dual Port RAM 7 Output Error Detection Means 9 Mask Means E ₁ Output Error Signals E ₁₀ Read Error Signals

Claims (3)

[Claims] 1. A dual port R for clock replacement.
An ATM equipped with an AM (2), which detects a header error of an input cell written in the dual port RAM (2) and a read cell read from the dual port RAM (2) and discards the cell in which the error occurs. In the cell discard method in the transmission method, on the write side of the dual port RAM (2), the above header error is detected and the error detection result is written to the dual port RAM (2) together with the input cell, and the dual port RAM (2) On the read side, the read cell read from the dual port RAM (2) is read to detect the header error occurring in the dual port RAM (2), and the error detection result before the write is also read. Error detection result before writing to (2) and after reading from dual port RAM (2) Based on the error detection result, the cell discard method in ATM transmission system, which comprises carrying out in a batch cell discard. 2. A dual port R for clock replacement.
AM (2), an input error detecting means (1) for detecting a header error of an input cell before writing to the dual port RAM (2), and a header of a read cell after reading from the dual port RAM (2). An output error detecting means (7) for detecting an error is provided, and the above two error detecting means are provided.
As a result of the header error detection by (1) and (7), in the cell discard circuit in the ATM transmission system that discards the input cell or read cell in which an error has occurred, the detection result of the input error detection means (1) is set to the input cell. The above dual port RAM that can be written in correspondence (2)
And the detection result of the input error detection means (1) read from the dual port RAM (2) and the detection result of the output error detection means (7), the cells in which an error has occurred are grouped together. A cell discarding circuit in the ATM transmission system, which comprises a masking means (9) for discarding the cells. 3. A read error signal (E ₁₀ ) read from the dual port RAM (2) indicating the detection result of the input error detection means (1), and the output error detection means.
The output error signal (E ₁ ) indicating the detection result by (7) and the read cell (D) read from the dual port RAM (2).
The discard circuit in the ATM transmission system according to claim 2, wherein ₁₀ ) and ₁₀ ) are simultaneously input to the mask means (9).