JPH0793249A - Cpu board provided with extended bus and in-circuit emulator - Google Patents

Abstract

PURPOSE:To provide the CPU board capable of switching access at high speed. CONSTITUTION:When an extended device is accessed, a gate control signal is turned to an 'L' level and outputted to a gate control line 34 by a switching control circuit 48. Thus, since the gate of an AND circuit 38 is closed, a control signal outputted from a CPU 2 and required for access is not applied to an object equipment. Therefore, only the extended device is accessed. On the other hand, when the object device is accessed, the gate control signal is turned to an 'H' level and outputted to the gate control line 34 by the switching control circuit 48. Thus, since the gate of the AND circuit 38 is opened, the signal of an in-board control line 32 is outputted to a plug 14 as it is. Namely, the control signal outputted from the CPU 2 and required for access is applied to the object device.

Description

Detailed Description of the Invention

[0001]

This invention relates to a CP having an expansion bus.
The present invention relates to a U board, and more particularly to speeding up bus switching.

[0002]

2. Description of the Related Art FIG. 8 shows a block diagram of a conventional CPU board. This CPU board is a target device (not shown)
Pull out the CPU of the computer from the socket,
The plug 14 is used by inserting it into this socket. As a result, new bus lines 10a, 12a
Can be added to add an expansion device (such as a memory or an input / output device). That is, the expansion device can be connected to the connector 16 for use. Further, by using a CPU 2 having a higher speed than the CPU of the target device,
The processing speed can be improved. 18 and 2
Reference numerals 0, 18a, and 20a are control signal lines for sending control signals.

By using the CPU board as described above, a new address bus 12a and data bus 10a can be obtained. However, the address of the expansion device connected to the new address bus 12a and the new data bus 10a will overlap the address of the target device. Therefore, when accessing the expansion device, the address bus 12 and the data bus 10 connected to the target device must be disconnected. Otherwise, when the expansion device is accessed, the target device is also accessed at the same time, and normal operation cannot be guaranteed.

In order to perform such switching, the conventional CP
On the U board, a switching control circuit 8 and buffers 4 and 6 are provided. The switching control circuit 8 inputs address information from the address bus 12a and determines whether the address is an address assigned to the expansion device. That is, it is determined whether the expansion device has been accessed. Buffer control line 2 if the expansion unit is accessed
The buffers 4 and 6 are controlled via 2 to bring the buffers 4 and 6 into a non-conducting state. As a result, the CPU 2 is separated from the data bus and address bus of the target device. On the other hand, when the expansion device is not accessed, the switching control circuit 8 controls the buffers 4 and 6 in the conductive state. As a result, the CPU 2 is connected to the data bus and address bus of the target device.

As described above, the buffers 4 and 6 are controlled to be conductive or non-conductive according to the address, so that access to the target device and access to the expansion device can be switched at high speed.

[0006]

However, the conventional CPU board as described above has the following problems.

In recent years, the operating speed of CPUs has increased. Therefore, the buffers 4 and 6 for disconnecting the bus line also need to operate at high speed in accordance with this. However, since the bus line is composed of a large number of lines and the mutual capacitances are large, there is a limit to speeding up the buffer control signal. Especially, when the bus width is increased (the number of lines is increased) due to the speeding up of the processing, it is all the more serious.

Also, a buffer must be provided for each of a large number of lines, and as the bus width increases,
There is also a problem that the circuit configuration becomes complicated.

An object of the present invention is to solve the above problems and provide a CPU board capable of switching access at high speed.

[0010]

According to another aspect of the CPU board of the present invention, the target device and the CPU are substantially directly connected to each other without providing a buffer in the bus line in the board.
A gate circuit is provided in one or more on-board control signal lines necessary for accessing the target device among the on-board control signal lines, and the gate circuit is closed when the CPU accesses the expansion device. It has a feature.

According to a second aspect of the in-circuit emulator, an emulation circuit necessary for emulating a part or all of the target device is connected to the extension bus line and the extension control line of the CPU board of the first aspect. It is characterized by being configured.

[0012]

According to the present invention, the bus line terminal and the CPU are substantially directly connected without providing a buffer in the on-board bus line, and the gate circuit is provided in the on-board control signal line necessary for accessing the target device. Is provided, and the switching control circuit controls the gate circuit.
When accessing the expansion device, the switching control circuit
The gate circuit is turned off and the control signal is not given to the target device. Therefore, even if the CPU and the target device are connected by the bus line, the target device is not accessed.
In other words, without providing a buffer in the bus line on the board,
The access to the target device and the expansion device can be switched, and the speed can be increased.

[0013]

1 is a block diagram of a CPU board according to an embodiment of the present invention. The in-board data bus 10 and the in-board address bus 12 (in-board bus line) are output from the CPU 2 and are directly connected to the plug 14. The plug 14 is a kind of connector having the same shape as the pin of the CPU of the target device (not shown). At the time of use, the CPU of the target device is pulled out from the socket, and the plug 14 is inserted instead.

From the CPU 2, the control signal line 3
0 and 32 are issued. The CPU 2 performs necessary control by the control signal lines 30 and 32. The control signal line 32 is a control signal line (at least one) required to access each address. The control signal lines 30 are all control signal lines except the control signal line 32 among the control signal lines necessary for the CPU 2 to perform control. The control signal line 30 is the plug 14
The control signal line 32 is connected to the plug 14 via an AND circuit 38 which is a gate circuit.

The on-board data bus 10 and the on-board address bus 12 are branched into an extended data bus 10a and an extended address bus 10b, respectively. In addition, the control signal lines 30 and 32 are respectively branched,
These are extended control signal lines 30a and 30b. The extension data bus 10a, the extension address bus 10b, and the extension control signal lines 30a and 30b are connected to the connector 16. At the time of use, an expansion device (not shown) such as a memory or an input / output device is connected to the expansion connector 16 for use.

Further, a switching control circuit 48 is provided on this CPU board. The switching control circuit 48 is provided with a part or all of the extended address bus 12a,
Part or all of the control signal from the CPU 2 is given. In response to this, the switching control circuit 48 determines whether the CPU 2 is trying to access the expansion device or the target device. When accessing the expansion unit,
The switching control circuit 48 sets the gate control signal to the “L” level and outputs it to the gate control line 34. As a result, the gate of the AND circuit 38 is closed, so that the signal of the in-board control line 32 is not output to the plug 14. That is,
The control signal required for access issued from the CPU 2 is not given to the target device. Therefore, only the expansion device is accessed.

On the other hand, when the target device is accessed, the switching control circuit 48 sets the gate control signal to the "H" level and outputs it to the gate control line 34. As a result, the gate of the AND circuit 38 is opened, and the signal of the in-board control line 32 is directly output to the plug 14.
That is, the control signal necessary for access issued from the CPU 2 is given to the target device. At this time, a control signal necessary for access is also given to the expansion device, but since the address of the expansion device is not accessed, only the target device is accessed.

As described above, the access between the target device and the expansion device can be switched. AND circuit 38
The number of control signal lines to be gated by means of one to several lines is sufficient, and not only high-speed control is possible, but also the circuit can be simplified.

FIG. 2 shows an I embodying the block diagram of FIG.
An example of the C board 54 is shown. Here, a 32-bit CPU2 (for example, Intel's 486DX is used.
2) is used. The IC board 54 is connected to the target device by the plug 14. In this figure, only the memory of the target device is shown, and other parts are omitted. The entire display of the expansion device is omitted.

In this embodiment, the address strobe signal ADS among the control signals is controlled by the gate circuit 38. The control signal W / R is a signal indicating whether the reading or writing is performed.

The operation of the circuit of FIG. 2 will be described. First, the case of accessing the target device will be described. The data signal DATA and the control signal W / R of the CPU 2 are given to the memory 52 of the target device via the plug 14. The upper bits of the address signal ADDRES are decoded by the decoder 50 and given to the chip select terminal CS of the memory 52. That is, in the address area assigned to the memory 52, the decoder 50 outputs and the memory 52 becomes operable. Address signal AD
The lower bits of DRES are directly provided to the memory 52.

The address strobe signal ADS is given to the memory 52 via the gate circuit 38. The gate circuit 38 is controlled by the output of the switching control circuit 48. The switching control circuit 48 has an address signal ADDR.
Control signal CTL from upper bit of ES and CPU2
1 to CTLn are given.

The switching control circuit 48, based on these,
It is determined whether to access the target device or the expansion device. When the target device is accessed, the output is “H”, and when the expansion device is accessed, the output is “L”. Here, since the target device is accessed, the output becomes "H" and the gate 38 is opened. Therefore, the address strobe signal ADS is stored in the memory 52.
Given to.

The write operation and the read operation will be described with reference to FIG. In the time chart of FIG. 3, CLK is an operation clock of the CPU 2. First, the CPU 2 sets the address strobe signal ADS to the “L” level in the cycle T1 (α in FIG. 3). As a result, the address input of the memory 52 becomes valid. In addition, the CPU 2
In order to clarify that it is a read operation, the control signal W / R is set to the “L” level (β in FIG. 3). Also, CP
The address signal ADDRES is output from U2 and applied to the memory 52. Then, the data is read through the data bus 12 (γ in FIG. 3). The same applies to the write operation.

Next, the case of accessing the expansion device will be described. In this case, the output from the switching control circuit 48 becomes "L". Therefore, the gate of the gate circuit 38 is closed. The timing chart of the operation in this case,
As shown in FIG. The address signal ADDRES and the control signal W / R are supplied to the memory 52 of the target device, but the address strobe signal ADS remains "H". Therefore, the bus cycle of the memory 52 is not valid, and no data signal is output from the memory 52 to the data bus 12.

On the other hand, since the address strobe signal is applied to the expansion device, the data signal is output from the memory of the expansion device to the data bus 12a. Therefore, the CPU 2 reads data from the expansion device side. It should be noted that the write operation is similarly performed on the side of the expansion device.

In FIG. 5, the extension device has an address of 800,000.
An example of the switching control circuit 48 used when allocating a memory of 00H or more is shown. In this example, the most significant bit A31 of the address signal ADDRES and the memory / IO
The switching control signal M / IO is applied to the NAND circuit 90 of the switching control circuit 48. Memory / IO switching control signal M
/ IO is "H" when accessing the memory,
This is a control signal which becomes “L” when accessing the input / output device. Therefore, when the memory is accessed and an address of 80000000H or more is accessed, the output of the switching control circuit 48 becomes "L" and the AND gate 38 is closed.

By the way, the drive capacity of the extended memory bus 10a and the extended data bus 10b may be insufficient depending on the type of connected expansion device. In such a case, as shown in FIG.
Should be provided.

In the above embodiment, the address strobe signal ADS is controlled by the gate circuit 38. However, CPU2 that does not have such a signal
When using, a read signal and a write signal may be used.

In each of the above embodiments, the gate circuit is switched by the control signal from the CPU 2 and the address signal, but the gate circuit may be switched only by the address signal or only the control signal.

Further, in the above embodiment, no buffer is provided on the on-board bus lines 10 and 12, and the CPU 2 and the target device are directly connected. However, the CPU 2 and the target device may be substantially directly connected within the range in which the effect of the present invention can be obtained. For example, the in-board bus lines 10 and 12 may be provided with a protection circuit or a terminator composed of resistors, capacitors, diodes and the like.

FIG. 7 shows a CPU board 54 according to the present invention.
An example of an in-circuit emulator using is shown. The plug (emulation terminal) 14 of the CPU board 54 is the target device 10 that is the target device.
0 IC socket. The expansion connector 16 of the CPU board 54 has an I / O circuit 102 for emulation, a memory 104, and a break point control circuit 1.
06 etc. are connected. With these, the target device 1
Emulates the 00 CPU. In particular, the CPU board according to the present invention is capable of emulating a high-speed CPU because the access is switched quickly.

The expansion connector 16 is omitted,
A circuit for emulation may be formed on the CPU board 54.

[0034]

According to the present invention, the bus line terminal and the CPU are substantially directly connected without providing a buffer in the on-board bus line, and the on-board control signal line necessary for accessing the target device is provided. A gate circuit is provided and the switching control circuit controls the gate circuit. Therefore, access to the target device and the expansion device can be switched without providing a buffer in the on-board bus line, and the speed can be increased.

That is, according to the present invention, it is possible to provide a CPU board and an in-circuit emulator capable of switching access at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a CPU board according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example in which the block diagram of FIG. 1 is embodied.

FIG. 3 is a time chart explaining the operation of the circuit of FIG.

FIG. 4 is a time chart explaining the operation of the circuit of FIG.

5 is a diagram showing an example of a switching control circuit 48. FIG.

FIG. 6 is a block diagram showing a CPU board according to another embodiment.

FIG. 7 is an in-circuit circuit according to an embodiment of the present invention.
It is a block diagram of an emulator.

FIG. 8 is a diagram showing a conventional CPU board.

[Explanation of symbols]

 2 ... CPU 10 ... In-board data bus 10a ... Extended data bus 12 ... In-board address bus 12a ... Extended address bus 32 ... Control signals necessary for access 48 ... Switching Control circuit

[Procedure amendment]

[Submission date] September 7, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The operation of the circuit of FIG. 2 will be described. First, the case of accessing the target device will be described. The data signal DATA and the control signal W / R of the CPU 2 are given to the memory 52 of the target device via the plug 14. High-order bit of address signal ADDRES and address straw
The bus signal ADS is decoded by the decoder 50 and given to the chip select terminal CS of the memory 52. That is, in the address area assigned to the memory 52, the decoder 50 outputs and the memory 52 becomes operable. The lower bits of the address signal ADDRES are directly given to the memory 52.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

The address strobe signal ADS is given to the decoder 50 via the gate circuit 38. The gate circuit 38 is controlled by the output of the switching control circuit 48. The switching control circuit 48 includes an address signal ADD
Control signal CT from upper bit of RES and CPU2
L1 to CTLn are given.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

The switching control circuit 48, based on these,
It is determined whether to access the target device or the expansion device. When the target device is accessed, the output is “H”, and when the expansion device is accessed, the output is “L”. Here, since the target device is accessed, the output becomes "H" and the gate 38 is opened. Therefore, the address strobe signal ADS is transmitted to the decoder 5
Given to 0 .

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

Claims (2)

[Claims] 1. A CPU board, which can be used in place of the CPU of a target device and can be connected to an expansion device, comprising: a CPU; and an on-board bus line drawn from the CPU and connected to a bus line of the target device. , In-board control signal line drawn from CPU and connected to control signal line of target device, expansion bus line branched from on-board bus line and connected to expansion device bus line, and in-board control signal line In a CPU board provided with an expansion control line that is branched from the control signal line and connected to the control signal line of the expansion device, and a switching control circuit that controls access to the target device and access to the expansion device The target device and the CPU are substantially directly connected without providing a buffer therein, and the access of the target device among the control signal lines on the board is controlled. A gate circuit is provided in one or more on-board control signal lines required for the switching control circuit, and the switching control circuit closes the gate circuit when the CPU accesses the expansion device. CPU board with. 2. An in-circuit emulator configured by connecting an emulation circuit necessary for emulating a part or all of a target device to the expansion bus line and expansion control line of the CPU board of claim 1.