JPH0793914A - Decoding apparatus - Google Patents

Abstract

PURPOSE:To check a code error rate effectively by enabling better viterbi decoding even when a symmetrical waveform distortion is left in a ternary equalization waveform signal in a decoding apparatus which performs a recording and reproduction in a partial response system to execute a viterbi decoding. CONSTITUTION:In a clock reproduction system 10, an automatically slicing system which is adapted to feed back an output of a comparator 13 with an LPF15 is employed in order to prevent the jittering of a bit clock used for the A/D conversion and a viterbi decoding of a ternary equalization waveform signal. The slice level corresponds to a shift value of an averaged level of a signal as reproduction signal binary equalized. A microcomputer circuit 21 computes and generates a decoding control signal using shift information thereof and a viterbi decoder 22 relaxes pass holding conditions determined by a difference metric corresponding to an asymmetric distortion generation patter of a signal based on a decode control signal thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device, which is applied to a digital VTR, an optical disk device or the like, and is used in the case of performing a Viterbi decoding by detecting a multilevel equalized reproduction signal in synchronization with a sampling clock. , And to an improvement for enabling accurate Viterbi decoding even when the symmetry of the reproduced signal is insufficient.

[0002]

2. Description of the Related Art Recently, in a digital information recording / reproducing apparatus represented by a digital VTR or the like, NRZI (Non Return to Z) has been accompanied by high density recording of information on a recording medium.
Recording / reproduction by a partial response (PR) system such as ero Inverted) code and interleaved NRZI code has been adopted, and a Viterbi decoder is often used for data decoding processing.

This is because when the PR system is adopted, signal transmission having a power spectrum suitable for the frequency characteristics of the recording / reproducing system can be performed, and S / N due to noise in the unnecessary band.
There is an advantage that the deterioration of the ratio is small and the density can be increased, and when the Viterbi decoder is used, an excellent S / N ratio and a low S / N ratio can be obtained while maximizing the use of the information contained in the reproduced signal. This is because decoding with a bit error rate becomes possible.

Conventionally, a recording / reproducing circuit of a digital VTR has a basic structure as shown in FIG. 6, and a recording / reproducing channel is formed via a recording medium (magnetic tape or the like). . In the figure, the recording data input from the digital signal processing unit of the recording system is the precoder 1
A predetermined code correlation is applied by the signal, and the modulated recording signal is recorded on the recording medium 3 via the signal recording system 2 [recording amplifier 2a, recording unit (magnetic head, rotary transformer, etc.) 2b].
On the other hand, the recording signal of the recording medium 3 is read by the signal reproducing system 4 [reproducing unit (magnetic head or rotary transformer) 4a, reproducing amplifier 4b], and the read signal is output to the data decoding system 5.

In the data decoding system 5, the distortion included in the read signal is removed by the waveform equalization circuit 6 and the distortion is removed by the ternary equalization circuit 7.
The value equalized waveform signal is converted into a digital signal while sampling the signal by the A / D converter 8 and decoded by the Viterbi decoder 9 to obtain a reproduced signal. Also,
The reproduction signal is output from the Viterbi decoder 9 to the reproduction system digital signal processing unit and subjected to predetermined processing for display output and the like.

By the way, NRZI and interleaved NR
If a PR system that reproduces in three values such as ZI is adopted, the detection level at the sampling points (data points) by the A / D converter 8 is large because the three-value equalization circuit 7 performs waveform equalization. It becomes a value, and it is difficult to directly extract the clock information (phase point) for sampling from the equalized waveform.
Therefore, a clock recovery system 10 is provided separately from the data decoding system 5 to independently generate clock information and supply it to the A / D converter 8 and the Viterbi decoder 9 as a synchronizing bit clock.

In the clock recovery system 10, the signal obtained from the waveform equalizing circuit 6 is converted into a binary equalized waveform signal by the binary equalizing circuit 11, amplified by the amplifier 12, and then detected by the comparator 13 for edge detection. To extract the phase, and based on the phase, the PLL
The (Phase Locked Loop) circuit 14 generates a synchronization bit clock. However, in the signal recording system 2 and the signal reproducing system 4 described above, the signal waveform is often asymmetrically distorted due to the non-uniformity of the duty ratio of the recording signal itself or the asymmetry of the system. However, since it is difficult to completely remove the distortion by the waveform equalization circuit 6, asymmetric distortion remains in the binary equalized reproduced wave and the ternary equalized reproduced wave.

The relationship between the recording signal, the binary equalized reproduced wave, the ternary equalized reproduced wave and the reproduced signal in such a case is shown in FIG. The figure shows the relationship when recording / reproducing is performed by the NRZI code system. If the waveform signal equalizing circuit 6 is used to completely remove the distortion of the recording signal (a), the binary equalized reproduced wave and the ternary equalized reproduced wave are respectively represented by (b) and (c). As described above, the waveform has a symmetry with respect to the reference level, but due to the above-mentioned factors, an asymmetry is generated in the read signal from the recording medium 3 with respect to the trailing edge and the leading edge of the recording signal (a), which causes a waveform or the like. When the equalizing circuit 6 cannot remove the binary equalized reproduced wave and the ternary equalized reproduced wave, asymmetric waveform distortions such as (d) and (e) or (g) and (h) are generated. The center level (dotted line) of the eye pattern shifts to a level deviating from the original reference level (dotted line). That is, the center levels of the binary equalized reproduced wave and the ternary equalized reproduced wave shift toward the negative side by ΔE2 and ΔE3 when the falling becomes relatively large, and conversely the falling becomes relatively large. When this happens, the shift is to the plus side by ΔE2 and ΔE3. Therefore, if edge detection is performed by the comparator 13 that simply sets a constant slice level, the duty ratios of the reproduction signals become uneven as shown in (f) and (i).
(The pulse width changes only in the shaded area in FIG. 7), the jitter of the synchronizing bit clock output from the PLL circuit 14 correspondingly increases, and as a result, the sampling point shifts and the bit error rate of Viterbi decoding increases. It causes the problem of becoming large.

Therefore, conventionally, for a modulated signal (DC free code) that does not contain a DC component after equalization such as the above-mentioned binary equalized reproduced wave, the output of the comparator 13 is set to LPF (Low
An auto slicer that feeds back to the comparison level terminal side of the comparator 13 via the Pass Filter) 15 is used so that the output of the comparator 13 does not include a DC component. That is, the comparator 13 is made to correspond to the shift amount in the binary equalized reproduction wave.
The slice level is changed to prevent the jitter of the synchronizing bit clock of the PLL circuit 14 so that a reproduced signal having a uniform duty ratio can be obtained.

By the way, the above-mentioned auto slicer is intended to optimize the synchronizing bit clock in the clock reproducing system 10. The waveform distortion remains for the ternary equalized reproduced wave, and the center level is It is A / D converted while being shifted and input to the Viterbi decoder 9. Therefore, when the signal is decoded by the Viterbi decoder 9, the code error rate becomes large because the waveform distortion of the ternary equalized reproduced wave and the center level of the eye pattern are shifted.

Regarding the problem in the Viterbi decoding as described above, "the average level Ap of the signal peak is obtained and the average level Ap is used to calculate the metric in the Viterbi decoder, and at the same time, the average of the signal itself is calculated. The level "m" is determined, and the average level m is subtracted from the input of the Viterbi decoder. The Viterbi decoder is less affected by fluctuations in the signal "(Japanese Patent Laid-Open No. 62-18118). Even if there is a change in the peak level or center level of the read signal due to the characteristics of the recording / reproducing system, the improvement measure that can properly perform the Viterbi decoding is provided.

[0012]

However, in the above proposal, the amplitude fluctuation of the signal is caused by the AGC (Automatic Gai).
n Controller) can be sufficiently suppressed, and since the average level m of the signal itself is a so-called DC fluctuation, asymmetrical waveform distortion remains in the ternary equalized reproduced wave as described above. It is considered that it does not function effectively when

Therefore, according to the present invention, as shown in FIG. 6, in the decoding device which uses the auto slicer in the clock recovery system to prevent the jitter of the synchronizing bit clock, the waveform which is asymmetrical to the ternary equalized reproduced wave is used. Even if distortion is included,
It was created for the purpose of providing a decoding device that can perform good Viterbi decoding by utilizing the change in slice level of an auto slicer.

[0014]

SUMMARY OF THE INVENTION The present invention comprises a multi-valued equalizing means for obtaining a multi-valued equalized waveform signal from a reproduction signal, and a binary equalization means for obtaining a binary equalized waveform signal from the reproduction signal. Means for generating a sampling clock using the binary equalized waveform signal by the binary equalized means, obtaining an averaged level of the input binary equalized waveform signal, and inputting the averaged level. A clock generating means for correcting the jitter of the sampling clock by detecting the level difference from the binary equalized waveform signal, and a multi-value obtained by the multi-value equalizing means using the sampling clock of the clock generating means. In a decoding device having a signal detecting means for sampling the digitized waveform signal and a Viterbi decoding means for decoding the sampling signal by the signal detecting means, averaging obtained from the clock generating means An arithmetic means is provided for obtaining a level difference between the bell and a constant reference level, and a decoding control signal corresponding to the level difference is provided. Based on the decoding control signal, the Viterbi decoding means determines a path establishment condition determined by a difference metric. According to the generation mode of the level difference.

[0015]

When the distortion removal of the reproduced signal is not sufficient, the average level of the binary equalized waveform signal varies due to the residual waveform distortion. The waveform distortion remaining in the reproduced signal naturally causes the waveform distortion and the fluctuation of the averaging level in the multilevel equalized waveform signal. However, they are the fluctuations of the waveform distortion and the averaging level of the binary equalized waveform signal. Has a certain correlation with. Therefore, the waveform distortion and the averaging level of the multilevel equalized waveform signal change in accordance with the fluctuation of the level difference between the averaging level obtained from the clock generating means and a constant reference level.

On the other hand, as will be described later, the Viterbi decoding means determines the surviving path based on the corresponding path establishment condition while obtaining the difference metric. However, as described above, waveform distortion or the like exists in the multilevel equalized waveform signal. In this case, if the normal path establishment condition is applied, an incorrect path may be selected.

In the present invention, the calculating means obtains the level difference, creates a decoding control signal corresponding to the level difference, and the Viterbi decoding means corrects the path establishment condition based on the decoding control signal. ing. That is, on the basis of the correspondence relationship between the level difference obtained from the clock generation means and the asymmetry of the multilevel equalized waveform signal, the decoding control signal is output by the Viterbi decoding means according to the variation direction and variation amount of the level difference. The information that relaxes the path establishment condition of is used to prevent the Viterbi decoding unit from making an erroneous path selection due to the waveform distortion of the multilevel equalized waveform signal.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a decoding device according to the present invention will be described below with reference to FIG.
It will be described in detail with reference to FIG. First, FIG. 1 shows a recording / reproducing circuit of a digital VTR according to this embodiment.
The circuit configuration shown in the figure is almost the same as that described with reference to FIG. 6, and since each unit represented by the same reference numeral has the same function, here, each unit and its operation will be described. The description is omitted. The circuit of the present embodiment is characterized in that the clock recovery system 10 is provided with a microcomputer (microcomputer) circuit 21 with a built-in A / D converter, and that the Viterbi decoder 22 uses the microcomputer circuit 21 to determine the condition for establishing the path. It is based on the control signal from.

Specifically, the microcomputer circuit 21 is always LPL
Slice level and reference voltage level obtained from 15 outputs
The level difference from [0 (V)] is obtained, and the information related to the positive / negative (hereinafter referred to as “(±) information”) and the information proportional to the value obtained by squaring the absolute value of the level difference (hereinafter referred to as “α information”). ) Is output to the Viterbi decoder 22 as a decoding control signal. It should be noted that in this embodiment as well, FIG.
Since the recording / playback is performed by the NRZI code system shown in, and the reference level of the binary equalized playback wave is set as 0 (V), α information is given by α∝ (ΔE2) ^2. .

On the other hand, the Viterbi decoder 22 is capable of changing the path conditional expression, but before the explanation of the operation of the circuit of this embodiment, the decoding principle when Viterbi decoding is applied to the NRZI coding system is explained. I will explain. First, Fig. 2 shows NRZI.
It is the figure which modeled the recording / reproducing transfer system in a code system. At time: K, the transmission signal a _K is precoded to obtain an intermediate sequence b _K = −a _K b _K−1, which is passed through the recording / reproducing channel. In this case, since the magnetic recording system has a differential characteristic like a digital VTR, its output becomes z _K = b _K -b _{K -1} when the amplitude decrease in the high frequency range is corrected. Then, in general, [g ₀ , g ₁ ,
, G _L ] (where L is the length of the intersymbol interference of the channel), the signal passing through the channel is z _K = a _K g ₀ + a _K-1 g ₁ if there is no noise. + ...... a _KL g _L next, and the received signal noise n _K is added becomes _{y K = z K + n K} . still,
a _K is a binary signal, and takes 0 or 1 based on the recording signal of FIG. 7 here.

Therefore, comparing the above equations for z _K , in the case of the NRZI code system, g ₀ = 1 and g ₁ = -1,
g _X = 0 (where X = 2, ..., L), and the state S _{K at} time: _K is given by S _K = b _K , and b _K is -1 or 1. The number is 2, and the state transition diagram is as shown in FIG. Further, based on the state transition diagram of FIG. 3, the state transition is represented in time series as the trellis diagram of FIG.

Therefore, when two kinds of metrics L _K (+) and L _K (-) are defined according to each state as shown in FIG. 4, time:
There are two paths from K-1 state S = -1 and 1 toward time: K, but in each state of time: K, the path with the largest metric is the correct path among the above two paths. Will be selected as. That is, L _K (+) = max [L _K-1 (+) + {-(y _K- 0) ² }, L _K-1 (-) +
{− (Y _K −2) ² }] L _K (−) = max [L _K−1 (+) + {− (y _K +2) ² }, L _K−1 (−) +
The metric is determined according to the formula of {− (y _K −0) ² }]. However, as is clear from the mathematical expression, as the time elapses, negative numbers are gradually accumulated in each metric, and the absolute value thereof becomes infinitely large, so that it cannot be applied to an actual circuit for calculation.

On the other hand, the information necessary to determine the path is 2
It is the difference between the metrics in the two states, not the absolute value. Therefore, assuming that the difference metric is ΔL _K , ΔL _K = L _K (+) − L _K (−) = max [L _K−1 (+) + {− (y _K −0) ² }, L _K−1 ( _{-) + {- (y K} -2) 2}] -max [L K-1 (+) + {- (y K +2) 2}, L K-1 (-) + {- (y K -0 ) ² }], ΔL _K is finite and can be calculated by dividing into four combinations of paths. However, since there is actually no combination in the case where the paths in FIG. 4 intersect, as shown in FIG. 5, it can be classified into the following three path establishment conditions according to the mode of the three paths. ΔL _K = 4y _K −4 4y _K −ΔL _K−1 > 4 (A) ΔL _K = ΔL _K−1 4 ≧ 4y _K −ΔL _K−1 > −4 (B) ΔL _K = 4y _K +4 − 4 ≧ 4y _K −ΔL _K-1 (C)

Then, based on these equations (a), (b) and (c), the difference metric ΔL _K-1 at time: K _-1 and y _{K at} time: _K.
Is given, the next difference metric ΔL _K is determined, and the surviving path can be determined by cyclically executing the calculation at each time.

The Viterbi decoder 9 in the conventional recording / reproducing circuit described in FIG. 6 decodes the reproduced signal based on the above-mentioned principle. However, the ternary value obtained by the ternary equalizing circuit 7 If the center level of the eye pattern is deviated due to residual asymmetric distortion in the regenerated reproduced wave, the above equation (a),
If (b) and (c) are applied as they are, the bit error rate increases.

In the circuit of this embodiment, (±) information and α information [∝ (ΔE2) ² ] created by the microcomputer circuit 21 based on the slice level output from the LPF 15 to the comparator 13 as described above.
Is output to the Viterbi decoder 22 as a decoding control signal. Then, the Viterbi decoder 22 adaptively changes the above three path establishment conditions (a), (b), and (c) based on the decoding control signal as follows. That is, when the (±) information is negative [when the central level of the binary equalized reproduced wave is shifted in the negative direction as shown in FIG. 7 (d)], the path based on Set the satisfaction conditions, and on the contrary
When the (±) information is positive [when the center level of the binary equalized reproduced wave is shifted in the positive direction as shown in FIG. 7 (g)], the path establishment condition based on the formula To do.

When the (±) information is negative: ΔL _K = 4y _K −4 + α 4y _K −ΔL _K−1 > 4-α ... ΔL _K = ΔL _K−1 4−α ≧ 4y _K −ΔL _K-1 > _{-4 ... ΔL K = 4y K +4} -4 ≧ 4y K -ΔL K-1 ... (±) if the information is _{positive; ΔL K = 4y K -4 4y} K -ΔL K-1> 4 ... ΔL K = ΔL _K-1 4 ≧ 4y _K −ΔL _K-1 > −4 + α ΔL _K = 4y _K + 4-α −4 + α ≧ 4y _K −ΔL _K-1

The setting of the path establishment condition in the Viterbi decoder 22 is performed by the residual distortion of the ternary equalized reproduced wave and the shift of the center level as shown in (e) and (h) of FIG. On the other hand, the conditions for taking the paths (a) and (c) shown in FIG. 5 must be relaxed. Specifically, when the center level of the ternary equalized reproduction wave is shifted to the minus side, the above-mentioned mathematical expression relaxes the path selection condition shown in (a) of FIG. When the center level of the equalized reproduced wave is shifted to the plus side, the path selection condition shown in (c) of FIG. 5 is relaxed. Therefore, the recording / playback system 2,4
Signal asymmetry and waveform distortion occur, the waveform equalization circuit 6 does not sufficiently remove the distortion, and nonlinear residual distortion in the ternary equalized reproduced wave or fluctuation in the center level of the eye pattern occurs. Even in this case, good Viterbi decoding can always be performed, and the code error rate can be effectively suppressed.

[0029]

The decoding device of the present invention has the following effects by having the above configuration. In a decoding device that performs recording / reproduction in the PR system and also performs decoding in Viterbi decoding means, when asymmetric distortion of a signal occurs in the recording / reproduction system and sufficient distortion removal cannot be performed even by waveform equalization. , The asymmetric distortion remains in the multi-valued equalized waveform signal to be reproduced and the error rate of Viterbi decoding increases, but in the present invention, the binary value is used in order for the clock generation means to correct the jitter of the sampling clock. By using the averaging level of the equalized waveform signal, a decoding control signal calculated based on the level difference between the averaging level and a constant reference level is used to adaptively establish the path establishment condition of the Viterbi decoding means. Since this is alleviated, good Viterbi decoding can always be performed even if there is asymmetrical distortion of the signal waveform or deviation of the center of the eye pattern, and the code error rate can be suppressed.

[Brief description of drawings]

FIG. 1 is a digital V according to an embodiment of a decoding device of the present invention.
It is a block circuit diagram which shows the recording / reproducing circuit of TR.

FIG. 2 is a diagram modeling a recording / reproducing transmission system in the NRZI code system.

FIG. 3 is a state transition diagram when Viterbi decoding is applied to the NRZI coding system.

FIG. 4 is a trellis diagram when Viterbi decoding is applied to the NRZI coding system.

FIG. 5 is a path classification diagram when Viterbi decoding is applied to the NRZI coding system.

FIG. 6 is a block circuit diagram showing a recording / reproducing circuit of a conventional digital VTR.

FIG. 7 is a signal timing chart showing the relationship between a recording signal, a binary equalized reproduced wave, a ternary equalized reproduced wave, and a reproduced signal in a normal case and a case where asymmetrical waveform distortion occurs.

[Explanation of symbols]

1 ... Precoder, 2 ... Signal recording system, 2a ... Recording amplifier, 2b ...
Recording unit, 3 ... Recording medium, 4 ... Signal reproducing system, 4a ... Reproducing unit, 4b
… Regenerative amplifier, 5… Data decoding system, 6… Waveform equalization circuit, 7
... three-value equalization circuit (multi-value equalization means), 8 ... A / D converter (signal detection means), 9, 22 ... Viterbi decoder (Viterbi decoding means), 10
... Clock reproduction system, 11 ... Binary equalization circuit (binary equalization means),
12 ... Amplifier, 13 ... Comparator (clock generation means), 14 ... PL
L circuit (clock generation means), 15 ... LPF (clock generation means), 21 ... Microcomputer circuit (calculation means).

Claims (1)

[Claims] 1. A multi-value equalizer for obtaining a multi-value equalized waveform signal from a reproduced signal, a binary equalizer for obtaining a binary equalized waveform signal from the reproduced signal, and a binary equalizer 2 A means for generating a sampling clock using a value-equalized waveform signal, which calculates an averaging level of an input binary equalized waveform signal and compares the averaged level with the input binary equalized waveform signal. Clock generation means for correcting the jitter of the sampling clock by detecting the level difference, and signal detection for sampling the multilevel equalized waveform signal obtained by the multilevel equalization means using the sampling clock of the clock generation means Means and a Viterbi decoding means for decoding the sampling signal by the signal detecting means, the averaging level obtained from the clock generating means and a constant reference level. Is provided, and arithmetic means for creating a decoding control signal corresponding to the level difference is provided, and based on the decoding control signal, the Viterbi decoding means determines a path establishment condition determined by a difference metric as a generation condition of the level difference. A decoding device characterized by easing according to.