JPH0787380B2 - CMi decoding circuit - Google Patents

Description

The present invention relates to a CMi decoding circuit used for decoding a CMi code used in a binary signal transmission system such as an optical fiber transmission system.

[Conventional technology]

CMi (Coded Mark Inversion: Coded Mark
Inversion) code means the logical "1" as shown in FIG.
Corresponding three types of states "1", "00", and "01" to the space and mark of the information signal series, and alternately select "11" and "00" for the mark "1" of the information signal. However, it is a code that selects “01” for the space “0.” That is, the CMi code serially converts one bit of the information signal sequence into two bits and transmits it, which is either “0” or “1”. "It has features such as preventing loss of synchronization information due to continuity and halving the mark ratio on the transmission path.

A circuit diagram of a conventional CMi decoding circuit is shown in FIG. 6 and its time chart is shown in FIG.

Flip-flop (hereinafter abbreviated as FF) 100, FF shown in FIG.
102 holds the bit first half level of the signal A having the opposite phase of the received CMi signal, and FF101 holds the bit second half level. Next, the exclusive OR gate 3 compares the first half level and the second half level, and if the levels are the same, it is determined to be a mark, and if they are different, it is determined to be a space. The resulting signal F is a signal obtained by restoring the received CMi signal to the original information signal sequence.

However, this restored signal F has a problem that a hazard as shown in FIG. 7 occurs.

Next, FIG. 8 shows a circuit for detecting an error generated on a transmission line by using a conventional CMi decoding circuit, and FIG. 9 shows a time chart thereof.

In FIG. 8, it is the AND gate 4 that detects “10” (“01” in this case because the polarity of the received CMi signal is inverted) that is not in the pattern of the received CMi signal as an error.

The patterns "11" and "00" of the received CMi signal appear alternately. However, when "11" or "00" continues, the error occurs when the exclusive OR gates 5, 6 and 7 and the divider circuit Detect by comparing the previous mark level with the newly received mark level, 103. The differential circuit 11 and the delay circuit 12 are required to detect an error in this way, but such a circuit is not suitable for LSi conversion.

Note that, as a technique related to this field, for example, JP-A-60-227549 is cited.

[Problems to be solved by the invention]

In the above-mentioned prior art, no consideration is given to the occurrence of a hazard, and there is a problem that the latter stage logic malfunction due to the propagation of a signal including this hazard and a problem that the logic is unsuitable for LSi implementation.

An object of the present invention is to provide a CMi decoding circuit that eliminates hazards, has a simple circuit configuration, and is suitable for LSi conversion.

[Means for solving problems]

The above object is achieved by configuring a CMi decoding circuit using two-phase clock signals having different phases extracted from the received CMi signal.

[Action]

A CMi decoding circuit according to the present invention operates with two-phase reference clock signals having different phases extracted from a received CMi signal.
Since the phase reference clock signal is used to determine the first half level of the received CMi signal, and the second phase reference kelock signal is used to determine the second half level, a hazard does not occur in the decoded signal and it may malfunction. There is no.

Further, since the error detection circuit also operates with the two-phase reference clock signals having different phases, the differentiation circuit and the delay circuit, which are required in the prior art, are not required, and a circuit suitable for LSi implementation can be configured.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. As shown in FIGS. 1 and 2, the first-phase reference clock signal T0 indicating the first half of the bits of the two-phase reference clock signal in which the level of the first half of the received CMi signal is synchronized with the CMi signal.
Hold at FF200. The output of the FF200 and the received CMi signal are ORed by the OR gate 21, and the output is held in the FF202 by the second phase reference clock signal T1 indicating the latter half of the bit. The signal NRZ output from the FF202 is a signal restored to the original information signal sequence. In this decoding circuit, the error pattern "10" is likely to have changed from "11" or "00" to "10" due to a random error that occurred on the transmission path, so the original information signal is Consider it a mark.

Next, a time chart of the first error detection will be described with reference to FIG.

The signal AD that holds the level of the first half of the received CMi signal AA is "1"
And when the second half level of the received CMi signal AA is “0” (that is, when the pattern is “10”), the first CMi error is detected.
Hold this with FF201.

Next, a second error detection time chart will be described with reference to FIG. The FF 203 holds the first half level of the received CMi signal.
The AND gate 22 passes the first-phase reference clock signal T0 only when the restored information signal is a mark. The FF 204 holds the mark level by the passed clock signal AL. The output of FF204 and the phase opposite to the first half bit level of the newly received CMi signal are exclusive ORed by gate 23, resulting in a match and newly received CMi.
When the signal pattern is other than "01" (that is, when the original information signal is a mark), the AND gate 24 detects the second error, and the FF 205 holds and outputs it.

As described above, the CMi decoded signal NRZ, the first error detection signal ER1 and the second error detection signal ER2 are obtained in synchronization with the second phase reference clock T1.

〔The invention's effect〕

 The present invention has the following effects.

(1) The received CMi signal can be converted into a decoded signal without a hazard.

(2) It is possible to detect an error on the transmission path of the received CMi signal with a simple circuit configuration.

(3) It is suitable for LSi implementation because it operates with two-phase reference clock signals having different phases extracted from the received CMi signal and has no delay circuit or differentiating circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a circuit for performing CMi decoding and CMi error detection showing an embodiment of the present invention, FIGS. 2 to 4 are time charts relating to FIG. 1, and FIG. Is a diagram for explaining the CMi code,
FIG. 6 is a circuit diagram showing a conventional CMi decoding circuit, FIG. 7 is its time chart, FIG. 8 is a circuit diagram showing a CMi error detection circuit using the CMi decoding circuit shown in FIG. 6, and FIG. 9 is It is the time chart. 1,2 …… NOT gate, 3,5,6,23 …… gate (exclusive OR), 4,7,10,20,22,24 …… AND gate, 8,9,21 …… OR gate, 100 ~ 102,200 ~ 205 …… Flip-flop.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Toshiaki Koyama 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Pref., Kanagawa Factory, Hiritsu Manufacturing Co., Ltd. (56) References JP-A-61-135231 (JP, A) JP-A-61 -135230 (JP, A) JP 60-227549 (JP, A) JP 60-70848 (JP, A) JP 57-65943 (JP, A) JP 63-67055 (JP, A) ) JP-A-59-45763 (JP, A) JP-A-59-178051 (JP, A) JP-A-58-71752 (JP, A) JP-B 3-76608 (JP, B2) JP-B 57- 58096 (JP, B2)

Claims (2)

[Claims] 1. A first half indicating a first half of bits of a two-phase reference clock signal which is input with a received CMi signal and which is synchronized with the CMi signal.
A first flip-flop that holds and outputs an input signal in accordance with a phase reference clock signal, and a logical sum circuit that takes the logical sum of the signal of the opposite phase of the received CMi signal and the output signal of the first flip-flop The output signal of the OR circuit is input and the input signal is held by the second phase reference clock signal indicating the latter half bit of the two phase reference clock signals.
Of the second flip-flop for outputting, the first AND circuit for ANDing the signal of the opposite phase of the received CMi signal and the output signal of the first flip-flop, and the first AND circuit A CMi decoding circuit, comprising: a third flip-flop for inputting an output signal and holding / outputting the input signal in accordance with the second phase reference clock signal. 2. A CMi decoding circuit according to claim 1, wherein the output signal of the first flip-flop is input and the input signal is held and output by the reference clock signal of the second phase. And a second AND circuit for taking a logical product of the output signal of the second flip-flop and the reference clock signal of the first phase,
A fifth flip-flop that receives the output signal of the flip-flop and holds and outputs the input signal according to the output clock signal of the second AND circuit, and a signal that is the opposite phase of the output signal of the first flip-flop. And an exclusive OR circuit that takes the exclusive OR of the output signal of the fifth flip-flop and a third product that takes the logical product of the output signal of the OR circuit and the output signal of the exclusive OR circuit. And a sixth flip-flop that receives the output signal of the third AND circuit and holds and outputs the input signal according to the reference clock signal of the second phase.
CMi decoding circuit.