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JPH0786199A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Method for manufacturing silicon carbide semiconductor device

Info

Publication number
JPH0786199A
JPH0786199A JP5229332A JP22933293A JPH0786199A JP H0786199 A JPH0786199 A JP H0786199A JP 5229332 A JP5229332 A JP 5229332A JP 22933293 A JP22933293 A JP 22933293A JP H0786199 A JPH0786199 A JP H0786199A
Authority
JP
Japan
Prior art keywords
nitride film
silicon
semiconductor device
sic
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5229332A
Other languages
Japanese (ja)
Inventor
Akiyasu Kumagai
明恭 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP5229332A priority Critical patent/JPH0786199A/en
Publication of JPH0786199A publication Critical patent/JPH0786199A/en
Pending legal-status Critical Current

Links

Classifications

    • H10P30/2042
    • H10P30/21

Landscapes

  • Formation Of Insulating Films (AREA)

Abstract

(57)【要約】 【目的】SiC半導体素体にAlを所期の濃度に導入したp
形領域を形成し、半導体素子作製を可能にする。 【構成】イオン注入後のアニール時のAlの外方拡散を、
表面に窒化けい素膜を形成することにより防止して所期
のAl濃度を得る。窒化けい素とSiCの熱膨張率の違いに
よる支障の発生は、窒化けい素膜の両面に酸化けい素膜
を積層することにより防止する。
(57) [Summary] [Purpose] p was obtained by introducing Al into a SiC semiconductor element at a desired concentration.
Forming a shaped region enables semiconductor device fabrication. [Composition] Outward diffusion of Al during annealing after ion implantation,
It is prevented by forming a silicon nitride film on the surface to obtain the desired Al concentration. The occurrence of trouble due to the difference in the coefficient of thermal expansion between silicon nitride and SiC is prevented by laminating silicon oxide films on both sides of the silicon nitride film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、炭化けい素 (以下SiC
と記す) 素体にp型領域形成のためにアルミニウム (A
l) をイオン注入するSiC半導体装置の製造方法に関す
る。
The present invention relates to silicon carbide (hereinafter referred to as SiC).
Aluminum (A) for forming a p-type region in the element body.
l) of the present invention relates to a method for manufacturing a SiC semiconductor device.

【0002】[0002]

【従来の技術】2.2〜3.3eVの広いバンドギャップを有
するSiCは、けい素に比べ最大電界強度が高い特徴を有
し、高耐圧半導体素子の材料として期待されている。半
導体素子の製造には、不純物のドーピングが不可欠であ
る。SiCに高温においてイオン注入すれば、AlやGaでp
形になることは、Jornal of the Electrochemical Soci
ety 、Vol 119(1972)p.1355 にAddamiano らにより、ま
たSov.Phys.Semicond 、Vol 9(1976)p.820にGusev らに
より報告されている。
2. Description of the Related Art SiC having a wide band gap of 2.2 to 3.3 eV has a characteristic that the maximum electric field strength is higher than that of silicon and is expected as a material for a high breakdown voltage semiconductor element. Doping of impurities is indispensable for manufacturing semiconductor devices. If ion-implanted into SiC at high temperature, p with Al or Ga
Forming is the Journal of the Electrochemical Soci
ety, Vol 119 (1972) p. 1355 by Addamiano et al. and Sov. Phys. Semicond, Vol 9 (1976) p. 820 by Gusev et al.

【0003】[0003]

【発明が解決しようとする課題】一般にイオン注入した
半導体基板は不純物の電気的な活性化のためアニール工
程が続けて施される。ところが、SiC素体にイオン注入
したAlはアニール工程で外方拡散、すなわちSiC中のAl
が基板外に放出される現象が生じ、所期の不純物濃度が
得られないという点でAlのイオン注入は困難であった。
Generally, an ion-implanted semiconductor substrate is continuously subjected to an annealing process for electrically activating impurities. However, the Al ion-implanted into the SiC element diffuses outward in the annealing process, that is, the Al in SiC.
It was difficult to implant Al ions in that the desired impurity concentration could not be obtained due to the phenomenon that Al was released outside the substrate.

【0004】本発明は、この問題を解決し、SiC素体中
にAlをイオン注入して所期の不純物濃度の領域を形成す
るSiC半導体装置の製造方法を提供することにある。
An object of the present invention is to solve this problem and provide a method of manufacturing a SiC semiconductor device in which Al is ion-implanted into a SiC element body to form a region having a desired impurity concentration.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明のSiC半導体装置の製造方法は、SiC素体
の所定の領域にAlのイオン注入を行い、少なくともその
Alのイオン注入を行った領域の表面に窒化けい素膜によ
り被覆したのちアニールする工程を含むものとする。窒
化けい素膜の厚さが0.1μm以上、0.5μm以下である
と良い。窒化けい素膜とSiC素体の間に酸化けい素膜を
介在させることが有効である。その酸化けい素膜の厚さ
が0.5μm以下であることが望ましい。さらに窒化けい
素膜の反酸化けい素膜側にも酸化けい素膜を被着するこ
とが有効である。この場合、両酸化けい素膜の厚さをほ
ぼ等しくすることが良い方法である。
In order to achieve the above object, a method of manufacturing a SiC semiconductor device according to the present invention is performed by implanting Al ions into a predetermined region of a SiC element body, and at least performing the ion implantation.
It includes a step of coating the surface of the region where Al ions are implanted with a silicon nitride film and then annealing. The thickness of the silicon nitride film is preferably 0.1 μm or more and 0.5 μm or less. It is effective to interpose a silicon oxide film between the silicon nitride film and the SiC body. The thickness of the silicon oxide film is preferably 0.5 μm or less. Further, it is effective to deposit a silicon oxide film also on the anti-oxidation silicon film side of the silicon nitride film. In this case, it is a good method to make the thicknesses of both silicon oxide films substantially equal.

【0006】[0006]

【作用】理由は十分には解明されていないが、窒化けい
素膜はAlを固溶し、Alの外方拡散阻止作用があることが
実験的に見出された。外方拡散阻止には0.1μm以上の
厚さが必要である。厚すぎるとその中に固溶されるAlの
量が多くなりすぎるので、0.5μm以下に抑えるとよ
い。ただし、窒化けい素はSiCに比べて熱膨張率が小さ
く、その熱膨張率の差異によりSiC素体と窒化けい素膜
の間に熱応力が発生し、窒化膜に亀裂が生じる場合があ
り、アニール時にこの亀裂を通じてAlが外方拡散し、Si
C中にAl濃度のばらつきが生ずることがある。酸化けい
素膜はこの両者の緩衝膜として作用する。酸化膜厚は膜
付け時間がなるべく短くなるように、また、酸化膜中に
外方拡散するAl量を少なくするために0.5μm以下にす
る必要がある。そして、窒化膜の厚さとほぼ等しくする
のが窒化膜に亀裂を発生させないために有効である。し
かし、深い拡散層を形成するためにアニール温度を高く
した場合には、酸化けい素と窒化けい素の熱膨張率の差
異により両者間に熱応力が発生し、窒化膜に亀裂が発生
する。そこで、窒化膜を両面の酸化膜により挟むことに
より、熱応力の発生を極力抑える。
[Function] Although the reason has not been sufficiently clarified, it has been experimentally found that the silicon nitride film forms a solid solution with Al and has an Al outward diffusion blocking effect. A thickness of 0.1 μm or more is required to prevent outward diffusion. If it is too thick, the amount of Al dissolved in it will be too large, so it is preferable to keep it to 0.5 μm or less. However, silicon nitride has a smaller coefficient of thermal expansion than SiC, and due to the difference in coefficient of thermal expansion, thermal stress may be generated between the SiC element body and the silicon nitride film, which may cause cracks in the nitride film. During annealing, Al diffuses out through these cracks and Si
There may be variations in Al concentration during C. The silicon oxide film acts as a buffer film for both. The oxide film thickness needs to be 0.5 μm or less so that the film deposition time is as short as possible and the amount of Al that diffuses outward into the oxide film is small. And, it is effective to make the thickness of the nitride film approximately equal to that in order to prevent the nitride film from cracking. However, when the annealing temperature is increased in order to form a deep diffusion layer, thermal stress is generated between the silicon oxide and silicon nitride due to the difference in thermal expansion coefficient between them, and a crack is generated in the nitride film. Therefore, by sandwiching the nitride film between the oxide films on both sides, generation of thermal stress is suppressed as much as possible.

【0007】[0007]

【実施例】図1(a) 、(b) は本発明の一実施例のAlイオ
ン注入工程を示す。まず、SiC基板1にAlイオン2をイ
オン注入する〔図1(a) 〕。このとき、イオン注入条件
は加速電圧100keV、ドーズ量は3×1014cm-2、イオン種
27Al+ である。次にSiC基板の表面に窒化膜3を形成
する〔図1(b) 〕。窒化膜の形成は例えば、スパッタ
法、プラズマCVD法などによる。この窒化膜によりAl
の外方拡散が防止されるが、窒化膜中のAlの固溶度が大
きく、窒化膜が厚いほどアニール中の外方拡散により窒
化膜中に固溶するAlの量は大きくなる。ただし、窒化膜
が薄すぎるとAlが通過するおそれがあるほか、ピンホー
ルができやすく、ピンホールの部分でAlが外方拡散する
恐れがある。窒化膜の厚さは0.1〜0.5μm程度が適当
である。また、SiC基板面内で窒化膜厚にばらつきを生
じているとSiC基板内へのAlの拡散量に局部的な差異を
生じる。したがって、SiC基板中のAl濃度の面内分布も
ばらつきが生じる。すなわち、窒化膜3は上記の厚さで
しかもSiC基板面内で均一の厚さに作製する必要があ
る。このあと、アニールを1200℃の温度で窒素雰囲気中
で10時間実施した。
EXAMPLE FIGS. 1 (a) and 1 (b) show an Al ion implantation process according to an example of the present invention. First, Al ions 2 are ion-implanted into the SiC substrate 1 [FIG. 1 (a)]. At this time, the ion implantation conditions are an acceleration voltage of 100 keV, a dose amount of 3 × 10 14 cm −2 , and an ion species of 27 Al + . Next, a nitride film 3 is formed on the surface of the SiC substrate [FIG. 1 (b)]. The nitride film is formed by, for example, a sputtering method or a plasma CVD method. This nitride film makes Al
However, the solid solubility of Al in the nitride film is large, and the thicker the nitride film, the greater the amount of Al that forms a solid solution in the nitride film due to the outward diffusion during annealing. However, if the nitride film is too thin, Al may pass therethrough, and pinholes are likely to be formed, so that Al may diffuse outward in the pinhole portion. The appropriate thickness of the nitride film is about 0.1 to 0.5 μm. Further, if the nitride film thickness varies within the surface of the SiC substrate, a local difference occurs in the amount of Al diffused into the SiC substrate. Therefore, the in-plane distribution of Al concentration in the SiC substrate also varies. That is, the nitride film 3 needs to be formed to have the above-mentioned thickness and a uniform thickness within the surface of the SiC substrate. Then, annealing was performed at a temperature of 1200 ° C. in a nitrogen atmosphere for 10 hours.

【0008】図2(a) 〜(d) に示す別の実施例を示し、
まず、SiC基板に図1に示した方法と同様にAlイオン2
をイオン注入する〔図2(a) 〕。次にSiC基板表面に0.
1μm程度の厚さの酸化膜4を形成する〔図2(b) 〕。
次いで酸化膜4上に窒化膜3を図1と同様の方法によっ
て形成する〔図2(c) 〕。このときの窒化膜は、図1の
ように窒化膜のみをAlの外方拡散防止膜とする場合と同
様の理由により0.1〜0.5μm程度の均一膜厚を有する
膜である必要がある。さらに、窒化膜3の上に再び酸化
膜5を形成する〔図2(d) 〕。SiC基板1と窒化膜3の
間に緩衝膜として酸化膜4が形成されており、SiCと窒
化けい素の熱膨張率の違いによる熱応力の発生を抑えて
はいるが、アニール温度を高くするために窒化膜3を酸
化膜4および酸化膜5により挟む構造としている。外方
拡散防止膜が、図1のように窒化けい素膜3のみ、ある
いは酸化けい素膜4と窒化けい素膜3よりなる構造で
は、アニール時に窒化膜3に亀裂が生じ、この亀裂によ
りSiC基板内でAlの面内濃度分布にばらつきを生じる場
合があった。図2に示すように、外方拡散防止膜が酸化
膜4、窒化膜3および酸化膜5からなる構造のときに
は、1500℃、10時間のアニール後の亀裂は発生しない。
このとき、酸化膜5の厚さは、酸化膜3の厚さと同等に
するのが窒化膜3に亀裂を発生させないために有効であ
った。
Another embodiment shown in FIGS. 2 (a) to 2 (d) is shown.
First, on the SiC substrate, as in the method shown in FIG.
Are ion-implanted [Fig. 2 (a)]. Next, 0.
An oxide film 4 having a thickness of about 1 μm is formed [FIG. 2 (b)].
Next, the nitride film 3 is formed on the oxide film 4 by the same method as that shown in FIG. 1 [FIG. 2 (c)]. At this time, the nitride film needs to be a film having a uniform film thickness of about 0.1 to 0.5 μm for the same reason as in the case where only the nitride film is used as the outward diffusion preventing film for Al as shown in FIG. is there. Further, an oxide film 5 is formed again on the nitride film 3 [FIG. 2 (d)]. An oxide film 4 is formed as a buffer film between the SiC substrate 1 and the nitride film 3 to suppress the generation of thermal stress due to the difference in thermal expansion coefficient between SiC and silicon nitride, but to increase the annealing temperature. Therefore, the nitride film 3 is sandwiched between the oxide film 4 and the oxide film 5. In the structure in which the outward diffusion preventing film is composed of only the silicon nitride film 3 or the silicon oxide film 4 and the silicon nitride film 3 as shown in FIG. 1, a crack is generated in the nitride film 3 during annealing, and this crack causes the SiC In some cases, the in-plane concentration distribution of Al varied within the substrate. As shown in FIG. 2, when the outward diffusion preventing film has a structure composed of the oxide film 4, the nitride film 3 and the oxide film 5, no crack occurs after annealing at 1500 ° C. for 10 hours.
At this time, it was effective to make the thickness of the oxide film 5 equal to the thickness of the oxide film 3 in order to prevent the nitride film 3 from cracking.

【0009】図3は、本発明の実施例により製造された
半導体装置のp形領域におけるAl濃度分布を示し、SiC
素体表面のAl濃度は1×1019cm-3程度で、拡散深さ2μ
m程度の濃度分布が均一に得られた。
FIG. 3 shows the Al concentration distribution in the p-type region of the semiconductor device manufactured according to the embodiment of the present invention.
The Al concentration on the surface of the element body is about 1 × 10 19 cm -3 and the diffusion depth is 2μ.
A concentration distribution of about m was obtained uniformly.

【0010】[0010]

【発明の効果】本発明によれば、窒化けい素のAl外方拡
散阻止作用を利用して、Alイオン注入後SiC素体表面を
窒化けい素膜により被覆してSiCへの所期の濃度でのAl
導入領域を形成することができた。また窒化けい素とSi
Cとの熱膨張率の違いによる支障の発生を、酸化けい素
膜の積層により防止することができた。
According to the present invention, by utilizing the Al outward diffusion blocking effect of silicon nitride, the surface of the SiC element body is covered with a silicon nitride film after Al ion implantation to obtain a desired concentration in SiC. At Al
The introduction area could be formed. Also silicon nitride and Si
The occurrence of troubles due to the difference in the coefficient of thermal expansion from C could be prevented by stacking the silicon oxide film.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるAlイオン注入工程を
(a) 、(b) の順に示す断面図
FIG. 1 shows an Al ion implantation process in one embodiment of the present invention.
Sectional views shown in order of (a) and (b)

【図2】本発明の別の実施例におけるAlイオン注入工程
を(a) ないし(d) の順に示す断面図
FIG. 2 is a sectional view showing an Al ion implantation step in another embodiment of the present invention in the order of (a) to (d).

【図3】本発明の実施例により製造されたSiC半導体装
置のp形領域における濃度分布図
FIG. 3 is a concentration distribution diagram in a p-type region of a SiC semiconductor device manufactured according to an example of the present invention.

【符号の説明】[Explanation of symbols]

1 SiC基板 2 Alイオン 3 窒化けい素膜 4、5 酸化けい素膜 1 SiC substrate 2 Al ion 3 Silicon nitride film 4, 5 Silicon oxide film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】炭化けい素素体の所定の領域にアルミニウ
ムのイオン注入を行い、少なくともそのアルミニウムの
イオン注入を行った領域の表面を窒化けい素膜により被
覆したのちアニールする工程を含むことを特徴とする炭
化けい素半導体装置の製造方法。
1. A method of implanting aluminum into a predetermined region of a silicon carbide body, at least covering the surface of the region where the aluminum ion implantation is performed with a silicon nitride film, and then annealing. A method for manufacturing a characteristic silicon carbide semiconductor device.
【請求項2】窒化けい素膜の厚さが0.1μm以上、0.5
μm以下である請求項1記載の炭化けい素半導体装置の
製造方法。
2. A silicon nitride film having a thickness of 0.1 μm or more and 0.5.
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the thickness is not more than μm.
【請求項3】窒化けい素膜と炭化けい素素体の間に酸化
けい素膜を介在させる請求項1あるいは2記載の炭化け
い素半導体装置の製造方法。
3. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a silicon oxide film is interposed between the silicon nitride film and the silicon carbide body.
【請求項4】酸化けい素膜の厚さが0.5μm以下である
請求項3記載の炭化けい素半導体装置の製造方法。
4. A method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the thickness of the silicon oxide film is 0.5 μm or less.
【請求項5】窒化けい素膜の反酸化けい素膜側にも酸化
けい素膜を被着する請求項3あるいは4記載の炭化けい
素半導体装置の製造方法。
5. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein a silicon oxide film is deposited also on the anti-silicon oxide film side of the silicon nitride film.
【請求項6】両酸化けい素膜の厚さをほぼ等しくする請
求項5記載の炭化けい素半導体装置の製造方法。
6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the thicknesses of both silicon oxide films are made substantially equal.
JP5229332A 1993-09-16 1993-09-16 Method for manufacturing silicon carbide semiconductor device Pending JPH0786199A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5229332A JPH0786199A (en) 1993-09-16 1993-09-16 Method for manufacturing silicon carbide semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5229332A JPH0786199A (en) 1993-09-16 1993-09-16 Method for manufacturing silicon carbide semiconductor device

Publications (1)

Publication Number Publication Date
JPH0786199A true JPH0786199A (en) 1995-03-31

Family

ID=16890500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5229332A Pending JPH0786199A (en) 1993-09-16 1993-09-16 Method for manufacturing silicon carbide semiconductor device

Country Status (1)

Country Link
JP (1) JPH0786199A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952679A (en) * 1996-10-17 1999-09-14 Denso Corporation Semiconductor substrate and method for straightening warp of semiconductor substrate
JP2000012482A (en) * 1998-06-22 2000-01-14 Fuji Electric Co Ltd Method for manufacturing silicon carbide semiconductor device
JP2002314071A (en) * 2001-04-18 2002-10-25 Denso Corp Method for manufacturing silicon carbide semiconductor device
US6573534B1 (en) 1995-09-06 2003-06-03 Denso Corporation Silicon carbide semiconductor device
WO2012120731A1 (en) 2011-03-09 2012-09-13 住友電気工業株式会社 Production method for semiconductor device
WO2012120730A1 (en) * 2011-03-09 2012-09-13 住友電気工業株式会社 Production method for semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573534B1 (en) 1995-09-06 2003-06-03 Denso Corporation Silicon carbide semiconductor device
US5952679A (en) * 1996-10-17 1999-09-14 Denso Corporation Semiconductor substrate and method for straightening warp of semiconductor substrate
JP2000012482A (en) * 1998-06-22 2000-01-14 Fuji Electric Co Ltd Method for manufacturing silicon carbide semiconductor device
JP2002314071A (en) * 2001-04-18 2002-10-25 Denso Corp Method for manufacturing silicon carbide semiconductor device
WO2012120731A1 (en) 2011-03-09 2012-09-13 住友電気工業株式会社 Production method for semiconductor device
WO2012120730A1 (en) * 2011-03-09 2012-09-13 住友電気工業株式会社 Production method for semiconductor device
JP2012190864A (en) * 2011-03-09 2012-10-04 Sumitomo Electric Ind Ltd Manufacturing method for semiconductor device
US8765617B2 (en) 2011-03-09 2014-07-01 Sumitomo Electric Industries, Inc. Method of manufacturing semiconductor device

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