JPH0786414A - Semiconductor device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Wiring of the layer with the strictest placement / wiring spacing according to design rules for the grid for automatically placing / wiring each element of each layer constituting the semiconductor integrated circuit By diagonally wiring, it is possible to set an interval of the grid to an optimum value that satisfies all design rules, and to provide a high-density semiconductor device with high wiring efficiency. [Structure] Only the wiring of the layer that is the most strict by the design rule is diagonally wired with respect to the above grid, and the distance between the diagonal wiring of the layer that is the most strict by the design rule is limited by the design rule. Within the range that satisfies the design rule of the strictest layer, and within the range that the placement and wiring interval of each element of each layer other than the layer with the strictest restriction satisfies the design rule of the strictest layer, The angles of the grid and the diagonal wiring are set so that the grid is minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having high wiring efficiency and high density.

[0002]

2. Description of the Related Art A large-scale semiconductor integrated circuit (hereinafter referred to as LSI: Large Scale) such as a gate array method or a standard cell method is used by using an automatic placement and routing program.
Described as Integrated Circuit. )
When creating the layout pattern, it is necessary to set the grid so as to satisfy the design rule (design rule) of each element of each layer that constitutes the LSI, for example, each element such as a metal layer, a polysilicon layer, and a diffusion layer. There is. With the grid, in the automatic placement and routing program,
The minimum spacing (minimum unit) for arranging the respective elements so as to satisfy the design rule, and the respective elements are arranged on the grid.

Each of the elements has a unique design
Since there is a rule, and in the automatic placement and routing, each element needs to satisfy all the respective design rules, the grid spacing is determined by the most restrictive element design rule. The most restrictive element is a metal layer element at present. In particular, it is expected that the design rule of the metal layer will become a bottleneck in the processes before the 0.5 μm (micron) process. Thus, when the grid determined by the metal layer is used, the LSI
As a whole, the density cannot be increased. In particular, there is a problem that the density of the entire LSI cannot be increased even if the miniaturization of other elements, for example, each element such as a polysilicon layer and a diffusion layer is significantly advanced compared to the metal layer forming technique.

Therefore, in some cases, the density can be increased by deciding the grid according to the design rules of layers (elements) other than the metal layer and arranging the metal layer at intervals of twice or three times that. . However, if the grid is determined by the design rule of the layer other than the metal layer in this way, the wiring of the metal layer naturally causes a design rule error at the grid interval. Therefore, even if the design rule of the metal layer is, for example, 1.5 times the grid spacing, the wiring of the metal layer must be wired at the double grid spacing. But,
In such a configuration, the metal layer wiring is
Since it is not a rule, there is a problem that high density is hindered accordingly.

Here, the problems of the above-described conventional technique will be described in detail with reference to FIGS. 4 and 5 showing the conventional example.
FIG. 4 is a layout pattern showing the wiring state of the metal 1 layer and the metal 2 layer when the layout and wiring are performed using the grid 4 set according to the design rule of the layers other than the metal layer. The grid 4 shown in FIG. 4 is assumed to satisfy the design rules of all layers except the metal layer.
In FIG. 4, the wiring in the vertical direction is the wiring 1 in the first metal layer, and the wiring in the horizontal direction is the wiring 2 in the second metal layer. In the example of the wiring shown in FIG. 4, VI is provided at a position where the wiring 1 of the metal 1 layer and the wiring 2 of the metal 2 layer intersect.
An A hole (connection element) 3 connects the wiring 1 of the metal 1 layer and the wiring 2 of the metal 2 layer. In addition,
The VIA hole 3 is provided so that its center is at the center of the grid 4.

In the layout pattern shown in FIG. 4, the spacing between the wirings 2 of the metal 2 layer in the VIA hole 3, that is, the spacing between the wirings 2 of the left and right and upper and lower metal 2 layers is too small, so that the design rule is satisfied.・ An error occurs. This is exactly the same for the wiring 1 of the first metal layer. That is, when the grid 4 shown in FIG. 4 is placed and wired as a unit, a design rule error occurs in the wiring of the metal 1 layer and the metal 2 layer, and it cannot be used in the actual manufacturing process.

Therefore, when the automatic placement and routing is performed in units of the grid 4 having the same grid spacing as in FIG. 4, in order to satisfy the design rule of the metal layer, a metal pattern like the layout pattern shown in FIG. It is necessary to wire the wires 1 and 2 of the first layer and the metal second layer at a grid interval of twice or more. Here, when the wirings 1 and 2 of the metal 1 layer and the metal 2 layer are wired at a double grid interval as in the illustrated example, the design rule of the metal layer is satisfied. Therefore, in the layout pattern shown in FIG. 5, even in the VIA hole 3, the space between the wiring 1 of the metal 1 layer and the wiring 2 of the metal 2 layer, that is, between the wiring 1 of the left and right and the upper and lower metal 1 layers and the metal The distance between the wirings 2 of the two layers is sufficiently wide and does not cause a design rule error. However, when the wirings 1 and 2 of the metal 1 layer and the metal 2 layer are wired at a double grid interval, for example, if the design rule of the metal layer is 1.5 times the grid interval, Since the above design rule is not the minimum design rule, there is a problem in that the density of the entire LSI is hindered as described above.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to design a grid for automatically arranging and wiring each element of each layer constituting a semiconductor integrated circuit in order to solve the above-mentioned problems of the prior art.・ By diagonally laying the wiring of the layer with the strictest restrictions on the placement and wiring spacing by rules, for example, the wiring of the metal layer, the grid spacing can be set to the optimum value that satisfies all the design rules. It is an object of the present invention to provide a highly densified semiconductor device.

[0009]

DISCLOSURE OF THE INVENTION According to the present invention, only the wiring of the layer, which is most severely restricted by the design rule, is diagonally wired with respect to the grid for automatically placing and wiring the elements of each layer constituting the semiconductor integrated circuit. However, the distance between the diagonal wirings of the layer that is the most restrictive by the design rule is within the range that satisfies the design rule of the layer that is the most restrictive by the design rule, and the layer that is the most restrictive by the design rule is The angle of the grid and the diagonal wiring is set so that the grid is minimized within a range in which the layout and wiring distance of each element of each layer other than the above satisfies the design rule of the layer that is most severely restricted by the design rule. The present invention provides a semiconductor device characterized by the above. Further, it is preferable that the layer most severely limited by the design rule is a metal layer.
Further, it is preferable that the layer that is most restricted by the design rule is wired at an angle of 45 ° with respect to the grid.

[0010]

According to the semiconductor device of the present invention, a grid for automatically arranging and wiring the respective layers constituting the semiconductor integrated circuit is provided with a layer having the strictest restriction on the arrangement and wiring intervals by the design rule, for example, a metal layer wiring. By wiring diagonally at a predetermined angle to the grid, the spacing of the grid is within a range that satisfies the design rule of each layer other than the metal layer, and between the wirings of the metal layers diagonally wired to the grid. Within the range where the spacing satisfies the design rule of the metal layer, the inclination angles of the grid and the metal wiring with respect to the grid are set so that the grid is minimized, and the optimized grid and diagonal wiring are set. The wiring of each element of each layer and the metal layer is performed by using the above. For this reason, the semiconductor device of the present invention has high wiring efficiency, and therefore it is easy to increase the density of the semiconductor device.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings. Figure 1
3A is a layout pattern of an embodiment of a semiconductor device according to the present invention. In the following description,
Although the metal wiring layer will be described as a representative example of the layer having the strictest restriction on the arrangement and wiring distance by the rule, the present invention is not limited to this. Layout shown in Figure 1
The pattern is the layout pattern shown in FIG.
The wiring is the same except that the wiring is changed to a wiring of 2 degrees and the wiring 2 of the second metal layer is changed from a wiring in the horizontal direction to a wiring having an angle of 45 ° diagonally upward to the right. A number is attached and the description is omitted.

In the following description, it is assumed that the spacing of the grid 4 is set to satisfy the design rule of each layer other than the metal layer, preferably the minimum value A thereof.

In the layout pattern shown in FIG. 1, since the wiring 1 of the metal 1 layer and the wiring 2 of the metal 2 layer are wired at an inclination angle of 45 °, the wiring 1 of the metal 1 layer and the wiring 1 of the metal 1 layer are formed. And the distance between the wiring 2 of the metal 2 layer and the wiring 2 of the metal 2 layer are both √2.
The grid spacing is doubled (about 1.4 times), and although the spacing of the grid 4 is A, the spacing between the diagonal wirings is √2A (about 1.4A). Here, when the spacing √2A between the diagonal wirings of each of the wirings 1 and 2 of the metal 1 layer and the metal 2 layer both satisfy the design rule of the metal layer, the spacing of the grid 4 can be A. Therefore, as long as the spacing √2A between the diagonal wirings of the metal layer satisfies the design rule of the metal layer, the grid 4 is set to have the minimum value within the range that satisfies the design rule of each element of each layer. It suffices to determine the interval A. For example, if the design rule of the metal layer is B, the spacing A of the grid 4 may be B / √2 or more in order to satisfy the design rule of the metal layer. Therefore, when the design rule B of the metal layer is √2A or less, the grid interval is A, and when the design rule B of the metal layer is larger than √2A,
The interval between the grids 4 may be B / √2. Furthermore, V
Since the IA holes 3 are also arranged at the upper, lower, left, and right sides with a double grid interval, the VIA holes 3 and the left and right VIs are arranged.
The distance between the A hole 3 and the upper and lower VIA holes 3 is sufficiently wide, and the design rule error does not occur. Of course, when the spacing of the grid 4 is determined, it is preferable to use the spacing between the wirings in the VIA hole 3 where the conditions are the most severe as the spacing between the wirings of the metal layer.

In the above embodiment, the case where the wiring of the metal layer is wired at an angle of 45 ° has been described, but the present invention is not limited to this, and the inclination angle of the oblique wiring with respect to the grid 4 is designed. As long as the rule is satisfied and the distance between the grids 4 can be minimized, it may be any number of times, for example, 30 ° or 60 °. In particular, when the density of the wiring 1 of the first metal layer and the density of the wiring 2 of the second metal layer are different, it is preferable to set the inclination angle to an angle other than 45 ° depending on the difference in the wiring density. Also,
Although the wiring 1 of the metal 1 layer descends to the right and the wiring 2 of the metal 2 layer rises to the right, the wiring 1 of the metal 1 layer may rise to the right and the wiring 2 of the metal 2 layer may descend to the right.
Further, the number of metal wiring layers may be three or four. In addition, the grid interval and its arrangement method are arbitrary, and may be grid-like at regular intervals as in the above embodiment, for example, a rectangle or a ratio of 1: 2: 3. May be placed in.

As described in detail above, according to the present invention, the wiring of the metal layer is designed in each layer other than the metal layer.
The grid interval can be made smaller than that in the case where wiring is performed at twice the grid interval determined by the rule, and the minimum value of the design rule of each layer other than the metal layer can be approached. Further, the grid is set in the present invention so that the distance between the metal by the diagonal wiring satisfies the design rule of the metal layer and also satisfies the design rules of the layers other than the metal layer.
That is, the angle and grid spacing are such that the metal-to-metal spacing is the minimum of the metal layer design rules, and the closest value to the grid minimum determined by the design rules other than the metal layer is the grid. Is to be set as.

FIG. 2 shows a NAN having a CMOS structure as an embodiment which constitutes an internal circuit of a semiconductor device according to the present invention.
It is a layout pattern of the D gate. Also, FIG.
Is a CMOS NAN corresponding to the layout pattern of the CMOS NAND gate shown in FIG.
It is a transistor circuit diagram as an example of a D gate.

The NAND gate shown in FIG. 3 includes P-channel transistors (hereinafter referred to as PMOS) 5a and 5a.
b and N-channel transistors (hereinafter referred to as NMOS) 6a and 6b. The PMO
The sources of S5a and 5b are both connected to the power supply Vdd, the source of the NMOS 6b is connected to the ground GND, and similarly, the drain is connected to the source of the NMOS 6a, the drain of the NMOS 6a, and the PMO.
The drains of S5a and 5b are short-circuited to output the output signal line C. Also, the PMOS 5b and the NMOS
An input signal line A is input to the gate of 6a, and similarly, an input signal line B is input to the gates of the PMOS 5a and the NMOS 6b.

The layout pattern shown in FIG. 2 is a layout pattern in which the NAND gate shown in FIG. 3 is constructed as an embodiment constituting an internal circuit of the semiconductor device of the present invention.
Because it is a pattern, VIA hall 3, grid 4, N
The elements are the same except that the diffusion layer 7, the P diffusion layer 8 and the contact hole 9 are provided. Therefore, the same components are designated by the same reference numerals, and the description thereof will be omitted. Figure 2
In FIG. 3, the wiring line to the lower right is the wiring line 1 in the first metal layer, and is, for example, the power supply Vdd, the ground GND, and the signal line C.
Similarly, the wiring to the right is the wiring 2 of the second metal layer,
For example, the wiring connected to the source of the PMOS 5a, P
The wiring is connected to the drains of the MOSs 5a and 5b. Further, the signal lines A and B input to the gates of the PMOS and the NMOS are wirings of the polysilicon layer, and thus are wired in the vertical direction.

In the layout pattern shown in FIG. 2, since the interval of the grid 4 is set to the minimum value as compared with the conventional layout pattern, the wiring efficiency is very good and the layout pattern is constructed. Area is also smaller.

[0020]

As described in detail above, according to the present invention, in the grid set in the automatic placement and routing program used when creating the layout pattern of the LSI, the placement and routing interval according to the design rule is set. By laying wiring of a layer having the strictest limitation, for example, a metal layer obliquely with respect to the grid, the grid spacing is set to be equal to the design of all elements constituting the LSI.
The minimum value that satisfies the rule can be set, and the wiring efficiency is improved. In addition, since the wiring efficiency is good, the area for forming the layout pattern of each circuit forming the LSI is also small, so that the density of the LSI can be easily increased.

[Brief description of drawings]

FIG. 1 is a layout pattern as an example of a semiconductor device according to the present invention.

FIG. 2 is a layout pattern of a NAND gate having a CMOS structure as an embodiment constituting an internal circuit of a semiconductor device according to the present invention.

FIG. 3 is an equivalent circuit diagram of the NAND gate having the CMOS structure shown in FIG.

FIG. 4 is a layout pattern of an example in which an interval between wirings of metal layers of a conventional semiconductor device is one grid.

FIG. 5 is a layout pattern of an example in which the interval between wirings of a metal layer of a conventional semiconductor device is 2 grids.

[Explanation of symbols]

 1 metal 1 layer wiring 2 metal 2 layer wiring 3 VIA hole (connection element) 4 grid 5a, 5b P channel transistor (PMOS) 6a, 6b N channel transistor (NMOS) 7 N diffusion layer 8 P diffusion layer 9 contact Hall A, B, C Signal line Vdd Power supply GND Ground

Claims (3)

[Claims] 1. A grid for automatically arranging and arranging each element of each layer constituting a semiconductor integrated circuit is diagonally wired only in a layer which is most severely restricted by a design rule, and is restricted by the design rule. The distance between the diagonal wirings of the layer with the strictest is within the range that satisfies the design rule of the layer with the strictest restriction by the design rule, and the placement of each element of each layer other than the layer with the strictest restriction by the design rule The semiconductor device is characterized in that the angle of the grid and the diagonal wiring is set so that the grid is minimized within a range in which the wiring interval satisfies the design rule of the layer that is most severely restricted by the design rule. . 2. The semiconductor device according to claim 1, wherein the layer most severely limited by the design rule is a metal layer. 3. The semiconductor device according to claim 1, wherein the layer that is most restricted by the design rule is wired at an angle of 45 ° with respect to the grid.