JPH0783246B2 - CMOS pseudo open drain circuit - Google Patents

Description

The present invention relates to a CMOS pseudo open drain circuit for wired or ORing the output of a CMOS gate array.

[Conventional technology]

Conventionally, an open drain (open collector) circuit is generally used in a logic circuit. An open drain circuit is a circuit for taking wired or output of outputs of a plurality of integrated circuits (ICs). As shown in Fig. 3 (1), the structure is such that multiple drivers 410, ..., 510 in IC400 ,.
Therefore, drive the common signal line 30. This signal line
30 is pulled up by resistor 40. Each movement
When any one of the output signals S supplied from inside the IC becomes high level, the drivers 410, ..., 510 are turned on and the wired or signal OD on the signal line 30 becomes low level, and all output signals When S becomes low level, the drivers 410, ..., 510 are turned off, and the pull-up resistor 40 works to return the wired or signal OD to high level. Therefore, the wired or signal OD is the logical OR of the negative outputs of the plurality of outputs S. Here, the value of the pull-up resistor 40 is
In order to make the rise time t ₁ of the OR signal OD ((2) in FIG. 3) sufficiently small, it must be a small value, and therefore the output drive capability of the drivers 410, ..., 510 must be made sufficiently large. . For example, considering the case where the power supply voltage is 5 V and the parasitic capacitance of the output line 30 is 100 pF, in order to set the rising time constant of the wired or signal OD to 10 ns,
The value of pull-up resistor 40 must be 10 (ns) / 100 (pF) = 100 (Ω), and the driving capacity of the driver must be 5 (V) / 100 (Ω) = 50 (mA) or more. .

However, when an open drain circuit is to be configured with a CMOS gate array, a normal gate array circuit does not have a driver 410 having such a large driving capability. Therefore, conventionally, the three-state buffer 610 composed of CMOS in the CMOS gate array 600, ..., 700 is used as a pseudo open drain circuit, and this is used as a pull-up resistor.
Was connected to 60. In this circuit, when the output signal S to one of the three-state buffers 610 is at the high level, the three-state buffer 610 is turned on and the wired or signal OD can be set to the low level. When the inputs S to all the three-state buffers 610 are low level, the respective buffers are in a high impedance state, and the wired or signal OD becomes high level due to the function of the pull-up resistor 60. A wired OR circuit using this circuit is disclosed, for example, in Japanese Patent Laid-Open No. 62-25355.
Is disclosed in.

[Problems to be Solved by the Invention]

In the above conventional technology, the current drive capability of the three-state buffer, which is generally composed of CMOS, is small, so the pull-up resistor
There is a drawback in that the value of 60 cannot be made small and the rise time t ₂ (2 in FIG. 4) of the output OD becomes very long. For example, as before, the power supply voltage is 5V, the output line 50
Assuming that the driving capacity of the three-state buffer 610 is up to 5mA when the parasitic capacitance of 100pF is 100pF, the pull-up resistance value must be 5 (V) / 5 (mA) = 1 (kΩ) or more. The time constant of the rise time of the wired or signal OD becomes 1 (kΩ) × 100 (pF) = 100 (ns) or more.

Therefore, when the machine cycle of the device having such an open drain circuit is about 50 ns, the rise time t ₂ of the wired OR signal OD becomes longer than the machine cycle. Therefore, such a pseudo open drain circuit has a drawback that it can be used only when a long rise time of the wired or signal OD is allowed.

An object of the present invention is to provide a pseudo open drain circuit that uses a CMOS three-state buffer and has a fast rise of the wired-OR signal OD.

[Means for Solving the Problems]

The above object is to provide a circuit which is supplied to the input of a tri-state buffer and which supplies a high level signal as an enable signal to the buffer during a high level and for a certain period immediately after the signal changes from the high level to the low level. It is achieved by

[Action]

With the above circuit, the output of the three-state buffer is temporarily changed to the high level before the output changes from the low level to the high impedance state. Since this change is driven by the gate of the CMOS, the rise time of the signal can be a small value of only the delay time of the gate (usually about 10 ns). After that, even if the output changes from the high level to the high impedance state, the wired or signal is held at the high level by the pull-up resistor. Therefore, the rise time of the wired or signal can be improved.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. In FIG. 1, 100, 200, 300 are CMOS gate arrays, 10 is an output signal line for taking wired OR of the output SOD of each gate array 100, 200, 300, and 20 is a pull-up resistor for pulling up the output signal line. The circuit inside the gate array is shown only inside 100, and the others are the same. Reference numeral 140 is a three-state buffer for forming a pseudo open drain circuit, 110 and 120 are latches, and 130 is an OR gate. The feature of this circuit is that a register 110,1 is provided between the output signal S supplied from the inside of each gate array and the three-state buffer 140.
A pulse circuit 1000 including 20 and a gate 130 is added, and immediately before the output SOD of the three-state buffer 140 is turned off, in response to the output signal S of the gate array, the output SOD changes from low level to high level. The pulse circuit 1000 supplies the input SD and the output enable signal SOE to the buffer 140.

The operation of this circuit will be described with reference to the time chart shown in FIG. The dotted line in the figure indicates that the three-state buffer 140 is in a high impedance state. Gate array 10
The output signal S of 0 is latched in synchronization with the system clock T 1.
Set to 10, its output SD is a three-state buffer
It is given to 140 as an input signal. The signal SD is set in the latch 120 in synchronization with the clock T. The output SDD is the output SD of the latch 110 delayed by one clock. Output enable S of three-state buffer 140
OE is given by the OR gate 130 as a logical sum of the signals SD and SDD, and is at the high level for a period longer than the signal SD by one cycle. Therefore, the output SOD of the three-state buffer 140
Holds a low level while SD, which is an output signal S synchronized with a system clock, is at a high level. After that, when the signal SD becomes low level, the output SOD becomes high level for one cycle during which the signal SOE is continuously high level, and then becomes high impedance state. Here, the delay time when the signal SOD changes from the low level to the high level is determined only by the delay of the three-state buffer 140, regardless of the value of the pull-up resistor 20 or the parasitic capacitance of the circuit, so the delay time is high. Can be done.

Therefore, the output SOD of a plurality of gate arrays 100, 200, 300 is connected via the pull-up resistor 20 to the wired or signal OD.
Becomes low level when any one of the output signals S of the gate array becomes high level, and otherwise becomes high level by the action of the pull-up resistor 20. Therefore, the output S of each gate array 100, 200, 300 is converted by the circuit of FIG.
The wired OR can be taken, and it functions as a pseudo open drain circuit of the circuit of FIG.

Another embodiment of the present invention is shown in FIG. In the figure, the same reference numbers and signals as in FIG. 1 refer to the same. In the pulse circuit 1000A of FIG. 5, reference numeral 1120 denotes a group of buffer gates that are connected in series in 10 stages, and the output signal S of the gate array is
Used to delay the. The difference between the circuit of FIG. 1 (1) and the circuit of FIG. 5 (1) is that the latch 120 in FIG.
Signal for controlling the output enable signal SOE of the three-state buffer 140 (SO
D) is made, while gate group 1 is shown in Fig. 5 (1).
A gate delay of 120 is used. In FIG. 5A, the output signal S is directly supplied to the OR gate 130 and the buffer 140 without synchronizing the output signal to the system clock as is done in the latch 110 of FIG. ing. The output enable SOE of the three-state buffer 140 is created by the logical sum of the output signal S and its delay signal SG.

FIG. 5 (2) shows the operation timing of the circuit of FIG. 5 (1). Here, TD is a delay time due to the gate group 1120.
The output SOD of the gate array 100 becomes low level while S is high level, and then becomes high level only during TD. In other periods, SOD is in high impedance state.
The change from the low level to the high level is performed at high speed as in the case of FIG. Therefore, as in the case of FIG. 1, a high speed pseudo open drain circuit can be constructed using the CMOS gate array.

The circuit of FIG. 1 is used when the signal on the bus 10 needs to be synchronized with the system clock T, while the circuit of FIG. 5 is used when it is not necessary to synchronize with the system clock. It can be realized with a smaller number of gates than the circuit in the figure.

〔The invention's effect〕

According to the present invention, when the pseudo open drain circuit is configured by the CMOS gate array, the delay of the rising of the wired OR signal is determined by the gate delay from the value (about 100 ns) determined by the pull-up resistor and the parasitic capacitance of the circuit. It is possible to improve the value (about 10 ns) by about one digit.

Further, when the circuit of the present invention is used, the delay of the circuit becomes independent of the value of the pull-up resistor, so that the value of the pull-up resistor can be increased, which is useful for reducing the power consumption of the circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a timing chart of the operation of the circuit of FIG. 3 (1) is a diagram of a conventional open drain circuit using a driver, (2) is its operation timing chart, and FIG. 4 (1) is a diagram of a conventional pseudo open drain circuit using a tristate buffer. (2) is a timing chart of the operation. FIG. 5 (1) is a diagram showing another embodiment of the present invention, and FIG. 5 (2) is a timing chart of its operation. 140 …… Three-state buffer for outputting pseudo open drain signal, 110, 120 …… Register, 1120…
... a group of buffer gates.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiromitsu Maeda 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Pref., Kanagawa factory, Hiritsu Seisakusho Co., Ltd. (56) References JP-A-1-290313 (JP, A)

Claims (1)

[Claims] 1. A three-state buffer 140 is provided at each of the output sections of a plurality of CMOS gate arrays, and the output signal SOD of each of the three-state buffers is wired.
In the CMOS pseudo open drain circuit ORed and connected to the common pull-up resistor 20, each of the plurality of CMOS gate arrays outputs an output signal S output from the inside of the CMOS gate array.
Is synchronized with the system clock T and outputs the output signal SD, and the output signal SD of the first latch 110 is delayed by one clock in synchronization with the system clock T and the output signal SDD is output. The three-state buffer 140, which is provided with a second latch 120 that performs the above operation, and an OR gate 140 that outputs the output signal SOE by ORing the output signal SD of the first latch 120 and the output signal SDD of the second latch 120. Is configured to receive the output signal SD of the first latch 110 as an input signal, the output signal SOE of the OR gate 140 as an enable signal, and output the output signal SOD. The output signal SOD of the first latch remains low level while the output signal SD of the first latch input as the input signal is high level, and then the output signal SD of the first latch becomes low level. Then, the output signal SOE of the OR gate 140, which is input as an enable signal, is continuously set to a high level for one cycle and then is set to a high impedance state. Pseudo open drain circuit.