JPH0783703A - Absolute encoder - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To provide an absolute encoder having a small ROM capacity for absolute position conversion and having less variation in the time required to convert to an absolute position. [Structure] A code plate 1 on which an absolute pattern is formed, and a detection element which moves relative to the code plate 1 and is arranged corresponding to the absolute pattern, and which detects the absolute pattern and outputs a bit signal Means 2 and an absolute value conversion means 3 that can convert only a specific bit pattern signal to an absolute value among the bit signals, and a bit signal is selected to be a specific bit pattern signal that can be converted by the absolute value conversion means 3. Up to the above, there is provided a signal selecting means for selecting a bit signal, and a calculating means 5 for calculating the position information of the code plate with respect to the detecting means based on the convertible bit signal and the number of selections in the signal selecting means. Characterize.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder, and more particularly to an absolute pattern to absolute position converting means.

[0002]

2. Description of the Related Art For example, as a conventional absolute encoder for converting an absolute pattern of a maximum period series (M series) into an absolute position, Japanese Patent Laid-Open No. 57-17521.
There is an absolute encoder disclosed in Japanese Patent Publication No. 1 and Japanese Patent Laid-Open No. 63-231215. JP-A-57-17
In the absolute encoder disclosed in Japanese Patent No. 5211, a ROM is used as an absolute position conversion means, and the absolute position of the detected position is directly obtained from each detected absolute signal. In other words, the ROM, which is a lookup table for converting the detection data into the absolute position, is used so that the absolute position conversion can be performed at all the detection positions representing the absolute position.

On the other hand, in the absolute encoder disclosed in Japanese Unexamined Patent Publication No. 63-231215, after clearing the reference M code generation circuit, the M corresponding to the rotational position (θ) of the code plate is input every time one clock pulse is input. Different M codes are sequentially output until the code (m) is reached. M code (m) corresponding to the rotational position (θ) from the reference M code generation circuit
When is output, by counting the number of clock pulses input until the M code (m) is output, it can be seen that the M code (m) corresponds to the rotational position (θ). It is the one.

[0004]

As described above, in the conventional absolute encoder, the absolute position conversion is performed by the ROM or the pattern generating circuit. In the former case where the absolute position conversion is performed by the ROM for all positions, the capacity of the ROM increases as the number of pulses of the absolute encoder (the number of minimum reading units) increases. For example, when 2 ⁿ pulses become 2 ^{n + 1} pulses, the ROM capacity becomes 2 · (n + 1) / n times. For this reason, the absolute encoder circuit is a semi-custom I such as a gate array.
If created in C, most of the number of gates of the semi-custom IC is used for the ROM part for absolute position conversion, and it cannot be used as the control part of the encoder. There was an inconvenience that it was not possible.

In the latter case where the absolute position conversion is performed by the pattern generating circuit, the time required for the absolute position conversion varies greatly depending on the absolute pattern, that is, depending on the positional relationship between the reference position and the detected position. For example, with an absolute encoder with 2048 pulses at a clock of 1 MHz, the required time is 1 μs and the maximum is 2.048.
ms. Therefore, when controlling a motor or the like using an absolute encoder, there is a disadvantage in that it is difficult to perform stable control because the required time difference is too large. The present invention has been made in view of the above problems, and an object of the present invention is to provide an absolute encoder in which the capacity of a ROM for absolute position conversion is small and the variation in the time required to convert to an absolute position is small. To do.

[0006]

In order to solve the above-mentioned problems, in the present invention, P (2 ^n-1 <P ≦ 2 ⁿ , n is a positive integer) minimum read units are formed. And a code plate having an absolute pattern in which one absolute value is represented by an n-bit pattern, and (n + m) (m is 1 or more) arranged relative to the code plate and arranged corresponding to the absolute pattern. (N + integer) detection element, and reads the absolute pattern (n +
m) detecting means for outputting a bit signal, and (n + m)
Among the bit signals, an absolute value conversion unit that can convert only a specific n-bit pattern signal corresponding to a specific n-bit pattern into the absolute value, and an n-bit signal is selected from the (n + m) bit signals, Until the n-bit signal becomes the specific n-bit pattern signal that can be converted by the absolute value conversion means, a signal selection means that selects the n-bit signal, the n-bit signal that can be converted and the selection in the signal selection means An absolute encoder is provided, which comprises: a calculating unit that calculates the position information of the code plate with respect to the detecting unit based on the number of times.

According to a preferred aspect, the signal selecting means selects the n-bit signal in the order of pattern arrangement formed in the absolute pattern.

[0008]

In the absolute encoder of the present invention, an absolute signal composed of (n + m) binary number sequences is detected from P (2 ^n-1 <P ≦ 2 ⁿ ) absolute patterns. Here, among the (m + 1) n-bit patterns included in the detected (n + m) binary sequence,
At least one n-bit pattern is constructed so that it can be directly converted into an absolute value and thus an absolute position. Thus, the absolute position a of the convertible n-bit pattern and the relative position k with respect to the detected position of the convertible n-bit pattern in the detection data are obtained. The relative position information k (0
≦ k ≦ m) and the absolute position information a of the n-bit pattern capable of absolute position conversion described above, the absolute position ak of the detected position can be obtained by performing calculation of ak, for example.

As described above, in the absolute encoder of the present invention, absolute position conversion is not possible at all detection positions directly, but absolute position conversion is possible only at a specific detection position. Therefore, the capacity of the ROM can be suppressed to a desired range by appropriately limiting the number of n-bit patterns that can be directly subjected to absolute position conversion. Further, the maximum time required to obtain the absolute position ak of the detected position depends on the absolute position interval of the n-bit pattern in which the absolute position can be converted. In other words, by appropriately securing the number of n-bit patterns capable of absolute position conversion and making the absolute position intervals substantially equal, it is possible to suppress the variation in the time required to convert the absolute positions to a desired range. It will be possible.

[0010]

Embodiments of the present invention will be described with reference to the accompanying drawings. 1 is a block diagram schematically showing a configuration of an absolute encoder according to a first embodiment of the present invention. Further, FIG. 2 is an absolute pattern generated by the generator polynomial of X ⁵ + X ³ + X ⁰ , and is a pattern in which one 0 is inserted in a portion where four 0s are consecutive in a 5th-order M series (maximum period series) pattern. Is. In other words,
The absolute pattern in FIG. 2 is a sequence of 2 ⁵ = 32 binary numbers, and 32 reading patterns are possible.

The absolute encoder shown in FIG.
Code display means 1 on which an absolute pattern of
Is equipped with. The code display means 1 has a binarized pattern in which, for example, in the case of an optical type, the shading is 1 and the transmission is 0. The absolute encoder shown in the figure further includes detection means 2 for reading the pattern information of the code display means 1 and converting it into a digital signal. The detection means 2 is composed of, for example, nine detection elements such as a photodiode array, and outputs detection data in parallel or serially via the output line 2-1.

The output 2-1 of the detecting means 2 is connected to the input of the absolute position convertible pattern position recognizing means 4.
In the absolute position convertible pattern position recognizing means 4, the absolute position converting means 3 receives five kinds of 5-bit pattern signals consisting of five consecutive number sequences in the inputted nine binary number sequences via the output line 4-1. To output sequentially. The absolute position conversion means 3 is configured to be able to directly perform absolute position conversion on the eight types of 5-bit sequence pattern signals shown in FIG. 3 among the above-mentioned 32 reading patterns. In other words, in the absolute position conversion means 3, 8 shown on the left side in the figure.
Absolute position conversion is possible for each type of 5-bit pattern signal, and each is converted to the absolute position shown on the right side of the drawing. Thus, in this example, n is 5, m is 4, and P is 32.

The absolute position conversion means 3 determines whether or not the input sequence pattern can be directly converted into an absolute position. The determination signal is input to the absolute position convertible pattern position recognition means 4 via the output line 3-1. When the conversion is possible, the absolute position conversion means 3 outputs the convertible 5-bit pattern absolute position information a to the calculation means 5 via the output line 3-2, and the absolute position convertible pattern position recognition means 4 outputs it. The relative position information k of a 5-bit pattern that can be converted is output to the calculating means 5 via the line 4-2. Receiving the position information of both, the calculation means 5 obtains the absolute position of the detected position and outputs it to the output 6 via the output line 5-1.

The operation of the absolute encoder of the present embodiment constructed as described above will be explained based on a concrete sequence of numbers. Of the absolute pattern of the code display means 1, the pattern portion where the nine detection elements of the detection means 2 face each other is read and binarized. Next, the detection data from the detection means 2, that is, 10111011 from the MSB side.
A binary number sequence of 0 is sent to the absolute position convertible pattern position recognition means 4 via the output line 2-1. The absolute position convertible pattern position recognizing means 4 checks whether or not the left 5 bit 10111 of the 9-bit detection data 101110110 can be directly converted into an absolute position via the output line 4-1. It outputs to the absolute position conversion means 3.

As shown in FIG. 3, the absolute position conversion means 3 cannot convert the 5-bit sequence pattern signal 10111 into an absolute position. Therefore, the absolute position conversion means 3 outputs the absolute position conversion impossible signal L via the output line 3-1.
Is output. Upon receiving this absolute position conversion impossible signal L,
The absolute position convertible pattern position recognizing means 4 outputs 01110 which is 1 bit from the left end and 5 bits from the right end of the 9-bit detection data 101110110 to the absolute position converting means 3 via the output line 4-1. Since this 5-bit sequence pattern signal 01110 is also not capable of absolute position conversion,
The absolute position conversion means 3 outputs the absolute position conversion impossible signal L via the output line 3-1.

Thereafter, this operation is repeated until the absolute position conversion can be performed by the absolute position conversion means 3. In this way, the absolute position convertible pattern position recognizing means 4 (n
The signal selecting means is configured to select an n-bit signal from the + m) bit signals and select the n-bit signal until a specific n-bit pattern signal that can be converted by the absolute position converting means 3 is obtained. In this embodiment, finally, data 10110 of 4 bits from the left end and 5 bits from the right end is output to the absolute position conversion means 3 through the output line 4-1. Since this 5-bit sequence pattern signal 10110 is capable of absolute position conversion, the absolute position conversion means 3 outputs the absolute position convertible signal H via the output line 3-1 and the absolute position of the convertible 5-bit pattern. The value a of 0101 (see the 4th line in FIG. 3), that is, 11 in decimal number is output to the calculating means 5 through the output line 3
Output via -2.

On the other hand, from the absolute position convertible pattern position recognizing means 4, it is possible to directly convert a 5-bit sequence from the left end of the detected data 101110110 by 4 bits to the absolute position, that is, absolute position conversion is possible. The value 4 indicating the relative position information k with respect to the detected position of the pattern is output to the calculation means 5 via the output line 4-2.
The calculation means 5 includes absolute position information 11 of directly convertible patterns and relative position information 4 of absolute position convertible patterns.
Based on the above, the absolute position 11-4 = 7 of the detected position is obtained and output via the output line 5-1.

As described above, in this embodiment, the absolute position conversion means 3 directly performs absolute position conversion on eight kinds of 5-bit patterns. There is no problem when the direct conversion to the absolute position is performed by the combinational circuit, but when the direct conversion is performed by the ROM, the address space still needs 5 bits, and the capacity of the ROM cannot be reduced. Therefore, as a second embodiment of the present invention, an absolute encoder is proposed in which eight kinds of 5-bit patterns are logically compressed into 3-bit patterns, the address space is set to 3 bits, and the ROM capacity is reduced to 1/4.

As a logical compression method in the absolute encoder according to the second embodiment, as shown in FIG. 4, there is a method in which the absolute position conversion is possible only in the pattern in which the upper 2 bits of the 5-bit pattern are 00. is there. That is, this is a method in which eight types of 5-bit patterns starting from 00 shown on the left side of the figure can be converted into absolute positions, and are converted to the absolute positions shown on the right side of the drawing, respectively. In this case, it is possible to immediately perform logical compression into a 3-bit pattern by only deleting the upper 2 bits of the 5-bit pattern capable of absolute position conversion. Therefore, as shown in FIG. 5, the 8 types of 3-bit patterns on the left side of the ROM are converted into the absolute positions shown on the right side of the figure, respectively. It is reduced to 1/4.

Further, as shown in FIG. 6, inputs X4 to X0
The same effect can be obtained even if logical compression is performed by a combinational circuit represented by a logical expression that can obtain 3 bits of outputs Y2 to Y0 from 5 bits of In the absolute position conversion of FIG. 4, the absolute positions are unequal intervals, and for example, 00011 on the 4th line (3 in decimal) and 0111 on the 5th line.
As in the case of 1 (15 in decimal), the absolute position interval between adjacent convertible adjacent patterns is 12, which is the maximum. Therefore, in this case, the number of detection elements required in the detection means 2 is 5 + 12-1 = 16.

As described above, in the case of the second embodiment in which the absolute position conversion is made unequal intervals to reduce the ROM address space, the number of detecting elements tends to increase. For this reason,
In order to minimize the number of detecting elements, it is desirable to configure the convertible 5-bit pattern including 00 described above to appear at substantially equal intervals (for example, 5 pitches as in the first embodiment). . Generally speaking, the number P (32 in this embodiment) of the minimum reading unit divided by the number of convertible specific bit signals (8 in this embodiment) is smaller by 1 (3 in this embodiment). ) Has a number of digits (2 in this embodiment) when represented by a binary number (0 in this embodiment).
0) is almost (m +) in the absolute pattern.
1) The pitches (5 pitches in this embodiment) are preferably present at substantially equal intervals. In addition, a convertible 5-bit pattern including a specific 2-bit sequence other than 00 may be configured to appear at substantially equal intervals.

In the above embodiment, the present invention has been described by taking the M-series absolute pattern as an example, but it is obvious that the present invention can be applied to other general absolute patterns. Further, although the present invention has been described in the above embodiment by taking the fifth-order M-series absolute pattern as an example, it is obvious that the present invention can be applied to higher-order absolute patterns. Furthermore, in the above-described embodiment, 00000 is included in the convertible 5-bit pattern,
As is clear from the absolute position interval, it is clear that the present invention can be realized even if this convertible pattern is omitted.

[0023]

As described above, in the absolute encoder of the present invention, the capacity of the ROM, which is the lookup table for converting the absolute pattern into the absolute position, can be greatly reduced to 1/4 or less, and
The time required for absolute position conversion can be shortened to about 2 μs. Therefore, according to the present invention, it is possible to realize a small-sized and cost-effective absolute encoder.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a configuration of an absolute encoder according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an M-sequence absolute pattern.

FIG. 3 is a diagram showing a 5-bit pattern that can be directly converted by an absolute position conversion unit and a corresponding absolute position.

FIG. 4 is another diagram showing a 5-bit pattern that can be directly converted by the absolute position conversion means and the corresponding absolute position, and is the contents of the absolute position conversion means configured for the logical compression of the second embodiment. FIG.

FIG. 5 is a diagram illustrating a second embodiment in which the ROM address space is reduced by logical compression.

FIG. 6 is a diagram showing a logical expression for logical compression.

[Explanation of symbols]

 1 Code Display Means 2 Detecting Means 3 Absolute Position Converting Means 4 Absolute Position Convertible Pattern Position Recognizing Means 5 Computing Means 6 Output

Front Page Continuation (72) Inventor Yuji Yamazaki 471 Nagaodai-cho, Sakae-ku, Yokohama-shi, Kanagawa Prefecture Nikon Yokohama Works

Claims (2)

[Claims] 1. An absolute pattern is formed from P (2 ^n-1 <P ≦ 2 ⁿ , n is a positive integer) minimum reading units, and one absolute value is represented by an n-bit pattern. A code plate and (n + m) (m is an integer of 1 or more) detection elements that move relative to the code plate and are arranged corresponding to the absolute pattern are provided, and the absolute pattern is read ( detecting means for outputting an (n + m) -bit signal; and an absolute value converting means for converting only a specific n-bit pattern signal corresponding to a specific n-bit pattern among the (n + m) -bit signals into the absolute value. An n-bit signal is selected from (n + m) -bit signals, and the n-bit signal is converted into the specific n-bit pattern signal that can be converted by the absolute value conversion means. Signal selecting means for selecting a signal; and calculating means for calculating the position information of the code plate with respect to the detecting means based on the convertible n-bit signal and the number of selections in the signal selecting means. Is an absolute encoder. 2. The absolute encoder according to claim 1, wherein the signal selection means selects the n-bit signal in the order of pattern arrangements formed in the absolute pattern.