JPH0778999A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for fabricating a semiconductor device in which the end of etching can be detected easily while facilitating regeneration of resist. CONSTITUTION:As shown in Fig. B, a polycide layer 6 and a silicon oxide 24 are etched using photoresists 51, 52 as masks. As shown in Fig. C, a gate electrode 26 is formed in the peripheral transistor region M2 and a control gate electrode 16 is formed in the memory cell region M1. Subsequently, the peripheral transistor region M2 is entirely covered with photoresist and etched. In the memory cell region M1, a polysilicon layer 4 and an interlayer insulation film 17 are formed using the silicon oxide 24 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a stack gate etching method.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device such as an EPROM or a FLASH memory, a memory cell region forming a memory cell and a peripheral transistor region are provided in the peripheral portion. There are the following methods for forming the stack gate in the memory cell region and the peripheral transistor region.

The first manufacturing method is shown in FIG. First, as shown in FIG. 4A, a silicon oxide film 9 is formed on the entire surface of the substrate.
A polysilicon layer 4 is formed in the memory cell region M1. An interlayer insulating film 7 is formed on the silicon oxide film 4. From this state, the polycide layer 6 is formed on the entire surface. Next, for the memory cell region M1, the photoresist 31 is selectively
The peripheral transistor region M2 is entirely covered with a photoresist 32. In this state, etch
The polysilicon layer 4, the interlayer insulating film 7, and the polycide layer 6 are molded. As a result, the stack gate 13 including the floating gate 14, the interlayer insulating film 17, and the control gate electrode 16 is formed in the memory cell region M1.

Next, after removing the photoresists 31 and 32, as shown in FIG. 4B, the peripheral transistor region M2 is formed.
Is selectively covered with a photoresist 42, and the memory cell region M
For No. 1, the entire surface is covered with photoresist 41. In this state, etching is performed to mold the polycide layer 6 to form a stack gate in the memory cell region M2.

As described above, in the first method, the memory cell region M1 and the peripheral transistor region M2 are separately etched to form stack gates having different layer thicknesses.

FIG. 5 shows the second method. First, FIG. 5A
As shown in, a silicon oxide film 9 is formed on the entire surface of the substrate. A polysilicon layer 4 is formed in the memory cell region M1. An interlayer insulating film 7 is formed on the silicon oxide film 4. From this state, the polycide layer 6 is formed on the entire surface. The process up to this point is the same as the first method. From this state, both the memory cell region M1 and the peripheral transistor region M2 are selectively covered with the photoresists 11 and 12. In this state, etching is performed to mold the polycide layer 6. This allows
The control gate electrode 16 is formed in the memory cell region M1, and the stack gate 2 in the peripheral transistor region M2 is formed.
8 is formed.

Next, with the photoresists 11 and 12 left, as shown in FIG. 5B, the peripheral transistor region M2 is formed.
The entire surface is covered with photoresist 22. In this state, etching is performed to form the polysilicon layer 4 and the interlayer insulating film 7 to form a stack gate in the memory cell region M1.

As described above, according to the second method, the common layer of the memory cell region M1 and the peripheral transistor region M2 is first etched, and then only the thick region is further etched to form the stack gate. Was there.

[0009]

However, the stack gate manufacturing method as described above has the following problems.

Generally, whether or not the etching is completed is determined by monitoring the rate of change in the amount of etching products generated in the etching process. However, in the first method, the polycide layer 6
In this etching, the memory cell region M1 and the peripheral transistor region M2 are separately etched. Therefore, as compared with the case where the entire surface of the substrate is etched, the etching region is almost halved, and the absolute amount of etching product generated is reduced. As a result, the rate of change in the amount of etching products generated becomes low, and it is difficult to detect the end point of ecking.

The second method has the following drawbacks. In this method, it is necessary to protect the peripheral transistor region M2 from being etched when the memory cell region M1 is etched. That is, the photoresist 2 is applied so that there is no unpainted portion on the photoresist 12.
2 needs to be applied. Generally, the photoresist is applied by a spin-off method. However, it is difficult to apply a new photoresist without a gap because the photoresist 12 having a layer thickness of several μm interferes.

In this case, if the thickness of the photoresist 22 is increased, the photoresist 22 can be applied without leaving any unpainted portion, but it takes time for the material and the forming process. Further, in the second method, if the exposure fails in the formation of the photoresist 22, it is necessary to remove the photoresist that has once failed. However, when the failed photoresist is removed, the photoresist 11 already formed in the memory cell region M1 is also removed together. In this case, it is difficult to reproduce the photoresist having the same shape on the already formed control gate electrode 16.

The present invention solves the above problems, and provides a method for manufacturing a semiconductor device in which the end point of etching can be easily detected and the resist can be formed again even if the photoresist formation fails. The purpose is to do.

[0014]

A method of manufacturing a semiconductor device according to claim 1, wherein a step of forming a first layer on a first substrate region of a semiconductor substrate, the first substrate region and the first substrate are formed. Forming a second layer on a second substrate region that is a semiconductor substrate region other than the region, forming a third layer made of a material other than photoresist on the second layer, Partially covering the third layer with photoresist and selectively etching the third layer; removing the photoresist and covering the second substrate region with photoresist; selectively etching the third substrate region; Third
And a step of selectively etching the first layer using the layer as a mask,
The third layer is different in thickness or material from the first layer, so that the third layer is configured to remain even after the etching process of the first layer is completed.

[0015]

According to the method of manufacturing a semiconductor device of claim 1,
A third layer made of a material other than photoresist is formed on the second layer, the third layer is partially covered with photoresist, and the second and third layers are selectively formed. Etching. As described above, since the entire surface of the second layer is etched once, the end point of etching can be easily detected.

After covering the second substrate region with a photoresist, the first layer is selectively etched using the selectively etched third layer as a mask. Therefore, even if the photoresist formation on the second substrate region fails, the photoresist can be formed again on the second substrate region without affecting the mask for the first layer.

Further, the third layer has a layer thickness or a material different from that of the first layer, and is configured to remain even after the etching process of the first layer is completed. Therefore, the third layer can function as a mask until the etching of the first layer is completed.

[0018]

EXAMPLE An example of the present invention will be described. Figure 1
FIG. 3 shows a method of manufacturing an EPROM which is an embodiment of the present invention. First, as shown in FIG. 1A, a field oxide layer 101 is formed by the LOCOS method to perform element isolation.
Next, a 10 nm silicon oxide film (Si
O ₂ ) is formed by dilute oxidation. Accordingly, the element forming region 103 of the memory cell region M1 which is the first substrate region.
A tunnel oxide film 18 is formed on the surface. In addition, the element forming region 10 of the peripheral transistor region M2 which is the second substrate region.
2 is covered with a silicon oxide film.

Next, a polysilicon layer 4 as a first layer having a thickness of 200 nm is formed on the entire surface of the substrate by the chemical vapor deposition (CVD) method, and then the polysilicon layer 4 is formed by using a photoresist. Etch as shown in 1B.

In this state, after the interlayer insulating film 17 is formed on the entire surface of the substrate, the interlayer insulating film 17 is etched using photoresist as shown in FIG. 1C. In this example, the interlayer insulating film 17 was formed by diluting a 30 nm silicon oxide film by dilution oxidation.

After removing the silicon oxide film on the element forming region 102 in the peripheral transistor region M2, 25
A gate oxide film (SiO ₂ ) 8 having a thickness of nm is formed.

Next, as shown in FIG. 2A, the polycide layer 6 as the second layer is formed to a thickness of 300 nm by the CVD method, and the silicon oxide film (SiO ₂ ) 24 as the third layer 24 is formed. Is formed with a thickness of 100 nm. In the present embodiment, the polycide layer 6 was formed on the polysilicon layer using tungsten silicon (WSi) as silicide.

Thereafter, as shown in FIG. 2B, photoresists 51 and 52 are formed on the memory cell region M1 and the peripheral transistor region M2. And photoresist 5
After etching the polycide layer 6 and the silicon oxide film 24 using the masks 1 and 52 as masks, photoresists 51 and 5
Remove 2.

As a result, as shown in FIG. 2C, the gate electrode 26 and the silicon oxide film 24 are formed in the element forming region 102 of the peripheral transistor region M2. Also,
The control gate electrode 16 and the silicon oxide film 24 are formed in the element formation region 103 of the memory cell region M1.

Next, as shown in FIG. 3A, the peripheral transistor region M2 is entirely covered with a photoresist 31. By etching in this state, the interlayer insulating film 17 and the polysilicon layer 4 are formed in the memory cell region M1 using the silicon oxide film 24 as a mask (see FIG. 3B). As a result, the stack gate 13 including the floating gate 14, the interlayer insulating film 17, and the control gate electrode 16 is formed in the memory cell region M1.

In this embodiment, since the interlayer insulating film 17 is composed of a silicon oxide film, the third film and the interlayer insulating film 1
The etching rates of 7 are equal.

Further, the etching of the polysilicon layer 4 is performed by
CF ₄ gas was used. As a result, the etching rate of the polysilicon layer 4 and the silicon oxide film 24 becomes 5: 1.

After that, the photoresist 31 is removed, impurities are ion-implanted to form a source and a drain, and CVD is performed.
Then, an interlayer insulating film (BPSG) is formed by using the method, an opening is provided, and a source electrode, a drain electrode and the like are formed (not shown).

As described above, in this embodiment, the silicon oxide film 24 is formed on the silicide layer 6, the peripheral transistor region M2 is covered with the photoresist 31, and then the silicon oxide film is selectively etched. Using 24 as a mask, the polysilicon layer 4 and the interlayer insulating film 17 are selectively etched. Therefore, the photoresist 3
In the formation of No. 1, even if the work fails in the coating or exposure step, the photoresist can be formed again.

Since the interlayer insulating film 17 is formed of a silicon oxide film, the interlayer insulating film 17 and the silicon oxide film 24 are formed.
Although the etching rate is 1: 1, the thickness of the silicon oxide film 24 is 100 nm and the thickness of the interlayer insulating film 17 is 50 nm. Therefore, even after the etching of the interlayer insulating film 17 is completed, the thickness of the silicon oxide film 24 is 50
nm remains, and the silicon oxide film 24 can function as a mask.

In this state, the thickness of the silicon oxide film 24 remains 50 nm, and the thickness of the polysilicon layer 4 is 20 nm.
It is 0 nm. Here, the etching of the polysilicon layer 4 is performed under the condition that the etching rate of the polysilicon layer 4 and the silicon oxide film 24 is 5: 1. Therefore, the silicon oxide film 24 can function as a mask until the etching of the polysilicon layer 4 is completed.

In the above embodiment, in order to make the silicon oxide film 24, which is the third layer, function more reliably as a mask until the etching of the polysilicon layer 4, which is the first layer, is completed, the silicon oxide film is used. The layer thickness of 24 may be increased.

In this embodiment, the silicon oxide film 24 is covered with photoresists 51 and 52, and the polycide layer 16 is selectively etched. As described above, since the entire surface of the polycide layer 16 is etched at once, it is possible to easily detect the rate of change of the amount of etching products without decreasing the amount of etching products, and to easily detect the end point of the etching process.

As described above, in this embodiment, as the material of the third layer, the silicon oxide film made of a material different from that of the polysilicon layer 4 which is the first layer is adopted. As described above, when the materials of the third layer and the first layer are different from each other, the etching rates of the both are usually different. The three layers can be used as a mask.

On the other hand, the materials of the third layer and the first layer may be the same. In this case, by increasing the layer thickness of the third layer, the third layer can be used as a mask until the etching of the first layer is completed. When another layer is provided between the first layer and the second layer as in the above embodiment, an etchant capable of selectively etching the other layer may be used.

In this embodiment, the third layer is made of a silicon oxide film, but the third layer may be made of another substance such as a silicon nitride film. In this case, the etching conditions may be such that the silicon nitride film functions as a mask until the etching of the interlayer insulating film 17 and the polysilicon layer 4 is completed.

As described above, the third layer may have any film thickness and material as long as it can selectively etch the first layer as a mask.
In particular, when the third layer is made of an insulating material such as a silicon oxide film or a silicon nitride film, even if it is formed on the stack gate 13 or the gate electrode 26, there is no particular problem in using it as a semiconductor device. The step of removing is unnecessary.

Further, both the layer thickness and the material may be changed instead of the layer thickness or the material.

Although the silicon oxide film 24 is formed by the CVD method in this embodiment, it may be formed by thermal oxidation. The same applies when a silicon nitride film is used for the third layer.

Further, the interlayer insulating film 17 may be formed of an ONO film composed of three layers of a silicon oxide film, a silicon nitride film and a silicon oxide film. For example, a 20 nm silicon nitride film is formed on a 10 nm silicon oxide film,
When a 5 nm silicon oxide film is formed thereon, etching may be performed using a mixed gas of CHF ₃ and O ₂ as etching conditions.

By performing etching under such conditions, the silicon nitride film can function as a mask until the etching of interlayer insulating film 17 and polysilicon layer 4 is completed.

In this embodiment, the case of using it for the EPROM has been described, but the present invention is not limited to this, and can be applied to any semiconductor device having a stack gate having a different layer thickness. it can.

Further, in this embodiment, the interlayer insulating film is formed between the first layer and the second layer.
The present invention can be applied to the case where such an insulating film is not provided between the second layer and the second layer.

[0044]

According to the method of manufacturing a semiconductor device of the first aspect, a third layer made of a material other than photoresist is formed on the second layer, and the third layer is partially formed. Cover with photoresist and selectively etch the second and third layers. Therefore, it is easy to detect the end point of etching. Further, after covering the second substrate region with a photoresist, the first layer is selectively etched using the selectively etched third layer as a mask. Therefore, the photoresist can be formed again.

That is, it is possible to provide a method of manufacturing a semiconductor device in which the end point of etching can be easily detected and the photoresist can be formed again even if the photoresist formation fails.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of an EPROM according to the present invention.

FIG. 2 is a diagram showing a manufacturing process of an EPROM according to the present invention.

FIG. 3 is a diagram showing a manufacturing process of an EPROM according to the present invention.

FIG. 4 is a diagram showing a method of manufacturing a conventional EPROM.

FIG. 5 is a diagram showing a conventional EPROM manufacturing method.

[Explanation of symbols]

 4 ... Polysilicon layer 6 ... Polycide layer 17 ... Interlayer insulating film 24 ... Silicon oxide film 51, 52 ... Photoresist 31.・ ・ ・ Photoresist M1 ・ ・ ・ Memory cell area M2 ・ ・ ・ ・ ・ Peripheral transistor area

Claims (1)

[Claims] 1. A step of forming a first layer on a first substrate region of a semiconductor substrate, a second layer being formed on the first substrate region and a second substrate region which is a semiconductor substrate region other than the first substrate region. Forming a third layer composed of a material other than a photoresist on the second layer, partially covering the third layer with a photoresist, and
Selectively removing the photoresist layer, removing the photoresist and covering the second substrate region with the photoresist, selecting the first layer using the selectively etched third layer as a mask. The method of manufacturing a semiconductor device, comprising: a step of selectively etching the third layer, wherein the third layer has a different layer thickness or material from that of the first layer. The method for manufacturing a semiconductor device is characterized in that it is also configured to remain.