JPH077438A - Serial-parallel conversion circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a serial-parallel conversion circuit that can retain the previous result without detecting an erroneous conversion result when detection of noise is detected. [Structure] A shift register 200 shifts a start signal, a register 201 enabled by a parallel output signal of the shift register 200 latches data to be serial-parallel converted, and a decoder 207 outputs a parallel output pulse from the shift register 200. A register 2 that detects when the data load signal is correctly enabled and is enabled by the detection output of the decoder 207
The data including the output of the register 201 is latched by 02 and converted into parallel data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved serial-parallel conversion circuit used in a digital signal processing circuit or the like for converting serially input data into parallel and outputting it.

[0002]

2. Description of the Related Art A conventional serial-parallel conversion circuit is constructed as shown in FIG. 3, in which FF1 to FF4 are D flip-flops which form a shift register 100 for sequentially sending serial data. D flip-flop FF
The serial data signal is input to the D input of 1, and the clock is input to the T input in the positive phase. The D input of the D flip-flop FF2 is connected to the D flip-flop FF1.
Q output of is connected. Similarly, the Q outputs of the D flip-flops FF2 and FF3 are connected to the D inputs of the D flip-flops FF3 and FF4, respectively.
Like the D flip-flop FF1, the positive-phase clock is input to the T inputs of the D flip-flops FF2, FF3, and FF4.

Further, FF8 to FF11 are D flip-flops which constitute a register 101 for latching the result of parallel conversion of serial data by the shift register 100. D flip-flops FF8, FF9,
The D inputs of the FF10 and FF11 are respectively provided with the D flip-flops FF4 and FF3 which constitute the shift register 100.
, FF2, FF1 Q outputs are connected. Also,
D flip-flop FF forming this register 101
Output 0, output 1, output 2 and output 3 are connected to the Q outputs of 8, FF9, FF10 and FF11, respectively.
T of flip-flops FF8, FF9, FF10, FF11
A data load signal for loading data to be output in parallel is input to the input in reverse phase.

FIGS. 4 and 5 show timing charts of this conventional example. In FIG. 4, n1 is noise superimposed on the clock, and in FIG. 5, n2 is noise superimposed on the data load signal.

Next, the operation of the conventional circuit in the case of noise superimposed on the clock will be described with reference to FIGS. 3 and 4. First, when serial data is input to the shift register 100, the serial data D0 and D1 are synchronized with the clock.
, D2, D3 are sequentially sent from the D flip-flop FF1 toward the D flip-flop FF4. Next, as a result of the data being forwarded each time one pulse of the clock is input in this way, the data D0 is transferred to the D flip-flop FF.
4, the data D1 is stored in the D flip-flop FF3, the data D2 is stored in the D flip-flop FF2, and the data D3 is stored in D.
It is latched by the flip-flop FF1.

The D flip-flop FF1,
D flip-flops FF11, FF10, FF9 forming a register 101 from the Q outputs of FF2, FF3, FF4,
Wirings for transferring data to the D input of FF8 are provided respectively, and as a result of the data sequentially fed to the D flip-flops FF1, FF2, FF3, and FF4 constituting the shift register 100 and latched in these wirings, the shift The parallel-converted data is output from the register 100 to the register 101.

Thereafter, the / data load signal is enabled at the timing shown by the broken line on the left side of FIG. 4 in synchronization with the falling edge of the clock signal corresponding to the data D3, and the parallel conversion is performed by the shift register 100. Data D0 to D3 latched in the flip-flops FF8 to FF11 are output from output terminals 0 to 3.

Now, consider the operation when noise n1 is mixed in the clock signal for driving the shift register 100. In the case of this conventional example, since serial data is sequentially sent using only the clock, if the noise exceeds the logic level of the circuit, that is, the level recognized as the high voltage, the noise is also regarded as the clock and operates. Will end up.
In other words, a rising edge of noise causes a malfunction of loading data into the register.

As a result, the flip-flop FF1 inputs the input data D0, D1, since the noise n1 is regarded as a clock signal and operates, although what should originally be operated when four clock signals are input. For D2 and D3, this is latched at the timing of the regular clock signal, but for noise n1 generated between the clocks corresponding to the input data D1 and D2, this is the same as the regular clock signal. To operate this noise n1
Indefinite data Dx is latched during the transition period from the data D1 to the data D2 in synchronization with the rising edge of the data. Thereafter, the serial data D0, D1, Dx, D2, D3 are flip-flop FF in synchronization with the regular clock signal.
2 and FF3 and FF4 are sequentially fed to the shift register 10
From 0, parallel-converted data is output to the register 101.

Then, by enabling the / data load signal at the timing shown by the broken line on the right side in FIG. 4 synchronized with the falling edge of the clock signal corresponding to the data D3, the shift register 100 performs parallel conversion and D conversion is performed. The data D1, Dx, D2 and D3 latched in the flip-flops FF8 to FF11 are output from the output terminals 0 to 3.

Next, the operation of the conventional circuit when noise is superimposed on the data load signal will be described with reference to FIGS. 3 and 5. First, the input data D0, D are synchronized with the clock signal.
1, D2, D3 are flip-flops FF1, FF2, F
It is sequentially fed to F3 and FF4 and latched. At this time, the register 101 operates by regarding the noise n2 generated almost at the same time as the clock corresponding to the input data D1 as a data load signal, so that the noise n2 falls. Synchronously flip-flops FF1, FF2, FF3, FF
Latch the data output by 4. At this time, the data D1 and D0 corresponding to the clock of the current cycle are latched in the flip-flops FF1 and FF2, but the current input data is not forwarded to the flip-flops FF3 and FF4, and the previous The data sent sequentially in the cycle is still latched. Therefore, if noise is mixed in the data load signal, the data will be loaded during the serial-parallel conversion.
Rewrite the correct conversion data.

[0012]

The conventional serial-parallel conversion circuit is configured as described above, and outputs an incorrect conversion result when the clock signal and the data load signal contain noise or rewrites the correct conversion result. There was a problem that it would end up.

The present invention has been made to solve the above-mentioned problems, and even when noise is introduced into the clock signal, the start signal, and the data load signal,
An object is to obtain a serial-parallel conversion circuit that can hold the previous conversion result.

[0014]

A serial-parallel conversion circuit according to the present invention includes a shift register for shifting a start signal indicating the beginning of serial data of each cycle to be serial-parallel converted in synchronization with a clock, and this shift register. For enabling the output signal of the storage means included in the first register to latch the data included in each cycle to be serial-parallel converted in synchronization with the clock, and for performing the serial-parallel conversion output from the shift register. And a decoder that detects when the pulse is correct and the data load signal is in the load enable state, and the data that constitutes the serial data including the output of the first register that is enabled by the detection output of the decoder is latched. And a second register that converts and outputs parallel data is output. When you are in, which is constituted so as not to output the conversion result.

[0015]

In the present invention, with the above-mentioned configuration, the pulse used for serial-parallel conversion is correct, and
The parallel conversion result is output only when the input data load signal is in the load enable state, and the previous conversion result is held when other noise is mixed.

[0016]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a serial-parallel conversion circuit according to an embodiment of the present invention. In the figure, FF21 to FF24 are D flip-flops that form a shift register 200 that creates a pulse for serial-parallel conversion.
A start signal indicating the beginning of serial data of each cycle to be serial-parallel converted is input to the D input of F21, and a clock is input in the positive phase to the T input. Further, the D input of the D flip-flop FF22 is connected to the D flip-flop FF.
21 Q outputs are connected. Similarly, the D inputs of the D flip-flops FF23 and FF24 are connected to the Q outputs of the D flip-flops FF22 and FF23, and the T inputs of the D flip-flops FF22, FF23, and FF24 are in phase with the D flip-flop FF21. The clock of is input.

FF25 to FF27 are the shift register 2
Is a D flip-flop that forms a register 201 for sequentially holding serial data to be serial-parallel converted using the pulse created by 00. This register 20
D flip-flops FF25, FF26, FF that make up 1
Serial data is input to the D input of 27, and the T input of the D flip-flops FF25, FF26, and FF27 is the D flip-flops FF21, FF22, and F.
A clock having the same phase as that input to the T inputs of F23 and FF24 is input. Also, this D flip-flop FF
The Q outputs of the D flip-flops FF23, FF22, and FF21 are input in reverse phase to the E inputs of 25, FF26, and FF27, respectively.

Further, FF28 to FF31 are D flip-flops which constitute a register 202 for latching the result of parallel conversion. This D flip-flop FF3
0, FF29, and FF28 have D flip-flops F at their D inputs.
The Q outputs of F25, FF26, and FF27 are connected to each other, and the serial data signal is input to the D input of the D flip-flop FF31. Clocks of the same phase as those input to the T inputs of the D flip-flops FF21, FF22, FF23 and FF24 are input to the T inputs of the D flip-flops FF28 to FF31. Also, this D
The output of the decoder 207 is connected to the E inputs of the flip-flops FF28 to FF31.

Reference numeral 207 is a register 2 in which serial data is sequentially input only when the pulse for serial-parallel conversion made using the shift register 200 is correct and the input data load signal is in the load enable state.
01 is a decoder for instructing the register 202 to latch the output of 01, and this decoder 207 is an inverter 1
It is composed of a 3- and 5-input AND gate 12.

In this decoder 207, 13 is an inverter for inverting the output of the D flip-flop FF23, 1
Reference numeral 2 is an AND gate to which the outputs of the D flip-flops FF21, FF22, FF23 and the inverter 13 and the output of the inverter 11 are input. Reference numeral 11 is an inverter that inverts a data load signal indicating that data to be output in parallel is loaded. 2 is a timing chart showing the operation of the serial-parallel conversion circuit according to the embodiment of the present invention.

Next, the operation will be described with reference to FIGS. First, when a start signal generated once in each cycle is input to the shift register 200, the start signal is forwarded in synchronization with the clock. As a result, first, when the output of the D flip-flop FF21 becomes Low, the D flip-flop FF27 is enabled,
The data D0 is latched in the D flip-flop FF27 at the rising edge of the clock. Similarly, when the output of the D flip-flop FF22 becomes Low, the D flip-flop FF26 is enabled and the data D1 is latched by the D flip-flop FF26. When the output of the D flip-flop FF23 becomes Low, the D flip-flop FF25 is enabled and the data D2 is latched by the DD flip-flop FF25.

Next, when the data load signal is enabled (Low) when the data D3 is input, the inverter 1
The output of 1 becomes High, the outputs of D flip-flops FF21, FF22, and FF23 are High, and the output of FF24 is Low, and the output of the inverter 13 to which the output of FF24 is input becomes High. Therefore, the output of the AND gate 12 of the decoder 207 becomes High, and the D flip-flops FF28, FF29, FF30, FF31 are enabled. Therefore, the output data D3 is latched and output by the D flip-flop FF31. At the same time, the outputs of the D flip-flops FF25 to FF27 are also latched by the D flip-flops FF28 to FF30 and output to the outside.

Therefore, the serial data is converted into parallel data. At this time, the decoder 207 enables the D flip-flops FF28 to FF31 to latch the data only when the pulse for serial-parallel conversion is correct. And when the pulse is incorrect,
The D flip-flops FF28 to FF31 are set in the disable state to hold the previous data.

Now, assuming that noise n2 is mixed in the data load signal, the output of the inverter 11 becomes High due to this noise n2. However, even if the noise n2 is mixed in, the outputs of the D flip-flops FF21, FF22, FF23 and Any one of the outputs of the inverter 13 is always Low. Therefore, even if noise n2 is mixed in the data load signal, the output of the AND gate 12 of the decoder 207 is
It never becomes High, and the outputs of the D flip-flops FF28, FF29, FF30, FF31 forming the register 202 retain the previous data.

Next, assuming that the noise n1 is mixed in the clock signal, the output of the D flip-flop FF23 is synchronized with the noise n1 unlike the original clock, unlike when the outputs of the D flip-flops FF21 to FF24 are correct. Rise at different timings, and this D flip-flop F
The D flip-flop FF25 of the register 201 latches the indefinite data DX in synchronization with the output of F23. However, even if the noise n1 is mixed in any of the clocks corresponding to the data D4 to D6, the D flip-flops FF21 and FF2.
The output of either one of 2 and FF23 is always Low. Therefore, even if noise n1 is mixed in the clock signal, the output of the AND gate 12 of the decoder 207 becomes disable (Low), and the output of the D flip-flops FF28, FF29, FF30, FF31 forming the register 202 is the same as the previous data. Retained.

If noise n3 is mixed in the start signal, one of the outputs of the D flip-flops FF21 to FF23 is always Low. Therefore, even if noise n3 is mixed in the start signal, the output of the AND gate 12 of the decoder 207 becomes disable (Low), and the output of the D flip-flops FF28, FF29, FF30, FF31 forming the register 202 is the same as the previous data. Retained.

As described above, in the above embodiment, the start signal input every one cycle of the serial data signal is sequentially fed by the shift register in synchronization with the clock, and is enabled in synchronization with the forwarded start signal. Each data other than the final data in one cycle is sequentially latched by the register, and only the final stage of the shift register is low by the decoder, and the outputs of all other stages are high.
Also, after confirming that the data load signal is low, the last data in one cycle of the serial data signal and the data other than the last data in one cycle latched by the above register are latched. Even if noise is superimposed on the clock signal, the start signal, and the data load signal, it is possible to correctly perform the serial-parallel conversion operation without causing a malfunction due to the noise.

In the above embodiment, the 4-bit serial-parallel conversion circuit has been described, but the present invention can be applied to multi-bits of 2 to 3 bits or more.
2) If it is a bit, then the shift register 200
Is set to n bits, the register 201 is set to n-1 bits, and the register 202 is set to n bits, and the same effect as that of the above embodiment is obtained.

[0029]

As described above, according to the serial-parallel conversion circuit of the present invention, the shift register for shifting the start signal indicating the beginning of the serial data of each cycle to be serial-parallel converted in synchronization with the clock, A first register that is enabled by an output signal of a storage unit included in the shift register and latches data included in each cycle to be serial-parallel converted in synchronization with the clock, and a serial-parallel output from the shift register A decoder that detects when the pulse for conversion is correct and the data load signal is in the load enable state, and the detection output of this decoder enables the serial data including the output of the first register. A second register that latches data, converts it to parallel data, and outputs it is provided. Since the conversion result is not output when it is incorrect, it is possible to detect the mixing of noise that may cause a malfunction.When the noise is mixed, the previous data is retained and the incorrect conversion result is not output. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a diagram showing a serial-parallel conversion circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing according to an embodiment of the present invention.

FIG. 3 is a diagram showing a conventional serial-parallel conversion circuit.

FIG. 4 is a diagram showing operation timing of a conventional example.

FIG. 5 is a diagram showing operation timing of a conventional example.

[Explanation of symbols]

 FF21 to FF31 D flip-flop 11 inverter 12 AND gate 13 inverter 200 shift register 201 register 202 register 207 decoder

Claims (1)

[Claims] 1. A shift register for shifting a start signal indicating the beginning of serial data of each cycle to be serial-parallel converted in synchronization with a clock, and an output signal of a storage means included in the shift register to enable the serial signal. A first register that latches serial data included in each cycle to be parallel-converted in synchronization with the clock, a pulse output from the shift register, and a data load signal for loading data to be output in parallel. A decoder for outputting a load enable signal based on the load enable signal; and a second register which is enabled by the load enable signal and which latches the output of the first register and the serial data and converts the serial data into parallel data for output. Serial-parallel conversion circuit characterized by.