JPH076596A - Memory circuit - Google Patents

Abstract

PURPOSE:To provide a memory circuit with simple and small-sized constitution circuit and less power consumption. CONSTITUTION:In a voltage-signal conversion part 10, an input voltage Vi is impressed to respective gates of an nMOS 11 and a pMOS 12. By the voltage- signal conversion part 10, the voltage Vp according to the input voltage Vi is outputted from an output end 14 between the nMOS 11 and the pMOS 12. The output voltage Vp is impressed to a voltage signal hold part 30 through a switch part 20. By the voltage signal hold part 30, the voltage Vo according to the output voltage Vq of the switch part 20 is outputted from the output end 34 between the nMODS 31 and the pMOS 32. When the switch part 20 is turned off, the voltage Vq is held to a constant value between the switch part 20 and the voltage signal hold part 30, and by the voltage signal hold part 30, the constant voltage Vo determined by the voltage Vq is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit for holding analog data, and for example, in a neural computer or the like, a memory for temporarily holding the analog data on the way of transferring the analog data. Regarding the circuit.

[0002]

2. Description of the Related Art Digital technology in computer science has made remarkable progress with the progress of fine processing technology, but the amount of capital investment is increasing at an accelerating rate, and analog technology is currently drawing attention. However, the current memory circuit holds two states of high level and low level, which has been an obstacle to analog type computer technology.

[0003]

However, according to the structure in which the data is stored in the memory as a digital value in this manner, the A / D converter is provided in addition to the memory, which causes a problem that the circuit structure becomes large. Yes, also DR
The configuration using the AM has a problem that a large amount of power is consumed to hold data in the memory.

The present invention is intended to solve such problems, and an object of the present invention is to provide a memory circuit having a simple and compact circuit structure and low power consumption.

[0005]

According to the memory circuit of the present invention, a first output voltage corresponding to an input voltage applied to each gate of an nMOS and a pMOS is output from an output provided between the nMOS and the pMOS. A voltage corresponding to the first output voltage is applied to the first voltage signal output means for outputting from the end and each gate of the nMOS and pMOS, and the second output voltage corresponding to the applied voltage is applied to the nMOS and pMOS. Second voltage signal output means for outputting from an output terminal provided between the first and second voltage signal output means, and switch means for controlling an electrical connection state between the first and second voltage signal output means. The output voltage is characterized in that it is held at a constant value according to the value of the applied voltage when the switch means is turned off.

[0006]

The present invention will be described below with reference to illustrated embodiments. FIG. 1 shows a memory circuit according to a first embodiment of the present invention.

The voltage signal converter 10 has an nMOS 11 and a pMOS 12, and the source of the nMOS 11 and the pMOS
The drain of 12 is connected. A drain voltage Vd is applied to the drain of the nMOS 11 and the pMOS 12
A source voltage Vs is applied to the source of the. nMO
An input voltage Vi is applied to the gates of S11 and pMOS12. That is, the voltage signal converter 1
0 constitutes a source follower, and nMOS 11 and pMOS
An output voltage Vp corresponding to the input voltage Vi is output from the output terminal 14 provided between the output terminals 12. The output voltage Vp is
It has a magnitude obtained by adding an offset amount determined by the structure of the voltage signal converter 10 to the input voltage Vi.

The output terminal 14 of the voltage signal conversion unit 10 is connected to the voltage signal holding unit 30 via the switch unit 20. The voltage signal holding unit 30 includes an nMOS 31 and a pMO.
It has S32, and the source of the nMOS 31 and the drain of the pMOS 32 are connected. Similar to the voltage signal converter 10, the drain voltage Vd is applied to the drain of the nMOS 31, and the source voltage Vs is applied to the source of the pMOS 32. The output voltage Vq of the switch unit 20 is applied to the gates of the nMOS 31 and the pMOS 32, respectively. The output voltage Vq of the switch unit 20 has a value obtained by subtracting the voltage drop due to the switch unit 20 from the output voltage Vp of the voltage signal conversion unit 10.

As described above, the voltage signal holding unit 30 also constitutes a source follower like the voltage signal conversion unit 10, and a voltage having a magnitude obtained by adding an offset amount determined by the structure of the voltage signal holding unit 30 to the input voltage Vq. Vo for nMOS
It is output from the output terminal 34 between 31 and the pMOS 32.

The switch unit 20 is composed of an nMOS provided between the voltage signal conversion unit 10 and the voltage signal holding unit 30, and controls the electrical connection state between them. This nM
A control voltage is applied to the gate of the OS by the control circuit 21. That is, the switch unit 20 maintains the ON state when a control voltage having a predetermined positive value is applied, and otherwise turns OFF.

The operation of this embodiment will be described. First, it is assumed that the control circuit 21 outputs a control voltage having a predetermined positive value, so that the switch unit 20 maintains the ON state. In this state, the output voltage Vp of the voltage signal conversion unit 10 changes according to the input voltage Vi, and the voltage V applied to the gates of the MOSs 31 and 32 of the voltage signal holding unit 30.
q also changes according to the input voltage Vi. Here, when the input voltage Vi reaches a predetermined value, the switch unit 20 is turned off by the action of the control circuit 21. As a result, the output voltage Vq of the switch unit 20 is held at a constant value according to the magnitude of the capacitance of the gates of the MOSs 31 and 32. Therefore, the output voltage Vo of the voltage signal holding unit 30 is held when the switch unit 20 is turned off. Is held at a constant voltage value determined by the input voltage Vi of the.

As described above, according to this embodiment, the voltage Vo having a constant value is output while the switch section 20 is off. That is, this embodiment does not require a RAM for holding a fixed value or a circuit for D / A converting the data stored in this RAM. Therefore, the circuit configuration is simple and compact, and the power consumption for holding data is small.

FIG. 2 shows a memory circuit according to the second embodiment of the present invention. In this embodiment, a capacitance 40 is connected between the switch unit 20 and the voltage signal holding unit 30. As a result, the charge holding capacity on the gate side of the voltage signal holding unit 30 increases, and the voltage Vq applied to the gate when the switch unit 20 is in the OFF state is the first
It is held at a constant value for a longer time than in the example. That is, according to the second embodiment, in addition to the same effect as the first embodiment, it is possible to obtain the effect that the time for holding the output voltage Vo of the voltage signal holding unit 30 at a constant value can be lengthened.

In the first and second embodiments, the switch section 20 is composed of the nMOS, but instead of this,
The voltage signal converter 10 and the voltage signal holder 3 are formed by pMOS.
It may be configured to turn on and off between 0s.

FIG. 3 shows a third embodiment of the present invention. This embodiment differs from the first and second embodiments in that the voltage signal converter 10 is provided with a switch 20. Further, the switch unit 20 of the third embodiment has a pMOS2
2 and nMOS 23, and the source of pMOS 22 is connected to the drain of nMOS 23. The drain of the pMOS 22 is connected to the source of the nMOS 11 by n
The source of the MOS 23 is connected to the drain of the pMOS 11. The gate of the pMOS 22 is connected to the control circuit 21 via the inverter 24, and the gate of the nMOS 23 is directly connected to the control circuit 21. The output terminal 14 is p
The voltage Vq provided between the MOS 22 and the nMOS 23 and output from the output terminal 14 is applied to the gates of the nMOS 31 and the pMOS 32 of the voltage signal holding unit 30.

In the switch section 20, the pMOS 22 and the nMOS 23 are turned on / off at the same time. That is, when the two MOSs 22 and 23 are turned off from the on state by the action of the control circuit 21, the voltage Vq at the time of switching to the off state is held at a constant value thereafter, and the MOSs 31 and 32 of the voltage signal holding unit 30 are held. Applied to the gate.

According to the third embodiment, since the drain current does not occur in the voltage signal conversion unit 10 while the switch unit 20 is off, power is not substantially consumed. Therefore, power saving can be achieved as compared with the first and second embodiments.

FIG. 4 shows a fourth embodiment of the present invention.
This embodiment is different from the third embodiment in that the switch unit 20 is composed of two nMOSs 25 and 26, and the other configurations are the same as those in the third embodiment. In the third embodiment, since the pMOS 22 and the nMOS 23 of the switch unit 20 are provided between the two MOSs 11 and 12 of the voltage signal conversion unit 10, the output voltage Vq is not only offset by the MOSs 11 and 12, but also the MOS 22 and It is also affected by the offset of 23. On the other hand, according to the fourth embodiment, since the two MOSs 25 and 26 are both nMOS, an offset due to them is not generated. The same effect can be obtained even if these MOSs 25 and 26 are both pMOSs.

FIG. 5 shows a fifth embodiment of the present invention.
In the first to fourth embodiments, the output voltage of the voltage signal conversion unit 10 and the voltage signal holding unit 30 has an offset added to the input voltage. The fifth embodiment has a configuration in which this offset is removed and the output voltage Vo is controlled to be substantially equal to the input voltage Vi, as described below.

In the structure of the fifth embodiment, only the part different from that of the fourth embodiment will be schematically described. The offset voltage Vf is applied to the voltage signal converter 10 and the voltage signal holder 30.
Is applied, and the switch section 50 is provided in the voltage signal holding section 30.

The switch section 50 has the same structure as the switch section 20 of the fourth embodiment, and has two nMOSs 5.
It is composed of 5, 56. The gates of the nMOSs 55 and 56 are connected to the control circuit 29, and are turned on and off at the same time by the action of the control circuit 29. Voltage signal holding unit 3
The output terminal 34 of 0 is provided between the nMOSs 55 and 56.

The input voltage Vi is applied to the first input terminal 16 of the voltage signal converter 10 via the capacitance 41, and the second input terminal 17 of the voltage signal converter 10 is offset via the capacitance 42. The voltage Vf is applied. That is, a voltage different from that of the fourth embodiment by the offset voltage Vf is applied to each gate of the nMOS 11 and the pMOS 12. Therefore, by controlling the offset voltage Vf, the magnitude of the output voltage Vq of the voltage signal conversion unit 10 when the switch unit 20 is in the ON state can be made equal to the input voltage Vi.

The first input terminal 18 of the voltage signal holding section 30
Is connected to the output terminal 14 of the voltage signal conversion unit 30 via the capacitance 43, and is connected to the second end of the voltage signal holding unit 30.
The offset voltage Vf is applied to the input end 19 of the capacitor via the capacitance 44. That is, a voltage different from that of the fourth embodiment by the offset voltage Vf is applied to the gates of the nMOS 31 and the pMOS 32. Therefore, similar to the voltage signal conversion unit 10, by controlling the offset voltage Vf, the switch unit 5
The magnitude of the output voltage Vo of the voltage signal holding unit 10 when 0 is in the ON state can be made equal to the input voltage Vq. In the IC, the voltage signal converter 1 is generally used.
0 and the voltage signal holding unit 30 are formed close to each other, and the manufacturing conditions are similar to each other, so that the offset voltage also has a close value. Therefore, as shown in FIG. 5, a common voltage can be used as Vf.

As described above, according to the present embodiment, by setting the offset voltage Vf to an appropriate value, the offset between the input / output voltages of the voltage signal conversion unit 10 and the voltage signal holding unit 30 is removed, and the output voltage Vo is increased. Can be substantially equal to the input voltage Vi. The offset voltage V
f can take either a positive or negative value as required.

On the other hand, the switch section 50 is in an off state when the memory circuit does not output analog data and is in an off state, and is switched to an on state immediately before the start of output. By keeping the switch unit 50 normally off in this way,
Power consumption in the voltage signal holding unit 30 can be suppressed.

In each of the above embodiments, the pMOS 12 of the voltage signal converter 10 and the pMOS of the voltage signal holder 30 are used.
Although the source voltage Vs is applied to 32, the sources of these MOSs 32 may be grounded instead.

[0027]

As described above, according to the present invention, it is possible to obtain a memory circuit having a simple and compact circuit structure and low power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing a memory circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a memory circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a memory circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a memory circuit according to a fourth exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a memory circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

 10 voltage signal conversion unit 20 switch unit 30 voltage signal holding unit 40 capacitance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Osawa 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. (72) Inventor Akira Urushiba 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Stock Company Takayamauchi

Claims (5)

[Claims] 1. A first output voltage according to an input voltage applied to each gate of an nMOS and a pMOS,
First voltage signal output means for outputting from an output terminal provided between the MOS and pMOS, and nMOS and pMO
A voltage corresponding to the first output voltage is applied to each gate of S, and a second output voltage corresponding to the applied voltage is output from an output terminal provided between the nMOS and pMOS. It comprises a voltage signal output means and a switch means for controlling an electrical connection state between the first and second voltage signal output means, wherein the second output voltage is the voltage when the switch means is turned off. A memory circuit characterized by being held at a constant value according to the value of an applied voltage. 2. The memory circuit according to claim 1, wherein a capacitance is connected between the second voltage signal output means and the switch means. 3. The switch means is a MOS provided between the output end of the first voltage signal output means and the second voltage signal output means.
The memory circuit according to. 4. The switch means is two MOSs provided between an nMOS and a pMOS of the first voltage signal output means, and the output end is provided between the two MOSs. The memory circuit according to claim 1. 5. The memory circuit according to claim 4, wherein both of the two MOSs are pMOSs or nMOSs.