JPH0761141B2 - Video memory - Google Patents

Description

The present invention relates to an image dedicated memory suitable for performing image signal processing.

[Conventional technology]

In digital video equipment, a line memory (a line indicates one horizontal scanning line) is one of important devices used in an image signal processing circuit such as a comb filter, a vertical spatial filter, or an interpolator. . As an example of an image signal processing circuit using a line memory, the 1979 Journal of the Television Society of Japan, Vol. 33, No. 4, PP271
~ 276 There is a two-dimensional filter for the Y / C separation circuit in digital television, which is discussed in the literature entitled "Color Television Signal Synthesis and Separation". As discussed in this document, as a two-dimensional filter for Y / C separation, the current video signal and 1H (H is 1
The horizontal scanning period is shown. ) The characteristics of the 2H type that performs calculations using the current video signal and the video signals 1H and 2H before it are better than the 1H type that performs calculations using the previous video signal .

As an IC memory used as a line memory for image signal processing, for example, there is CXK5808P sold by Sony. This memory has a 1K × 8 bit structure, and a 10-bit address is externally given. If an NTSC television signal is sampled at a frequency of 4 · f _SC (f _SC is the frequency of the color subcarrier), the number of samples in 1H is 910, so one memory IC is quantized to 8 bits. It has a capacity of 1H for the generated video signal. Therefore, it is possible to obtain a 1H delay signal and a 2H delay signal with a circuit configuration using two memories and an address counter that counts 1H (910 dots).

[Problems to be solved by the invention]

Using the above conventional IC memory, for example, in order to obtain a 1H delay signal and a 2H delay signal for the current video signal, two
IC memory, for example to generate additional addresses 10
Since a bit address counter is required, the circuit configuration becomes complicated and the scale of the memory peripheral circuit increases.

An object of the present invention is to provide a video memory which can obtain, for example, 1H and 2H delayed signals without increasing the number of pins of the IC memory by using one IC memory and a simple peripheral circuit.

[Means for solving problems]

To achieve the above object, in the video memory of the present invention, the capacity of the memory cell array is set to at least 2H and an address counter is built therein. The write address counter of this address counter is a clock having the same frequency as the sampling frequency of the input data, for example, a counter for counting the number of samples in 2H, and the read address counter is a clock having a frequency twice that of the write address counter. (For example, the number of samples in 2H) x 2 dots
Furthermore, as one bit in the memory address signal,
In the write operation, the most significant bit signal of the write address counter output is connected, and in the read operation, the least significant bit signal of the read address counter output is connected.

[Action]

In the above means, the most significant bit of the write address counter repeats the state of 0, 1 every 1H. On the contrary,
The least significant bit of the read address is 0, for each clock input whose frequency is double the clock input of the write address counter.
Repeat the state of 1. Therefore, by this, two output signals having different delay times (for example, a delay signal of 1H and a delay signal of 2H) are input to the input signal from the memory cell array.
It is possible to alternately read and output in clock units.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. First
In the figure, 100 is an image memory according to the present invention, 101 is a video input terminal, 102 is a video output terminal, 103 is a clock signal CLK input terminal, 104 is a reset signal RES input terminal, 105 is a power supply terminal, 106 is a ground terminal, and 107 is A memory cell array, 108 is a write address decoder, 109 is a read address decoder, 110, 112, 114 and 119 are binary counters, and 111 and 113 are 9
Decimal counter, 115 is switching circuit, 116 is delay circuit, 117, 118
Is a latch circuit. FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG.

In this embodiment, a case will be described in which an NTSC video signal is sampled at a frequency of 4 · f _SC, for example. in this case,
The number of samples in one horizontal scanning line is 910.

The operation of this embodiment will be described below. The memory cell array 107 has a capacity of 2H. Each memory cell has a data line for writing and a data line for reading, for example, as shown in FIG. 7, and data writing and reading can be performed independently. Further, the counter and the latch circuit used in this embodiment operate at the falling edge of the clock signal. A clock having a frequency of 8 · f _SC (hereinafter referred to as 8f _SC CLK) is input from the clock signal input terminal 103. This signal 8f _SC CLK is shown at 2a in FIG. By guiding this signal to the binary counters 114 and 119 and dividing the frequency, 4
· F _SC made the frequency of the clock (hereinafter referred to as the 4f _SC CLK.)
To get Output signal 2c of counter 119 and counter 114
2h and 2h in FIG. 2, respectively.
Counters 112, 113, 114 are synchronous counters and have terminals 104
It is reset by the reset signal RES that is input. Therefore, the phase of the 4f _SC CLK signal 2h with respect to the 8f _SC CLK signal is determined by the reset signal RES. This reset signal RES is shown as 2g in FIG. This reset signal R
The read address and write address can be initialized by externally applying ES. The counters 110, 111, 119 are also synchronous counters, and are reset by a signal RES ′ obtained by delaying the reset signal RES by the delay circuit 116. The delay circuit 116 will be described later,
In this embodiment, the delay amount in the delay circuit 116 is set to 2 clocks of 8f _SC CLK. This second reset signal RES 'is shown at 2b in FIG.

Input terminal for video input signal DI at the timing shown in Fig. 2f.
Enter in 101. This input signal DI is led to the latch circuit 117 and latched by the 4f _SC CLK signal 2c, and then the memory cell array 1
Write to 07. The two counters 110 and 111 constitute a write address counter that generates a write address. The counter 111 is a 9-ary decimal ring counter that counts the 4f _SC CLK signal 2c from the output of the counter 119, and the output of this counter 111 is 10 out of 11 bits of the write address.
Lead to the write address decoder 108 as bits WA _{1 to} WA ₁₀ . Indicating those addresses WA ₁ ~WA ₁₀ of the 10 bits expressed in a decimal number to the second figure 2e. The counter 110 is a binary counter, and every time the counter 111 counts 910, that is, 1H.
Repeat 0 and 1 every time. The output of the counter 110 is led to the write address decoder 108 as the remaining 1 bit WA ₀ of the 11 bits of the write address. This write address WA ₀ is shown at 2d in FIG. The write address decoder 108 decodes the write addresses WA _{0 to} WA ₁₀ , designates each memory cell in the memory cell array 107 corresponding to the write address WA _{0 to} WA _10, and puts them in a writable state.

For the sake of explanation, the memory cell array 107 is divided into two areas A and B. When the address WA ₀ is 0, the memory cell in the area A is accessed, and when WA ₀ is 1, the memory cell in the area B is accessed. Then, the video input signal DI is the memory cell array.
Data of 1H is continuously written in the area A of 107, and the next data of 1H is continuously written in the area B of the memory cell array 107. Hereinafter, this operation is repeated every 2H cycle.

2f in FIG. 2 indicates that the video input data DI is a memory cell array.
It is shown that data is sequentially written from the 0th memory cell in the A region of 107 to the 909th memory cell, and subsequently from the 0th memory cell in the 2B region to the 909th memory cell. On the other hand, the three counters 112, 113, and 114 constitute a read address counter that generates a read address.
Counter 113 has a 4f _SC CLK signal 2 from the output of counter 114.
a ring counter 910 binary counting the h, and the WA ₁ ~WA address RA ₁ to RA ₀ of 10 bits corresponding to the ₁₀ output 10-bit read address 11 bits in the counter 113 to the read address decoder 109 Lead. Shows what the address RA ₁ to RA ₁₀ of the 10 bits expressed in a decimal number in Figure 2 2k. The counter 112 is a binary counter, and repeats 0, 1 every time the counter 113 counts 910, that is, every 1H. The output signal 2i of the counter 112 is shown at 2i in FIG.

The output signal 2h of the counter 114 and the inverted output signal 2h are guided to the switching circuit 115, and both of these signals are output by the output signal 2i of the counter 112.
It is controlled by 0 and 1 of and switched. The output of the switching circuit 115 is led to the read address decoder 109 as the read address RA ₀ corresponding to the write address WA ₀ . Switching circuit 115
In FIG. 2, the read address RA ₀ is shown as 2j, assuming that the signal 2h is selected when the signal 2i is 0 and the signal 2h is selected when the signal 2i is 1.

Thus, the output signal 2h is read addresses RA ₀ next 1H period binary counter 114 after the reset is performed by the reset signal RES, the subsequent 1H period, the inverted output signal 2h of the counter 114 is an RA ₀ Become. By switching in this way, in a certain 1H period, data is first read from the memory cells in the region A, and then the region B and the region A are alternately read, while in the next 1H period, the region B is first read. After reading the data from the memory cell, the area A and the area B are alternately read. Hereinafter, this operation is repeated in 2H cycles. Read address decoder 1 by read address RA _{0 to} RA ₁₀
Latch circuit for the signal read from the memory cell specified by 09
It is led to 18, latched by 8f _SC CLK, and then output to the video output terminal 102. This output signal DO is shown at 21 in FIG. The signal DO output in this way is 1H higher than the input signal DI.
The signals before and 2H before are alternately arranged. Here, when data is being written to the memory cell in the area A (or B) of the memory cell array 107, A
The data read from the memory cell in the area (or B) is
It is a 2H delay signal, and the data read from the memory cell in the B (or A) area is a 1H delay signal. For example data
When A ₀ is input, the output data A ₀ is a 2H delay signal and the output data B ₀ is a 1H delay output. Similarly, the data
When B ₀ is input, the output data B ₀ is a 2H delay signal and the output data A ₀ is a 1H delay output. As indicated by reference numeral 21 in FIG. 2, a 2H delay output and a 1H delay output for the input signal DI are output to the output terminal 102. In the switching circuit 115, the output 2h of the counter 114 and the inverted output 2h thereof are changed to 1H. Since the read address RA ₀ is switched every time, the output order of the 2H delay signal and the 1H delay signal is always constant. For example, in this embodiment, the 2H delay signal and the 1H delay signal are output in this order. In this embodiment, since the address counter is automatically reset after performing a predetermined count, the reset from the reset terminal 104 is performed once after the power is turned on,
Alternatively, it may be done once every 2 hours.

According to the present embodiment, 1H delay output and 2H delay output with respect to the video signal input can be obtained with a simple circuit configuration and control signal. For example, in a line comb filter or an intra-field scanning line interpolation circuit, a large circuit is provided. It is possible to reduce the scale.

In the embodiment of FIG. 1, the input / output is 1 bit,
A memory cell array 107, an input terminal 101, an output terminal 102, and n sets of latch circuits 117 and 118 may be provided in each of n sets to form an n-bit video memory that delays an n-bit video signal. At this time, the 1H delay output and the 2H delay output are output from the same output pin, so the terminals required for data input / output are
It is 2n. This also applies to the other embodiments described below.

When it is desired to take out the 1H delay output and the 2H delay output separately, the circuit configuration shown in FIG. 3 may be used. In FIG. 3, 100 is a video memory according to the present invention shown in FIG.
01 is a video signal input terminal, 302 is a reset signal input terminal, 3
03 is 8f _SC CLK input terminal, 304 is current signal output terminal, 305/306
Are output terminals for 1H delay and 2H delay signals respectively, 309 is a frequency dividing circuit, 310 and 311 are latch circuits, and 314 is an inverting circuit. In this way, the desired signal output is obtained by latching the output signal of the video memory 100 with the clock of 4f _SC having a phase difference of 180 ° obtained by dividing the 8f _SC CLK supplied to the video memory 100 by 2. It is suitable for image processing such as line comb filters and scanning line interpolation circuits. For example, the current signal from the output terminal 304 and the 2H delayed signal from the output terminal 306 are each multiplied by -1/4, and the 1H delayed signal from the output terminal 305 is
It is possible to extract the color signal component from the NTSC signal by multiplying by 1/2 and adding these.

In the embodiment of FIG. 1, the reset timing of the write address counter can be adjusted by changing the delay amount of the delay circuit 116, so that the delay amount can be finely adjusted in dot units. For example, in this embodiment, the delay amounts in the latch circuits 117 and 118 in the input / output stage are taken into consideration and the delay amounts are set to just 1H and 2H. Further, by reversing the switching timing of the signal 2h and the signal 2h in the switching circuit 115, or by making the read address RA ₀ the negation of the output of the switching circuit 115, the 1H delay signal and the 2H delay signal in the video output signal DO The output order of can be changed. In the embodiment shown in FIG. 1, as shown in the timing chart of FIG.
A video signal 2H before is obtained as an output, and a 2H delay signal is generated at the falling timing of the 4f _SC CLK signal 2c which is the clock signal of the latch circuit 117, and a 1H delay signal is generated at the rising timing of the signal 2c. Is output. This facilitates the management of the timing when a plurality of the present video memories are connected in series. This will be described with reference to the circuit configuration of FIG. FIG. 4 shows that 1H, 2H, 3H and 4H delay signal outputs are obtained by connecting two video memories according to the present invention in series. In FIG. 4, 100a and 100b are video memories according to the present invention shown in FIG. 1, 307 and 308 are 3H delay and 4H delay signal output terminals, 312 and 313, respectively.
Are the same as the latch circuit, and the same parts as in FIG. 3 are denoted by the same reference numerals. Video memory 100a and 10
The same reset signal and the same clock signal are supplied to 0b. Since 1H delay output and 2H delay output alternately appear in the output of the video memory 100a, the phase obtained by dividing 8f _SC CLK by 2 is different by 180 ° as in the case of the circuit of FIG.
By latching this output signal with the clock of 4f _SC , 1H delay output and
Get 2H delayed output. Also, the output of the video memory 100a is led to the input of the video memory 100b.
Since the 2H delay signal is always output to the output of the video memory 100a at the timing when the data is taken into 100b, that is, the timing of the falling edge of 4f _SC CLK in the video memory 100b, the data is thinned out in particular. Of course, only the 2H delayed signal is input to the video memory 100b. Therefore, the output of the video memory 100b is delayed by 3H and 4H from the current signal.
Since delayed signals appear alternately, this is also output by latching with a 4f _SC clock that is 180 ° out of phase.
3H delay output and 4H delay output are obtained at 307 and 308, respectively. This is suitable for image processing such as a line comb filter and a scanning line interpolation circuit with higher performance.

In this embodiment, the input signal is the NTSC signal sampled at 4f _SC , but the present invention is not limited to this, and generally, the capacity of the memory cell array is 2 m bits, and the counters 111 and 113 are By using an m-ary counter, it is possible to support other methods in which the number of samples in the 1H period is m. In addition, the memory cell array 107 is
Although the operation is described by dividing it into two areas, these are areas on the address and do not prescribe a specific physical arrangement of memory cells in the memory cell array 107. When the delay amount in the delay circuit 116 is an even number of clocks of the 8f _SC CLK signal, the counter 114 and the counter 115 perform the same operation, and thus can be used in common. Switching circuit 11
5, the output signal 2h of the counter 114 and the same inverted output signal
2h is switched depending on the level of the output signal 2i of the counter 112, but the same function is used for the signals 2h and 2i,
Alternatively, it can be realized by taking the exclusive OR of the signals 2h and 2i, or the negation thereof.

FIG. 5 shows another embodiment of the video memory according to the present invention. The feature of this embodiment is that the number of dots in one horizontal scanning line period can be arbitrarily designated by the cycle of a reset signal RES applied from the outside. In FIG. 5, 500 is a video memory according to the present invention, 501 is a 1H / 2H delay discrimination clock signal output terminal, 502 is a decode signal output terminal, 503 is a memory cell array, 504, 506, 507 and 509 are binary counters.
505 and 508 are 1024-base 10-bit counters, 510 is a write address decoder, 511 is a read address decoder, and 513 is A ₁
A decoding circuit, 514 is a B ₁ decoding circuit, 515 is a decoding circuit, 516 to 524 and 526 are various gate circuits, and 525 is an edge detection circuit. Here, the memory cell array 503 is 2048
It has a capacity for bits, and each memory cell uses the one shown in FIG. Also, counters 504 and 509
In, when the set signal and the reset signal are input at the same time, the set has priority.

The operation of the embodiment shown in FIG. 5 will be described with reference to the timing chart of FIG. 8f _SC CLK is input from the input terminal 103. This is shown in Figure 6a. Further, a reset pulse RES having a 1H cycle is input from the input terminal 104. This reset pulse RES is shown in FIG. 6b. The counter 507 divides the reset pulse RES by 2 and counts 2H. The output signal 6g of the counter 507 is shown in FIG. 6g. The counter 509 normally outputs 4f _SC CLK, but when the reset pulse RES is input from the input terminal 104, resetting and setting are repeated every 1H. The output of the counter 509 is led to the read address decoder 511 as 1 bit RA ₀ of the read address. This address RA ₀ is shown in FIG. 6h. The 10-bit counter 508 counts the signal 6i obtained by inverting the output signal of the counter 509 every 1H. This signal 6i is shown in FIG. 6i. The output of the 10-bit counter is led to the read address decoder 511 as the remaining 10 bits RA _{1 to} RA ₁₀ of the read address. 10-bit counter output RA ₁ to RA ₁₀ of the 10
The representation in base 6 is shown in Figure 6j. These addresses
The data read from the memory cells accessed by RA _{0 to} RA ₁₀ is latched by the latch circuit 118 and then output from the output terminal 102. This video output signal is shown in FIG. 6k. Read addresses RA _{0 to} RA ₁₀ are applied to the decoding circuits 513 and 514.
Is input to decode the address of the first memory cell in the area A and the first memory cell in the area B, and generate a pulse. These pulses are gated by the output signal of counter 507. The counter 504 is repeatedly set and reset every 1H. The output signal of the counter 504 is led to the write address decoder 510 as the write address WA ₀ .
The counter 506 divides the 8f _SC CLK by 2 to obtain a 4f _SC clock signal 6c. Counter 505 counts signal 6c 1
This is a 0-bit counter, and its output is the write address WA ₁
~ WA ₁₀ is led to the write address decoder 510. Both the counters 505 and 506 are reset to 1H once. The output signal 6c of the counter 504 is shown at (3) in FIG.
Outputs WA _{1 to} WA ₁₀ of 05 are shown in decimal notation in Fig. 6 (5). Video signal DI input from input terminal 101
Is shown in FIG. 6f. This video input signal DI is the latch circuit 11
After being latched at 7, it is written to the memory cell specified by the write address WA _{0 to} WA ₁₀ . By the above operation, the video signals 1H before and 2H before the video input signal DI are alternately output to the output terminal 102.

In the embodiment of FIG. 5, by changing the decode value in the decode circuits 516 and 517, the reset and set timings of the counters constituting the write address counter can be adjusted, so that the delay amount can be finely adjusted in dot units. Become.

Further, in the present embodiment, the length of 1H is determined by the cycle of the reset pulse RES given from the outside. Therefore, it is possible to support a system in which the number of samples for 1H is 1024 or less, and the delay amount can be set. Furthermore, by controlling so that the writing of the video signal DI is stopped until the counter 505 counts 1024 and then is reset, it is possible to support a system in which the number of 1H samples is 1024 or more. For example, the clock signal CLK that inputs the reset pulse signal RES
If it is given in 1135 clock cycles, it is possible to obtain 1H and 2H delay signals even for PAL system video signals. At this time, since the video signal of 111 dots for more than 1024 clocks is not written in the present video memory, this period may be the blanking period of the video signal.

The decoding circuit 515 decodes the read addresses RA _{0 to} RA ₁₀ and outputs it to the output terminal 502. If the decode value at this time is the number of frequently used 1H samples, for example, 910, this decode output is used as the reset signal RES and the terminals 104 and
If 502 is connected, it is not necessary to give a reset signal from the outside.

The edge detection circuit 525 detects the edge of the reset signal RES. Therefore, since the pulse width of the reset signal RES to be input may be long over several clocks, the horizontal synchronizing signal can be used as it is as the reset signal RES.

A signal 6i which is the inverted signal 6i is output to the output terminal 501. As shown in FIG. 6, a 1H delay signal is output at the falling edge of the signal 6i and a 2H delay signal is output at the falling edge of the signal 6i. Therefore, if the signal 6i or 6i is output to the outside, 1H outside
When it is desired to take out the delayed signal and the 2H delayed signal separately, the video output signal DO may be latched by the signal from the output terminal 501 or the inverted signal thereof. Therefore, the clock frequency divider circuit 309 is not necessary when the method shown in FIGS. 3 and 4 is used in this embodiment.

In the embodiment of the present invention, the memory capacity is set to 2H, and the 1H and 2H delay signals are obtained. However, the present invention is not limited to this.
4H and obtain 1H delay and 4H delay output, or
The feature is that signals with different delay amounts are output from the same terminal, such as those that obtain 2H delay and 4H delay output.

FIG. 8 shows an example of the configuration of a 2H type Y / C separation comb filter using the embodiment of the video memory according to the present invention shown in FIG. In FIG. 8, 500 is an n-bit video memory according to the present invention shown in FIG. 5, 801 to 804 are latch circuits, 805 and 807 are adders, 806 is a multiplier, 808 is a subtractor, and 809 is a video. Signal input terminal, 810 is clock input terminal,
Reference numeral 811 is a color signal output terminal, 812 is a luminance signal output terminal, and 813 is an inverting circuit. A 2H delayed signal, a 1H delayed signal, and a current signal are obtained at the outputs of the latch circuits 802, 803, and 804, respectively. Therefore, a 2H comb filter can be realized with a simple circuit configuration as shown in the figure.

〔The invention's effect〕

According to the present invention, 1H and 2H delayed signal outputs can be easily obtained for a video signal input without increasing the number of pins of the IC memory, so that a video memory suitable for various image signal processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video memory according to the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1, and FIGS. 3 and 4 are shown in FIG. FIG. 5 is a block diagram showing an application example using the video memory of the embodiment, FIG. 5 is a block diagram showing another embodiment of the video memory according to the present invention, and FIG. 6 is a description of the operation of the embodiment of FIG. FIG. 7 is a circuit diagram showing an embodiment of a memory cell used in the video memory according to the present invention, and FIG. 8 is a comb type for Y / C separation using the video memory of the embodiment shown in FIG. It is a block diagram which shows the structure of a filter. 100 …… Video memory, 107 …… Memory cell array, 108…
… Write address decoder, 109 …… Read address decoder, 110, 112, 114, 119 …… Binary counter, 111, 113 …… 91
0-counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Nakagawa, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Hisabu Tsukazaki Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa House number 292, Incorporated Household Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor, Kazuo Kondo, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, House number 292 In-house Household Appliances Laboratory, Hitachi, Ltd. (72) Inventor, Mitsumoto Matsuzo Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture House No. 292 Co., Ltd. Household Appliances Research Laboratory, Hitachi, Ltd.

Claims (1)

[Claims] 1. A storage means capable of storing n-bit video data sampled at a frequency f for at least two horizontal scanning periods, n input terminals, n output terminals, and the n input terminals. Means for writing n bits of the video signal into the storage means, means for guiding the n-bit video signal read from the storage area to the n output terminals, and a frequency f
Write address counter that counts the number of samples for at least two horizontal scanning lines by using the clock signal as a clock pulse, and a read address counter that counts the number of samples for at least two horizontal scanning lines by using a clock signal of frequency 2f as a clock pulse. An address counter, and a storage area in the storage means selected according to the polarity of the most significant bit signal of the write address counter output at the time of the write operation, the least significant bit of the read address counter at the time of the read operation. A video which is configured to be selected according to the polarity of a signal, and two video data having different delay times are alternately output to the output terminal at a frequency 2f with respect to the input video data. memory.