JPH0756518B2 - Calendar clock circuit - Google Patents
Calendar clock circuitInfo
- Publication number
- JPH0756518B2 JPH0756518B2 JP60274558A JP27455885A JPH0756518B2 JP H0756518 B2 JPH0756518 B2 JP H0756518B2 JP 60274558 A JP60274558 A JP 60274558A JP 27455885 A JP27455885 A JP 27455885A JP H0756518 B2 JPH0756518 B2 JP H0756518B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- calendar clock
- voltage
- clock circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000010365 information processing Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000010355 oscillation Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Landscapes
- Electric Clocks (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は情報処理装置における無停電型カレンダ時計回
路に関する。The present invention relates to an uninterruptible calendar clock circuit in an information processing device.
（従来の技術） 情報処理装置におけるカレンダ時計回路は無停電型回路
となつている。(Prior Art) The calendar clock circuit in the information processing apparatus is an uninterruptible circuit.
第３図は従来のこの種の無停電型カレンダ時計回路の動
作概念を示す回路図である。本図はバツテリ回路３、切
替回路14、カレンダ時計回路IC5、水晶振動子６、発振
周波数微調整用可変コンデンサ７および装置電源より構
成されている。FIG. 3 is a circuit diagram showing the operation concept of a conventional uninterruptible calendar clock circuit of this type. This diagram comprises a battery circuit 3, a switching circuit 14, a calendar clock circuit IC 5, a crystal oscillator 6, a variable capacitor 7 for fine adjustment of the oscillation frequency, and a device power supply.
装置電源がオンのときはカレンダ時計回路部５に装置電
源から電流が供給され、装置電源がオフになるとバツテ
リ回路３よりカレンダ時計回路部５に電流が供給され
る。When the device power supply is on, a current is supplied from the device power supply to the calendar clock circuit unit 5, and when the device power supply is off, a current is supplied from the battery circuit 3 to the calendar clock circuit unit 5.
第３図の切替回路14はバツテリ回路３に接続されている
状態を示している。The switching circuit 14 in FIG. 3 shows a state in which it is connected to the battery circuit 3.
カレンダ時計回路部５はシステムバス８を経由して上位
制御回路９（例えばCPU−LSI）に接続されている。上位
制御回路９はカレンダ時計回路５に対し、時刻をセツト
したり、時刻を読み出したりすることができる。The calendar clock circuit section 5 is connected to a host control circuit 9 (for example, CPU-LSI) via a system bus 8. The upper control circuit 9 can set the time to the calendar clock circuit 5 and read the time.
第４図は第３図の回路のうち、切替回路とバツテリ回路
の具体例を示す回路図である。FIG. 4 is a circuit diagram showing a specific example of the switching circuit and the battery circuit in the circuit of FIG.
切替回路14は装置電源より供給される電圧値をチエツ
ク、一定電圧以下になつたとき、バツテリ回路に切替え
る電子スイツチである。The switching circuit 14 is an electronic switch that switches to a battery circuit when the voltage value supplied from the device power supply falls below a certain voltage.
規定電圧値のチエツクは抵抗R1とR2を分圧して検出して
おり、規定電圧値が加わるとトランジスタTr1がオンす
るためトランジスタTr2もオンし、規定電圧（＋5V）が
カレンダ時計回路部５の電源端子部に加わる。電源がオ
フした場合はトランジスタTr2もオフするため切替回路1
4は規定電圧とカレンダ時計回路部５の接続を切断す
る。The check of the specified voltage value is detected by dividing the resistors R 1 and R 2 , and when the specified voltage value is applied, the transistor T r1 turns on, so the transistor T r2 also turns on, and the specified voltage (+5 V) becomes the calendar clock circuit. It is added to the power supply terminal section of the section 5. Switching circuit 1 to turn off also the transistor T r2 If the power is turned off
4 disconnects the specified voltage from the calendar clock circuit unit 5.
バツテリ回路３は抵抗R3およびダイオードD1よりなる充
電回路部、抵抗R4の放電回路部および二次電池Ｂより構
成されている。The battery circuit 3 is composed of a charging circuit section consisting of a resistor R 3 and a diode D 1 , a discharging circuit section of a resistor R 4 and a secondary battery B.
切替回路14のトランジスタTr2がオフの場合は二次電池
Ｂより抵抗R4を介してカレンダ時計回路部５に電流が供
給される。なお、装置の電源がオンの場合は二次電池Ｂ
は充電回路部を介して充電される。Transistor T r2 of the switching circuit 14 is current calendar clock circuit section 5 in the case of off via a resistor R 4 from the secondary battery B is supplied. When the power of the device is on, the secondary battery B
Is charged via the charging circuit section.
（発明が解決しようとする問題点） さて、従来回路は装置電源がオンのとき、カレンダ時計
回路５に供給される電源電圧をバス８とのインタフエー
スをとるために規定電圧（TTLインタフエースの場合、
＋5.0V）を保持せねばならないが、装置電源がオフのと
きはバツテリ消費電力を抑制するために規定電圧より低
い値（一般には約3.0V）を採つている。そのためカレン
ダ時計回路部の発振周波数が二種の電圧値に依存し若干
変化するので１カ月も経つと時間が少し狂い、時刻再設
定の必要が生じる場合がある。(Problems to be Solved by the Invention) In the conventional circuit, when the power source of the device is turned on, the power supply voltage supplied to the calendar clock circuit 5 is controlled by the specified voltage (TTL interface voltage) to interface with the bus 8. If
+ 5.0V) must be maintained, but when the device power is off, a value lower than the specified voltage (generally about 3.0V) is used to suppress battery power consumption. For this reason, the oscillation frequency of the calendar clock circuit section slightly changes depending on the two kinds of voltage values, and therefore, the time may be slightly misplaced after one month, and it may be necessary to reset the time.
本発明の目的は、電源切替えに原因する時刻の変化を極
力少なくし短期間での時刻調整を不要にするため、カレ
ンダ時計回路部を規定電圧より一定電圧降下させた電圧
で発信周波数調整をしておき、上位制御回路がアクセス
した場合、カレンダ時計回路部出力が上位制御回路によ
って正しく受け取られるように、上位制御回路と同一の
電圧すなわち規定電圧に切り換えるようにしたカレンダ
時計回路を提供することにある。An object of the present invention is to adjust the oscillation frequency with a voltage which is a constant voltage drop below the specified voltage in the calendar clock circuit section in order to minimize the time change due to the power supply switching and to eliminate the need for time adjustment in a short period. It is to be noted that a calendar clock circuit is provided that is switched to the same voltage as the upper control circuit, that is, a specified voltage, so that the output of the calendar clock circuit section can be correctly received by the upper control circuit when accessed by the upper control circuit. is there.
（問題点を解決するための手段） 本発明のカレンダ時計回路は、情報処理装置の装置電源
がON状態のとき規定電圧により内蔵バッテリが充電さ
れ、上記装置電源がOFF状態のとき上記バッテリから上
記規定電圧より低い電圧を出力する第１の電源回路と、
上記規定電圧を予め定めた電圧だけ降下させ、上記第１
の電源回路からの出力電圧とほぼ同じ電圧を出力する第
２の電源回路と、時刻情報を発生するカレンダ時計回路
部と、上記カレンダ時計回路部をアクセスして上記時刻
情報の修正あるいは読み出しを行う上位制御回路と、上
記装置電源がON状態、かつ上記上位制御回路が上記カレ
ンダ時計回路部をアクセスしていない間上記情報処理装
置からの信号に応答して上記第２の電源回路からの出力
電圧に、上記装置電源がON状態、かつ上記上位制御回路
が上記カレンダ時計回路部をアクセスしている間だけ上
記情報処理装置からの信号に応じて上記規定電圧に、上
記装置電源がOFF状態のとき上記第１の電源回路からの
出力電圧にそれぞれ切替えて上記カレンダ時計回路部に
供給する切替回路とを備えている。(Means for Solving Problems) In the calendar clock circuit of the present invention, the built-in battery is charged with a specified voltage when the device power supply of the information processing device is ON, and when the device power supply is OFF, A first power supply circuit that outputs a voltage lower than a specified voltage;
The specified voltage is decreased by a predetermined voltage, and the first
The second power supply circuit that outputs a voltage substantially the same as the output voltage from the power supply circuit, the calendar clock circuit unit that generates time information, and the calendar clock circuit unit are accessed to correct or read the time information. An output voltage from the second power supply circuit in response to a signal from the information processing device while the upper control circuit is in the ON state and the upper control circuit is not accessing the calendar clock circuit section. When the device power supply is in the ON state, and the host control circuit is accessing the calendar clock circuit section, the device is in the OFF state when the device power supply is in the specified voltage according to the signal from the information processing device. And a switching circuit for switching to the output voltage from the first power supply circuit and supplying the voltage to the calendar clock circuit unit.
第１図は本発明によるカレンダ時計回路の回路ブロツク
図である。電源回路１は装置電源がオンのとき、バツテ
リ電圧とほぼ同等の電圧を出力する。電源回路３はバツ
テリ内蔵の回路である。切替スイツチ４は上位制御回路
（CPU−LSI）９がカレンダ時計回路IC5をアクセスする
ときは直接カレンダ時計回路ICに対して装置電源の規定
電圧を供給し、アクセスしないときは電源回路１より電
源供給し、また、装置電源がオフのときは、バツテリ内
蔵の電源回路３から電源を供給するように切替え動作す
る。FIG. 1 is a circuit block diagram of a calendar clock circuit according to the present invention. The power supply circuit 1 outputs a voltage substantially equal to the battery voltage when the device power supply is on. The power supply circuit 3 is a circuit with a built-in battery. The switching switch 4 directly supplies the specified voltage of the device power supply to the calendar clock circuit IC when the upper control circuit (CPU-LSI) 9 accesses the calendar clock circuit IC5, and supplies the power from the power supply circuit 1 when it does not access. When the power source of the apparatus is off, the switching operation is performed so that the power source circuit 3 with a built-in battery supplies power.
カレンダ時計回路IC5がアクセスされる時間はシステム
の時間軸で見るとごくわずかであるので、ほとんどバツ
テリ電圧に近い値でカレンダ時計回路は稼動しており、
発振周波数微調整用コンデンサ７をバツテリ電圧の状態
で調整すればカレンダ時計回路部の精度は大幅に上昇す
る。The time when the calendar clock circuit IC5 is accessed is very short when viewed on the time axis of the system, so the calendar clock circuit is operating at a value close to the battery voltage,
If the oscillation frequency fine adjustment capacitor 7 is adjusted in the state of the battery voltage, the accuracy of the calendar clock circuit unit is significantly increased.
（実 施 例） 次に第２図を参照して本発明による実施例を説明する。(Example) Next, an example according to the present invention will be described with reference to FIG.
第１図における電源回路１はダイオード21,22の直列回
路より構成されており、ダイオードの順方向ドロツプ電
圧を利用したものである。電源回路１が動作するときは
この２つのダイオード間に約1.4Vの電位差が生じる。The power supply circuit 1 in FIG. 1 is composed of a series circuit of diodes 21 and 22, and utilizes the forward drop voltage of the diodes. When the power supply circuit 1 operates, a potential difference of about 1.4V occurs between these two diodes.
規定電圧は5.0Vであるのでカレンダ時計回路部５には約
3.6Vの電源が供給される。Since the specified voltage is 5.0V, the calendar clock circuit section 5 has about
3.6V power is supplied.
電源回路３は充電電流制限抵抗24およびダイオード25よ
りなる充電回路部と放電電流制限抵抗26と２次電池27よ
り成り立つている。カレンダ時計回路部５の発振周波数
微調整は、上記電源回路３の出力電圧の状態で周波数可
変コンデンサ７によって調整される。The power supply circuit 3 is composed of a charging circuit section including a charging current limiting resistor 24 and a diode 25, a discharging current limiting resistor 26, and a secondary battery 27. The fine adjustment of the oscillation frequency of the calendar clock circuit unit 5 is performed by the frequency variable capacitor 7 in the state of the output voltage of the power supply circuit 3.
切替回路４は検出電圧設定用抵抗32,33と抵抗33に並列
に接続され、システムのプログラム制御により与えられ
る信号10によりオンオフさせられるトランジスタ34と、
ベースが抵抗32と33との接続点に接続された電圧検出用
トランジスタ31およびトランジスタ31によりオンオフ制
御され、規定電圧（＋5.0V）をカレンダ時計回路部５に
供給するスイツチ用トランジスタ30とから構成されてい
る。The switching circuit 4 is connected in parallel to the detection voltage setting resistors 32 and 33 and the resistor 33, and is turned on / off by the signal 10 given by the program control of the system, and the transistor 34,
A switch transistor 30 whose base is ON / OFF controlled by a voltage detection transistor 31 and a transistor 31 which are connected to a connection point between the resistors 32 and 33, and which supplies a specified voltage (+5.0 V) to the calendar clock circuit unit 5. Has been done.
次に詳細な動作について説明する。Next, detailed operation will be described.
本実施例におけるシステムバス８はTTLインタフエース
であり、装置電源より＋5Vの規定電圧が供給される。The system bus 8 in this embodiment is a TTL interface and is supplied with a specified voltage of +5 V from the power source of the device.
装置電源がオンで、カレンダ時計回路５をアクセスしな
いとき、信号線10にはプログラム制御によりトランジス
タ34がオンになるレベル電圧が与えられ、トランジスタ
34がオン、トランジスタ31,30がオフとなり切替回路４
の出力は無効となる。When the device power is on and the calendar clock circuit 5 is not accessed, the signal line 10 is provided with a level voltage at which the transistor 34 is turned on by program control.
Switching circuit 4 turns on and transistors 31 and 30 turn off.
Output is invalid.
一方、このとき電源回路１のダイオード21,22は順方向
にバイアスされるので、カレンダ時計回路部５には5.0V
よりダイオード２本分の順方向電位差が差し引かれた値
の約3.6Vが供給される。バツテリ27の出力電圧を＋3.0V
にしてあるのでバツテリは放電することなく、＋5V→抵
抗24→ダイオード25経由でバツテリ27は充電される。On the other hand, at this time, since the diodes 21 and 22 of the power supply circuit 1 are forward biased, the calendar clock circuit unit 5 has 5.0V.
About 3.6V, which is the value obtained by subtracting the forward potential difference of two diodes, is supplied. Output voltage of battery 27 is + 3.0V
Therefore, the battery is not discharged, and the battery 27 is charged via + 5V → resistance 24 → diode 25.
装置電源がオンでカレンダ時計回路部５がアクセスされ
るときは信号線10が接地され、トランジスタ34がオフ、
トランジスタ31,30がオンとなる。このときトランジス
タ30のエミッタ、コレクタ電圧は小さいので（約0.2
V）、カレンダ時計回路部５にはほぼ規定電圧の5Vに近
い値が供給される。When the device power is on and the calendar clock circuit section 5 is accessed, the signal line 10 is grounded, the transistor 34 is off,
The transistors 31 and 30 are turned on. At this time, the emitter / collector voltage of the transistor 30 is small (about 0.2
V), a value close to the specified voltage of 5 V is supplied to the calendar clock circuit unit 5.
装置電源がオフになつた場合はバツテリ27より抵抗26を
経由して＋3.0Vの電圧がカレンダ時計回路部５へ供給さ
れる。When the power source of the device is turned off, the voltage of +3.0 V is supplied from the battery 27 to the calendar clock circuit unit 5 via the resistor 26.
このときダイオード25,22およびトランジスタ30はすべ
て逆バイアスとなりバツテリからの放電電流はそれらに
は流れない。信号40は電源確立信号で、オンになると電
源電圧が規定になつていることを保証する信号である。At this time, the diodes 25 and 22 and the transistor 30 are all reverse biased, and the discharge current from the battery does not flow through them. The signal 40 is a power supply establishment signal, and is a signal that guarantees that the power supply voltage is regulated when turned on.
一般には装置電源より出力される。Generally, it is output from the device power supply.
この信号がオフになれば外部信号とは何ら関係なく、カ
レンダ時計回路部５内の情報は外部より乱されることは
ない。When this signal is turned off, the information in the calendar clock circuit unit 5 is not disturbed from the outside regardless of the external signal.
（発明の効果） 以上、詳しく説明したように本発明は装置電源オンのと
きでもバツテリ電圧に近い電圧を出力する電源回路を備
え、カレンダ時計回路部をアクセスするときのみシステ
ム規定電圧に切替えるように構成してあるので、等価的
にカレンダ時計回路への供給電圧をほぼ一定にすること
ができる。したがつて時計精度の大幅な向上を期待でき
る。(Effect of the Invention) As described in detail above, the present invention is provided with a power supply circuit that outputs a voltage close to the battery voltage even when the power supply of the device is turned on, and switches to the system specified voltage only when accessing the calendar clock circuit section. Since it is configured, the supply voltage to the calendar clock circuit can be equivalently made substantially constant. Therefore, it can be expected that the clock accuracy will be greatly improved.
第１図は本発明によるカレンダ時計回路の回路ブロツク
図、第２図は本発明によるカレンダ時計回路の実施例を
示す回路図、第３図は従来のカレンダ時計回路の基本構
成ブロツク図、第４図は第３図の具体例を示す回路図で
ある。 １……電源回路、３……電源回路 4,14……切替回路 ５……カレンダ時計回路部（カレンダ時計回路IC） ６……水晶振動子 ７……周波数調整用可変コンデンサ ８……システムバス ９……上位制御回路1 is a circuit block diagram of a calendar clock circuit according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a calendar clock circuit according to the present invention, FIG. 3 is a basic configuration block diagram of a conventional calendar clock circuit, and FIG. The drawing is a circuit diagram showing a specific example of FIG. 1 ... Power supply circuit, 3 ... Power supply circuit 4,14 ... Switching circuit 5 ... Calendar clock circuit unit (Calendar clock circuit IC) 6 ... Crystal resonator 7 ... Frequency adjusting variable capacitor 8 ... System bus 9 ... Upper control circuit
Claims (1)
定電圧により内蔵バッテリが充電され、該装置電源がOF
F状態のとき該バッテリから該規定電圧より低い電圧を
出力する第１の電源回路と、 前記規定電圧を予め定めた電圧だけ降下させ、前記第１
の電源回路からの出力電圧とほぼ同じ電圧を出力する第
２の電源回路と、 時刻情報を発生するカレンダ時計回路部と、 前記カレンダ時計回路部をアクセスして前記時刻情報の
修正あるいは読み出しを行う上位制御回路と、 前記装置電源がON状態、かつ前記上位制御回路が前記カ
レンダ時計回路部をアクセスしていない間前記情報処理
装置からの信号に応答して前記第２の電源回路からの出
力電圧に、前記装置電源がON状態、かつ前記上位制御回
路が前記カレンダ時計回路部をアクセスしている間だけ
前記情報処理装置からの信号に応じて前記規定電圧に、
前記装置電源がOFF状態のとき前記第１の電源回路から
の出力電圧にそれぞれ切替えて該カレンダ時計回路部に
供給する切替回路とを備えたことを特徴とするカレンダ
時計回路。1. A built-in battery is charged by a specified voltage when the device power supply of the information processing device is in an ON state, and the device power supply is OF
A first power supply circuit that outputs a voltage lower than the specified voltage from the battery when in the F state; and the specified voltage is dropped by a predetermined voltage,
Second power supply circuit that outputs a voltage substantially the same as the output voltage from the power supply circuit, a calendar clock circuit unit that generates time information, and the calendar clock circuit unit is accessed to correct or read the time information. An upper control circuit and an output voltage from the second power supply circuit in response to a signal from the information processing device while the device power supply is in an ON state and the upper control circuit is not accessing the calendar clock circuit unit. In, the device power supply is in the ON state, and to the specified voltage according to the signal from the information processing device only while the higher-order control circuit is accessing the calendar clock circuit unit,
A calendar clock circuit, comprising: a switching circuit that switches to an output voltage from the first power supply circuit and supplies the output voltage to the calendar clock circuit unit when the device power supply is in an OFF state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60274558A JPH0756518B2 (en) | 1985-12-06 | 1985-12-06 | Calendar clock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60274558A JPH0756518B2 (en) | 1985-12-06 | 1985-12-06 | Calendar clock circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62134589A JPS62134589A (en) | 1987-06-17 |
| JPH0756518B2 true JPH0756518B2 (en) | 1995-06-14 |
Family
ID=17543396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60274558A Expired - Fee Related JPH0756518B2 (en) | 1985-12-06 | 1985-12-06 | Calendar clock circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0756518B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011133489A (en) * | 2011-03-18 | 2011-07-07 | Toshiba Home Technology Corp | Rice cooker |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5043786U (en) * | 1973-08-17 | 1975-05-02 | ||
| JPS5668814A (en) * | 1979-11-09 | 1981-06-09 | Toshiba Corp | Computer system with clock control circuit |
| JPS56155885A (en) * | 1980-05-06 | 1981-12-02 | Citizen Watch Co Ltd | Electronic timepiece |
-
1985
- 1985-12-06 JP JP60274558A patent/JPH0756518B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011133489A (en) * | 2011-03-18 | 2011-07-07 | Toshiba Home Technology Corp | Rice cooker |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62134589A (en) | 1987-06-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |