JPH0750395A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: [PROBLEMS] To provide a semiconductor memory device having a structure capable of manufacturing a semiconductor memory device having a high integration density, which includes a capacitor using a crystalline insulating film as a dielectric, at a low cost, and a manufacturing method thereof. [Structure] The surface of the insulating film formed on the portion where the lower electrode does not exist is modified by ion implantation or the like to enhance the reactivity with the crystalline thin film, and the insulating film having high crystallinity is formed on the base electrode. An insulating film having low crystallinity is formed on each of the modified surfaces. [Effect] On the portion where the base electrode does not exist, the crystallinity is lost and the dielectric constant is lowered, so that the electrical coupling between the adjacent electrodes is weakened. As a result, the dry etching of the crystalline insulating film and the process of forming another insulating material are not required, and the manufacturing cost of the highly integrated semiconductor device is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having a small and large capacity capacitor (capacity) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Among thin films having crystallinity, for example, lead titanate (PbTiO ₃ ) exhibits an insulating property and has a relative dielectric constant of about 100 and a non-linear voltage-capacitance characteristic called ferroelectricity. Therefore, it is being developed as a dielectric thin film for capacitors of semiconductor memory devices and the like.

Generally, a capacitor is a two-terminal element using two conductive films respectively formed on both surfaces of a dielectric thin film as electrodes, but in a semiconductor memory device or the like, this capacitor is placed on the same plane. A lot of them are arranged and arranged. In this case, in order to prevent interference of electric signals between adjacent capacitors and reduce the parasitic capacitance, a portion not sandwiched between two electrodes facing each other, that is, a dielectric outside these two electrodes is used. The body membrane is
In order to reduce the parasitic capacitance, it is desirable to use a dielectric material having a relatively low dielectric constant, for example, an amorphous silicon oxide film, instead of the crystalline insulating thin film.

Therefore, as shown in, for example, VLSI System Design, May 1988, pages 116 to 123, a crystalline dielectric film is patterned according to the shape of a base electrode, and the removed portion is replaced with another portion. A method has been proposed in which a dielectric material is embedded to separate crystalline dielectric films of adjacent capacitors from each other.

[0005]

However, it is difficult to solve the difficulties caused by the high integration of the semiconductor memory device by the above conventional technique.

The first reason is that it is difficult to perform fine processing of the crystalline dielectric film with high accuracy. As is well known, as the integration density increases, the processing size becomes significantly smaller, and the etching amount in the horizontal direction (side etching amount) cannot be ignored with respect to the required dimensional accuracy. Instead of the wet etching that progresses, dry etching, which has directional etching, is used.

In order to perform this dry etching,
An element capable of forming a halogen compound with high volatility must be contained in the object to be etched as a constituent element. However, among the crystalline dielectric films, particularly oxides having a perovskite structure, such as barium and lead contained in barium titanate and lead titanate, have a low vapor pressure of halides and are formed into a predetermined shape by dry etching. It is difficult to process.

The second reason is that the number of required process devices is increased and the manufacturing cost is increased. In order to realize a highly integrated semiconductor device, it is necessary to extremely clean various containers or devices used in manufacturing. Therefore, a device for handling semiconductor wafers to which heavy metals such as barium and lead are attached. Cannot be shared with other processes. Therefore, the number of devices in the process after forming the crystalline dielectric thin film is increased, and the manufacturing cost is significantly increased.

An object of the present invention is to solve the conventional problems described above, to provide a semiconductor memory device having a capacitor having a crystalline insulating film and having a high integration density, and to manufacture this semiconductor memory device easily and at low cost. It is an object of the present invention to provide a method of manufacturing a semiconductor memory device which can be manufactured.

[0010]

In order to achieve the above object, the present invention has a crystalline insulating film interposed between a lower electrode and an upper electrode, and an outer portion where the lower electrode does not exist. Of the crystalline insulating film formed on the surface-modified insulating film by extending the crystalline insulating film on the surface-degraded insulating film such as silicon dioxide. , Which lowers the crystallinity.

The modification of the surface can be carried out, for example, by implanting ions into the insulating film using the lower electrode as a mask.

[0012]

The function of the insulating film whose surface is modified is extremely high with the crystalline thin film. Therefore, if the surface of the insulating film is modified and then the crystalline insulating film is formed on the entire surface, the portion formed on the lower electrode retains high crystallinity as it is. The crystallinity of the crystalline insulating film formed on the film is remarkably lowered, and accordingly, the oil field rate is remarkably lowered to prevent the parasitic capacitance from increasing.

That is, as shown in FIG. 1, a portion of the crystalline insulating film where the lower electrode 104 does not exist, that is, an insulating film 105 whose surface has been modified is formed on the exposed portion. The crystalline part and the insulating film 10
The crystallinity decreases due to the mutual reaction between 5. Therefore, the crystalline insulating film 103 in this portion does not exhibit the original high dielectric constant and nonlinear capacitance characteristic, and the dielectric constant is 1/10.
It drops below.

Of the crystalline insulating film, the portion 102 formed on the lower electrode 104 exhibits a high dielectric constant and nonlinearity, and the performance as a capacitor does not deteriorate.

That is, according to the present invention, the lower electrode 10
4 on the outer side of the lower electrode 104 without impairing the crystallinity, high dielectric constant and non-linear capacitance characteristics of the crystalline insulating film 102 formed on Only the properties of the film 103 can be selectively changed in a self-aligned manner. As a result, the dry etching of the crystalline insulating film or the step of forming another insulating film, which is required in the above-described conventional technology, is not required, and various highly integrated semiconductor devices can be manufactured at a much lower cost than before. Can be manufactured in.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing an embodiment of the capacitor of the present invention, and the process for forming this capacitor will be described with reference to FIGS.

First, as shown in FIG. 2A, a semiconductor layer 201 on which an element (not shown) for controlling the voltage applied to the capacitor is formed is formed by a known method. did. As the semiconductor layer 201, for example, a semiconductor substrate on which a field effect transistor for driving a capacitor is formed can be used.

On the upper surface of the semiconductor layer 201, the upper surfaces of the electrode terminals (not shown) of the above-mentioned element to be connected to the capacitor are exposed.

Next, an insulating film 203 is formed to insulate the lower electrode of the capacitor and the electrode terminal from each other. In this embodiment, a silicon oxide film formed by the atmospheric pressure CVD method is used as the insulating film 203. However, in order to improve the flatness of the interface between the lower electrode of the capacitor and the silicon oxide film 203, for example, Heat treatment may be performed by adding boron, phosphorus, or the like to increase the fluidity of the insulating film at high temperatures.

Next, a connection hole was formed in the insulating film 203, and a conductive plug 203 for connecting the lower electrode of the capacitor and the electrode terminal was formed. This conductive plug 20
No. 3 was formed by depositing tungsten or titanium nitride using the low pressure CVD method and filling the inside of the connection hole. Titanium nitride may be deposited instead of tungsten.

Next, the conductor layer 204 to be the lower electrode
Was formed. The material of the conductor layer 204 varies depending on the material of the crystalline insulating film deposited on the conductive layer 204. For example, the crystalline insulating film may be lead zirconate titanate (PZ).
In the case of the T) film, a laminated film of platinum and titanium nitride or a laminated film of platinum and tantalum is preferable.

After forming a mask layer 205 made of a photoresist film for processing the lower electrode into a predetermined shape, the conductor layer 204 is exposed by argon ion milling, as shown in FIG. 2B. The removed part,
The lower electrode 204 was formed. At this time, the etching time was lengthened so that the exposed portion of the insulating film 203 as the base was slightly etched. At the stage where this process is completed, the remaining mask layer 205 has a film thickness of at least 200.
to be nm. As the mask layer 205,
Various well-known photoresists used for forming a semiconductor device can be used.

Next, the acceleration voltage is 40 kV and the driving amount is 1 × 1.
A silicon atom is ion-implanted under the condition of 0 ¹⁷ / cm ² , and as shown in FIG. 3A, a layer 206 containing many silicon atoms is formed in a region of a depth of about 100 nm from the surface of the insulating film 203. did. As the implanting species at this time, in addition to silicon, a implanting species containing a halogen atom, preferably fluorine or chlorine can be used, and in order to suppress crystallization of a crystalline insulating film formed in a later step. It is valid.

After removing the mask layer 205 as shown in FIG. 3B, a crystalline insulating film was formed on the entire surface as shown in FIG. 4A. In this embodiment, 100 n of lead titanate is used as the crystalline insulating film by MOCVD.
m deposited. As lead titanate, Pb (DPM) ₂ heated to 140 ° C. and Ti (i-OC ₃ H ₇ ) ₄ heated to 30 ° C. were introduced into the reaction vessel while using argon as a carrier gas, and oxygen was added at 1000 cc / It was supplied at a flow rate of minutes to oxidize the raw material. The substrate temperature was 550 ° C.

As is apparent from FIG. 4A, the lead titanate film 208 formed on the Si-rich layer 206 formed by Si ion implantation is the layer 206.
Since Si contained therein diffuses in the lead titanate film 208, crystallization is hindered and the dielectric constant is about 10-20. Such a peculiar phenomenon in the lead titanate film 208 formed on the layer 206 containing a large amount of Si is considered to be caused by the accelerated oxidation of silicon in the presence of lead.

The above silicon implantation energy is 200
When the voltage is increased to keV, the layer 208 to be modified passes through the lower insulating layer insulating film 203 and reaches the layer 201 in which the element is formed, and the characteristics of the element formed in the layer 201 deteriorate. Resulting in. Further, Si ions pass through the ion-implanted mask layer 205, and the lower electrode 204
Since Si remains in the lower electrode 204 even after the mask layer 205 is removed, the crystallinity of the lead titanate film 207 deposited on the lower electrode 204 also deteriorates.

Further, the film thickness of lead titanate 207 is set to 50.
If the thickness is increased to about 0 nm, the effect of suppressing the crystallization is reduced. This is the surface modification layer 20 in which Si is implanted.
The amount of silicon supplied from 6 is the thick lead titanate film 2
This is because there is a shortage with respect to 07. Lead titanate film 207
Of these, the dielectric constant of the portion 207 deposited on the lower electrode 204 was about 150, and the voltage dependence of the capacitance showed a non-linear characteristic and a hysteresis characteristic.

Next, a platinum film was deposited by the MOCVD method to form the upper electrode 209, and the semiconductor device shown in FIG. 4B was formed.

When the surface is not modified and the layer 208 containing a large amount of Si is not formed, the lower electrode 20 is formed.
4 and the insulating film 203 have different lead titanate deposition rates, so that a layer having significant surface irregularities and high conductivity may be formed on the insulating film 203.
Poor electrical insulation sometimes occurred between adjacent capacitors. However, in the present invention, as described above, the insulating film 2
Since a layer 208 containing a large amount of Si is formed on the surface of 03, such a highly conductive layer is not formed thereon, and there is no fear of electrical insulation failure between adjacent capacitors.

In the present invention, when the silicon atoms are added in the percent order, a clear effect is obtained, so that the ion implantation amount of the silicon atoms is about 10.
^It may be ¹⁵ cm to ³ or more. As a means for modifying the surface of the insulating film, instead of the above-mentioned ion implantation, a lower electrode 204 of the capacitor is patterned and formed, and then heat treatment is performed at 1000 ° C. for about 30 minutes in a hydrogen atmosphere. Then, the exposed surface of the lower insulating film 203 may be reduced. Further, instead of modifying the surface of the insulating film 203, the same effect can be obtained by intentionally changing the composition of the insulating film in the final stage of forming the lower insulating film 203. A desirable result is obtained when the concentration of silicon ions and halogen ions in the plasma insulating film formed on the modified surface is approximately 1% (in number of atoms) or more.

The present invention is particularly effective for a semiconductor device having a high integration density, but is also applicable to a semiconductor device which does not require a high integration density, for example, a large capacity capacitor used in an analog IC.

Further, in FIG. 1, the element for controlling the voltage applied to the capacitor is shown as an example included in the layer 201, but it is formed on the same plane by providing an appropriate wiring layer. It is also possible to do so.

[0033]

As is apparent from the above description, according to the present invention, it is possible to effectively prevent the interference between capacitors using the crystalline insulating films adjacent to each other and increase the parasitic capacitance, and to achieve high integration and manufacturing. It is effective in reducing costs.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a process drawing showing an embodiment of the present invention.

FIG. 3 is a process drawing showing an embodiment of the present invention.

FIG. 4 is a process drawing showing an embodiment of the present invention.

[Explanation of symbols]

101 ... Upper electrode, 102 ... Crystalline insulating film, 103
... Amorphized insulating film, 104 ... Lower electrode, 105 ... Interlayer insulating film, 106 ... Electrode connecting plugs, 107, 2
01 ... Layer containing element, 202 ... Connection plug, 203 ... Insulating film, 204 ... Platinum for lower electrode, 2
05 ... Mask layer, 206 ... Modified layer, 207 ... Crystalline lead titanate film, 208 ... Amorphous lead titanate, 209
… Upper electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8242 27/108 29/78 21/8247 29/788 29/792 7514-4M H01L 29 / 78 301 M 371

Claims (12)

[Claims] 1. An insulating film formed on a semiconductor layer on which an element for driving a capacitor is formed, a lower electrode having a predetermined shape formed on a predetermined region of the insulating film, and the insulating film. A crystalline insulating film continuously formed on the exposed surface of the film and the lower electrode, and an upper electrode formed on the crystalline insulating film, wherein:
A portion where the lower electrode is not formed has a modified surface, and the crystallinity and the dielectric constant of the crystalline insulating film formed on the modified surface are different from those on the lower electrode. A semiconductor memory device having a crystallinity and a dielectric constant lower than that of the above-mentioned crystalline insulating film formed in. 2. The semiconductor memory device according to claim 1, wherein the crystalline insulating film is made of barium titanate or lead titanate. 3. The semiconductor memory device according to claim 1, wherein the insulating film is made of silicon dioxide, and the modified layer is a layer in which the oxidation number of silicon is reduced. 4. The semiconductor memory device according to claim 1, wherein the modified surface is an ion-implanted layer. 5. The semiconductor memory device according to claim 3, wherein the modified surface contains more silicon than other portions. 6. The semiconductor memory device according to claim 1, wherein the insulating film is made of silicon dioxide, and the modified surface is a layer obtained by reducing silicon dioxide. . 7. The semiconductor memory device according to claim 1, wherein the semiconductor layer is a semiconductor substrate on which a MOS transistor is formed. 8. A step of forming an insulating film on a surface of a semiconductor layer on which an element is formed, a step of forming a conductive film on the insulating film, and removing an unnecessary portion of the conductive film. Forming a lower electrode having a desired shape, etching the exposed portion of the insulating film to a desired depth, modifying the exposed region of the insulating film, and removing the crystalline insulator. Forming a film having a crystallinity and a dielectric constant lower than that of the crystalline insulating film formed on the lower electrode on the surface of the modified insulating film, and forming an upper electrode A method of manufacturing a semiconductor memory device, comprising the steps of: 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein the step of modifying the exposed region of the insulating film is performed by ion implantation. 10. The method of manufacturing a semiconductor memory device according to claim 9, wherein silicon is ion-implanted. 11. The method of manufacturing a semiconductor memory device according to claim 9, wherein the group 7a element is ion-implanted. 12. The semiconductor memory device according to claim 8, wherein the step of modifying the exposed region of the insulating film is performed by reducing the exposed region of the insulating film. Production method.