JPH0750661B2 - Manufacturing method of metal oxide metal capacitor - Google Patents

Description

[Detailed Description of the Invention] [Outline] Metal Oxide Metal (MO)
M) A dummy pattern for forming a conductive film for plating the upper electrode of the capacitor is provided.

[Industrial application field]

The present invention relates to a method of manufacturing a capacitor, and more particularly, to a method of forming an upper electrode of a MOM capacitor by selective plating.

[Conventional technology]

As input / output circuits for high-frequency field-effect transistors (FETs), conventionally, gold on alumina (ceramic) is etched to form a distributed constant circuit pattern, and further, chip capacitors (C) and wires (inductances (L)). ] Or patterning the tantalum nitride film to form L, C, R circuits to form an amplifier. Conventionally, this type of circuit is about 3 cm square.

There is a demand for miniaturizing such an amplifier and incorporating it in a hermetic package of 5 mm to 1.0 cm square. When such an amplifier is made, one amplifier (impedance
When connecting 50 Ω) to the next amplifier, the package is arranged and the terminals are brought into contact with each other for conduction, and the output of the previous stage is used as the input of the next stage to obtain a multistage amplifier. For example, if 5db per unit, by increasing the number as needed, a product with a gain of (5x2), (5x3) ... db can be easily obtained, and the degree of freedom in design and configuration is increased. Getting bigger,
Cost reduction by unitization is also realized.

It is a very small capacitor required for the above-mentioned amplifier
A cross-sectional view of the MOM capacitor during the process is shown in FIG. In the figure, 11 is a sapphire substrate [sapphire single crystal wafer (thickness: about 0.3 mm). This is a substitute for the conventional alumina], 12 is a gold lower electrode having a thickness of 3 to 5 μm, and 13 is a dielectric having a thickness of 0.1 to 1.0 μm formed by a chemical vapor deposition (CVD) method or vapor deposition. A body [for example, silicon dioxide (SiO ₂ )], 14 is a conductive metal film provided for forming the upper electrode 15 by plating [for example, nichrome / gold (NiC)].
r.Au)] is formed by vapor deposition to a thickness of 0.1 μm), 1
5 is a mask for selective plating of the upper electrode (for example, 5μ
m is a photoresist having a thickness of m), and 16 is an upper electrode of gold (Au) having a thickness of 5 μm. The material and thickness of the dielectric 13 are selected as needed. A cross section of the completed MOM capacitor is shown in Fig. 4 (b).

The reason for forming the upper electrode 16 by selective plating is 5μ.
This is because if the gold vapor-deposited to a thickness of m is etched, not only will the process take time, but also expensive gold will be wasted.

The above structure can be manufactured by a normal semiconductor process. The reason why the upper and lower electrodes 16 and 12 are formed to have a thickness of 3 to 5 μm is that they are required to have such a thickness in order to reduce circuit loss.

[Problems to be solved by the invention]

In the vapor deposition of the conductive metal film 14, there is a step at the edge of the lower conductor, and the dielectric 13 also has a step as shown in FIG. It may become thinner, or in some cases, a metal film may not be formed on the step. If that happens, there will be no continuity,
Since the metal film on the lower electrode is electrically isolated, plating is not performed and the upper electrode is not formed.

As a measure for surely forming the conductive metal film even in such a step portion, it has been attempted to taper the edge of the lower electrode 12, but it is extremely difficult to control it by an etching technique, and it is difficult to reduce the size. Therefore, taper is not preferable.

Alternatively, it has been proposed to form the conductive metal film thick, but this increases the cost and it is difficult to remove it in a later step.

Further, it was attempted to make it by electroless plating, but it was found that the quality of the metal film was difficult.

The present invention was created in view of these points, and the MOM
The aim is to provide a method in which the upper electrode of the structure is reliably made by plating.

[Means for solving problems]

The above-mentioned problems include a step of selectively forming a lower electrode on a substrate, a step of sequentially forming a dielectric and a conductive metal film on a substrate including the lower electrode, and an upper electrode forming region located on the lower electrode. And a step of forming a photoresist having an opening formed so as to expose at least a side surface portion of the lower electrode and a dummy area, the conduction metal film is energized, and the upper electrode forming area opened in the photoresist And a step of forming a plating film on the dummy region, which is solved by providing a method for manufacturing a metal oxide metal capacitor.

[Action]

In the method described above, the conductive metal film 14 is formed in the dummy region.
Although the conductive metal film 14a in the dummy area is electrically connected even if it is formed to be extremely thin or disconnected, the dummy area is plated to form the plated portion 18a, whereby the conductive metal required for plating is formed. All of the membrane 14b also conducts,
The upper electrode 16 is formed by plating. In the illustrated MOM, the capacitor that determines the capacitance is the upper electrode 1
Since it is only 6, the plated portion 18 does not affect the capacity of the MOM.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1B, the lower electrode 12 of Au is formed on the sapphire substrate 11 to a thickness of 3 to 5 μm as in the conventional example. As a general method, NiCr · Au is vapor-deposited to a thickness of 0.1 μm, and the lower electrode 12 is formed by selective plating.

Then, as shown in FIG. 1C, SiO ₂ is grown to a film thickness of 0.5 μm by the CVD method or vapor deposition to form the dielectric 13.

Then, NiCr / Au is vapor-deposited to a thickness of 0.1 μm to form a conductive metal film 14. At this time, it is assumed that the metal film 14 is disconnected at the step portion of the edge of the lower electrode 12.

In the next patterning of the photoresist 15 shown in FIG. 1D, not only the upper electrode is formed, but also the dummy region 17 is exposed at the step portion of the lower electrode 12.

Next, in the plating process, since the conductive metal film 14a in the dummy region 17 is conductive, the plated portion 18a is first formed in the dummy region.

According to an experiment by the present inventor, the plated portion 18a was formed within an extremely short time due to current concentration. The portion above the upper electrode 16 and the plated portion 18 is further plated, which serves to establish conduction with the disconnected metal film 14b.

Then, as shown in FIG. 1 (e), the photoresist 15 is removed, and the conductive metal film 14 which is not plated by etching is removed. Although the plating 18 remains, it is the upper electrode 16 that determines the capacity of the MOM shown in the figure. Therefore, leaving the plated portion 18 has no effect on the capacity of the MOM.

Then, if necessary, the dielectric is etched to complete the MOM capacitor structure similar to that shown in FIG.

A second embodiment of the invention is shown in the sectional view of FIG. First
In FIG. 1 (c) of the embodiment, the stepped portion, that is, the dielectric layer 13 in the dummy region 17 is removed by etching prior to the deposition of the conductive metal film 14. Then, a conductor film is vapor-deposited to obtain the structure shown in FIG.
However, the electrically conductive metal films 14a and 14b are not sufficiently electrically connected at the step portion.

Therefore, by plating the dummy area as in the case of the first embodiment, the conductive metal films 14a and 14b can be quickly connected. The structure at this time is shown in the sectional view of FIG. By continuing the plating, the upper electrode 16 is further plated.

FIG. 3 shows a case where the dielectric layer 13 is thicker than the conductive metal film 14 (third embodiment). In this example, connection is difficult even at the stepped portion of the dielectric layer indicated by S in the figure,
The problem was solved by making the dummy area 17 include two steps.

〔The invention's effect〕

As described above, according to the present invention, in the formation of the upper electrode of the MOM by the selective plating, even if there is a disconnection at the step portion of the lower electrode in the conductive metal film for plating,
The disconnection portion is connected to establish an electrical connection with the opened metal film to realize selective plating of the upper electrode, which is effective in improving the MOM manufacturing yield.

[Brief description of drawings]

1 (a) to (e) are sectional views of the first embodiment of the present invention, FIG. 2 is a sectional view of the second embodiment of the present invention, FIG. 3 is a sectional view of the third embodiment of the present invention, and FIG. FIG. 5 is a sectional view showing a problem of the conventional example, which is a sectional view of the conventional example. 1 to 3, 11 is a sapphire substrate, 12 is a lower electrode, 13 is a dielectric, 14 is a conductive metal film, 15 is a photoresist, 16 is an upper electrode, 17 is a dummy region, and 18 is a plated portion. is there.

Claims (1)

[Claims] 1. A step of selectively forming a lower electrode on a substrate, a step of sequentially forming a dielectric and a metal film for conduction on a substrate including the lower electrode, and an upper electrode forming region located on the lower electrode. And a step of forming a photoresist having an opening formed so as to expose at least a dummy area that exposes a side surface of the lower electrode, an upper electrode forming area opened in the photoresist by energizing the conductive metal film. And a step of forming a plating film on the dummy region, the method of manufacturing a metal oxide metal capacitor.