JPH0736720A - Redundant computer equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if a large-scale system is not constructed, the control operation can be switched to the standby side processor device immediately when the control side goes down while maintaining continuity. To do so. [Structure] Each processor device includes an OS execution memory means,
Program execution memory means, CPU device, step count means for starting the program by starting, counting the number of execution steps of the program and storing the number of steps executed up to that time by interruption to the CPU device, and interrupted by interruption When the program is restarted, the number of execution steps stored in its own step counting means is compared with the number of execution steps stored in the step counting means in the partner processor device, and if the difference is larger than a predetermined value, one processor device The CPU device on one side is operated first, and the CP of both processor devices is operated.
The U device is provided with a synchronization deviation adjusting means for controlling the U device to start executing the programs at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual computer system applied for controlling a process, and more specifically, it connects two processor units that can be executed independently by a system bus. The present invention relates to a duplicated computer device configured so that any of them can access an input / output device connected to a system bus.

[0002]

2. Description of the Related Art In a processor device for controlling a process, a processor device for performing a process control operation has a dual structure in order to improve reliability, and in preparation for a failure of one processor device, an input / output device from the other processor device is also provided. A dual computer device configured to allow access to is widely used.

When constructing such a duplicated computer device, how to connect and operate two processor devices becomes an issue. The following connection systems have been considered in the past. (A) The two processor devices are operated by the same software while synchronizing with each other, and the input / output devices (I / O) connected to these processor devices are also configured to be duplicated so that both are always synchronized. To do. (B) Two processor devices operate the same software separately on the control side and the standby side. Each CPU in the two processor units operates independently. The input / output device is operated by the control side when outputting a signal to the outside of the processor device, and the process of completing the operation inside the other parts is
The processing is executed independently by each processor device. The processing by the processor device on the control side is equalized to the processor device on the standby side at an arbitrary timing of the system. The processor device on the standby side prepares for the down of the processor device on the control side while always executing the processing by the equalization. (C) Two processor devices operate the same software separately on the control side and the standby side. Each CPU device in the two processor devices operates independently. The I / O device operates only on the control side, and the other one stands by in an executable state. Regarding the data operated by the processing by the processor device on the control side, the application software of the processor device on the control side equalizes the processor device on the standby side at an arbitrary timing. The processor device on the standby side prepares for the down of the processor device on the control side while always executing the processing by the equalization. When the processor device on the control side goes down, the process is continued according to the contents of the equalization. (D) Two processor devices operate the same or unique software independently. The two processor devices perform synchronous communication between the application software of the respective devices at arbitrary timings, and when the processor device on the control side goes down, the processor device on the stand-by side substitutes for it.

[0004]

In the conventional system in which the two processor units are combined as described above, (a)
The method of (2) has a problem in that it is necessary to synchronize each CPU in the processor device every time an instruction is performed, and the processing speed of the CPU is significantly reduced. In the method of (b), when the execution right is switched from the processor device in the execution state to the processor device on the standby side, the processor device on the standby side until then re-executes the already executed processing. Will be executed. At this time, it takes time for standby execution, which is not suitable for a process control system that requires real-time processing.

The method (c) complicates the design of data to be equalized, and in particular, in application software created using a high-level language, the compiler determines how to take the data area. To be
There is a problem that it becomes difficult to handle. The method of (d) is
Since the switching of the duplex is realized only by the application software of the mutual devices, it cannot be said that the system has a general duplex configuration.

The present invention has been made in view of these points, and in a processor device having a duplex configuration, application software operating under the control of an operating system (OS) does not have to be aware of the duplication, and accordingly, An object of the present invention is to provide a highly reliable dual processor device with a simple configuration for duplex switching control.

Another object of the present invention is to obtain the above-mentioned object by the inventors of the present invention.
No. 581 is an improvement of the duplex computer system, and is a duplex system in which two processor units can perform synchronous execution even in the case of application software that operates without using much of the OS function. An object is to provide a computer device.

[0008]

SUMMARY OF THE INVENTION The present invention which achieves such an object is a dual computer device in which two processor devices that can be executed independently are connected by a system bus, and an operating system is provided in each processor device. A stored OS execution memory means, a program execution memory means that stores an application program that operates while using the functions of the operating system (system call), a CPU device that operates according to the programs stored in the memories, and A step count means for starting the program executed by the CPU device, counting the number of execution steps of the program, and storing the number of steps executed up to now by an interrupt to the CPU device, and a restart of the program interrupted by the interrupt At times, the number of execution steps stored in its own step counting means is compared with the number of execution steps stored in the step counting means in the partner processor device, and if the difference is larger than a predetermined value, the processor device side with less execution steps number Synchronization start adjusting means for starting the CPU device of the above-mentioned CPU device by the number of steps of the above difference so that the CPU devices of both processor devices operate in synchronization with each other, and an interrupt received by its own CPU device. And an inter-process-device interrupt generating means for transmitting the information to the CPU device in the partner processor device.

[0009]

In each processor unit, the normal operation is that the application program stored in the program execution memory means operates while using the function of the OS. The step counting means counts the execution steps of the application program executed by the CPU device, and when the processing is interrupted by an interrupt to the CPU device, stores the number of execution steps that has been operated until then.

The synchronization deviation adjusting means reads out the number of execution steps stored in each step counting device and compares them when the processing of the execution program is restarted after the processing of the execution program is interrupted by the interruption, and both CPUs If there is a difference more than the allowable number of execution steps of the application program executed on the device, one of the delayed C
The PU device is activated first, and both CPU devices are controlled to operate synchronously.

As a result, the two processor units are always synchronized and execute the same processing, and when one processor unit goes down, the other processor unit can take over the operation continuously. it can.

[0012]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a functional block diagram showing the basic functions of the device according to the present invention. In the figure, MD1, M
D2 is two processor devices that can be executed independently, and are connected to each other by a system bus SB. The I / O devices that are actually involved in control are divided into a control side and a standby side depending on who accesses. It is assumed that the processor device MD1 side is for the actual work (control), and the other processor device MD2 side is the standby side.

Each of the processor units MD1 and MD2 is configured to perform data processing and control according to application software written in a generalized language (for example, C language) that operates under the control of an operating system (OS). Has been done. In addition, each processor device does not cause multiple execution by the OS other than the external interrupt process, and interrupts the process executed by the application program continuously because the application program calls the OS, or It is configured only so that processing for operating the OS is executed, and data transmission and reception and communication between programs are all performed via the OS.

In each of the processor units MD1 and MD2, 11 is an OS execution memory means storing an OS, and 12 is a program execution memory means storing an application program. The application programs stored here operate while using the functions of the OS (while making system calls), and are prepared according to various applications. However, the design or creation of them is conscious of duplication processing. Done without doing. A CPU device 13 operates according to each program stored in each of the memory means 11 and 12, and has a function of performing data arithmetic processing, various controls, communication processing, and the like.

Reference numeral 14 is an input / output device (I / O device) provided corresponding to each of the processor devices MD1 and MD2. Here, an example is shown in which each processor device is connected to the system bus SB connecting the two processor devices and provided inside each processor device. However, it may be provided outside the processor device, or each processor device independently. They may be combined and operate independently.

Reference numeral 15 is a process for making a similar interrupt to the partner processor device in the standby state when an interrupt is received from the I / O device 14 when its own processor device is involved in the actual work. It is an inter-device interrupt generation means. When the processor device on the standby side receives an interrupt from the inter-process device interrupt generation means 15 on the control side, it generates a pseudo interrupt to its own CPU device and performs the same interrupt processing as on the control side. The interrupt processing in this case is normally performed completely asynchronously with the operation of the application.

Reference numeral 16 denotes a step counting means, which is started by starting an application program executed by the CPU device 13, receives a run cycle signal to count the number of execution steps of the program, and interrupts the CPU device 13. It is configured to store the number of steps executed up to a certain time. Reference numeral 17 denotes a synchronization deviation adjusting means, which is the number of execution steps stored in its own step count means 16 and the number of execution steps stored in the step count means in the partner processor when the program interrupted by the CPU device 13 is restarted. And a function for reading and comparing, and when the difference in the number of steps is larger than a predetermined value, the CPU device on the side of the processor device having the smaller number of execution steps is caused to start the operation earlier by the difference number of steps, and both processor devices The CPU device has a function of controlling the CPU device to operate synchronously, and a function of restarting the step counting means 16 when the synchronous operation is started.

The two processor devices MD1 and MD2 are
Both the control side and the standby side operate independently by their respective CPU devices 13, but each processor device has
Since the two CPU devices are operating, if the operations are normally performed, the operations are synchronized with each other. However, if interrupt processing or the like continues to occur in one of the processor devices, the synchronous operation of the two processor devices will slightly shift.

The inventors of the present invention first disclosed in Japanese Patent Application No. 5-2658.
As a solution to this point, the dual computer apparatus proposed in No. 1 waits for the synchronization operation at both processor apparatuses when the application program executes a system call (every time the OS is called). It is configured to do. When the CPU device 13 generates an interrupt, the processor device accesses its own I / O device 14 (in this case, the control side transfers data to the standby side). If done), the program execution memory means 1
This is the case, for example, when an access request is made to the I / O device 14 from a program operating in 2.

Here, when the application program does not make a system call for a long time, the execution processing of the application program in both processor devices may gradually shift (a synchronization shift occurs in both processor devices). There is a nature. In the apparatus of the present invention, the step count means 16 and the synchronization deviation adjusting means 17 are provided so that the synchronization deviation does not occur even when the application program does not make a system call for a long time.

FIG. 2 is a main structural block diagram of an apparatus for implementing the present invention. Each of the processors MD1 and MD2 is composed of a microprocessor MP and a main memory ME, which are coupled to each other via a common system bus SB. In each microprocessor MP, CPU execution control means 13 having a function of performing arithmetic processing of data, various controls and communication processing according to an application program, inter-processor interrupt generating means 15, step counting means 16, synchronization deviation adjustment Means 17 are provided. Areas functioning as the OS execution memory means 11 and the program execution memory means 12 are prepared in the main storage means ME.

It should be noted that the system bus SB has a dual structure, and when one of the system buses fails, the other system bus is used to send I / O from each processor unit.
The configuration may be such that the device can be accessed. Figure 3
FIG. 3 is a conceptual diagram showing a software configuration for two processor devices to operate in synchronization.

In the figure, reference numeral 120 is a block generally showing the application software stored in the program execution memory means 12, and 121 is a dispatcher for controlling the execution of the application software 120. The dispatcher 121 operates under the control of the OS. One of the two processor devices is divided into a control side and the other is on a standby side, so that the same application software (program) is executed in synchronization with each other, the step counting means 16 and the synchronization deviation adjusting means 17 Controlled by the function of. Reference numeral 18 denotes a step save area for storing the count number of the step counting means 16 for each application software, which can be read out from the synchronization deviation adjusting means 17.

Reference numeral 122 denotes an interrupt processing unit, which is the CPU device 1
3, a block that receives interrupts from the I / O device 14 and the inter-processor interrupt generating means 15 and performs the interrupt processing. The operation for synchronizing the apparatus thus configured will be described below. In normal operation, the application software 120 executes a predetermined application software while using the function of the OS. In such an operation, if the application software 120 makes a system call, 2
Waiting processing is performed such that the operations of the one processor device MD1 and MD2 are synchronized.

In the meantime, each step counting means 16 in each processor unit is started by a start signal from the dispatcher 121, and receives a run signal from the CPU to C.
The number of PU execution steps is counted. Where C
The application software executed by the PU is interrupted when an interrupt occurs. Further, after that, the execution is resumed again by the dispatcher 121 operating under the control of the OS and the synchronization deviation adjusting means 17.
By execution control of.

FIG. 4 is a flow chart showing the operation when the above-mentioned interrupt occurs. Interrupt processing means 1
Upon receiving an interrupt from the outside, the CPU 22 determines whether the CPU device is executing the application software 120, and if not, executes a normal interrupt process.
On the other hand, when the application software is being executed, the number of execution steps of the application software up to that time is read from the step counting means 16, and the value is stored in the step save area 18 for each application software. Add to value and store. After that, normal interrupt processing is executed.

Since the interrupt accepted by the interrupt processing means 122 is normally accepted only by one of the processor devices, the inter-process device interrupt generating means 15 sends the interrupt to the other processor device via the system bus SB. However, a pseudo interrupt is performed. In response to this pseudo interrupt, the other processor device similarly reads the number of execution steps up to that time from the step count means 16 on its own side, and stores the value in the step save area 18 for each application software. Each time it is added to the current value and stored.

FIG. 5 is a flow chart showing the operation of the dispatcher 121 and the synchronization deviation adjusting means 17. When the interrupt processing is completed, the dispatcher 12
In No. 1, the interrupted application software is restarted. Prior to that, the synchronization deviation adjusting means 17 reads the number of execution steps of the restarted application software stored in the step save area 18, and The number of execution steps is compared with the number of execution steps of similar application software in the partner processor device. Then, it is determined whether the difference is larger than a predetermined allowable value, that is, whether the deviation of the synchronous operation between the two processor devices exceeds the allowable range.

When it is determined that the synchronization deviation is large, the CPU device of the processor device operating later than the operation of the one processor device is activated in advance by the number of delayed steps. To do. As a result, the processor device side activated earlier catches up to the same number of steps. Then, the step counting means 16 is cleared and restarted, and at the same time, the application software in the two processor devices are both activated to shift to the synchronous operation.

In the above description, it is assumed that the two processor units basically operate for synchronization when the application software operating under the control of the OS makes a system call. However, the configuration for omitting the operation for establishing such synchronization may be adopted. In this case, for example, the synchronization deviation adjusting unit refers to and compares the count value of the step counting unit in a predetermined cycle, and adjusts the synchronization deviation according to the difference, so that the interrupt processing is performed for a long time. Even if it does not exist, the synchronization shift does not increase gradually.

[0031]

As described above in detail, according to the present invention, two processor devices can be divided into a control side and a standby side depending on who accesses the I / O device actually involved in control. In the duplicated computer device to be configured, each processor device is provided with means for counting the number of execution steps of application software and synchronization deviation adjusting means, and configured to automatically take synchronization by catching an opportunity of interrupt processing. It was done.

Therefore, according to the present invention, the processor unit on the control side and the processor unit on the standby side always execute the same processing in synchronization with each other, and the control side goes down without constructing a large-scale system. In such a case, it is possible to immediately switch the control operation to the standby side processor device while maintaining continuity. Further, when the two processor devices perform the synchronization operation based on the system call and the system call is not performed for a long time, the deviation of the synchronization operation can be avoided and the application program At the time of designing, it is not necessary to consider the duplication processing (processing for synchronization), and the application program can be easily created.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing basic functions of an apparatus according to the present invention.

FIG. 2 is a main configuration block diagram of an embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a software configuration for two processor devices to operate in synchronization with each other.

FIG. 4 is a flowchart showing an operation when there is an interrupt.

FIG. 5 is a flowchart showing the operations of a dispatcher 121 and a synchronization deviation adjusting means 17.

[Explanation of symbols]

 MD1, MD2 Processor device SB system bus 11 OS execution memory device 12 Program execution memory device 13 CPU device 14 Input / output device (I / O device) 15 Inter-process device interrupt generation device 16 Step count device 17 Synchronization deviation adjustment device

Claims (1)

[Claims] 1. A dual computer device in which two processor devices that can be executed independently are connected by a system bus, and each processor device uses an OS execution memory means for storing an operating system and a function of the operating system ( Program execution memory means for storing application programs that operate while making system calls, CPU devices that operate according to the programs stored in the memories, and execution of the programs that are started by the start of the programs executed by the CPU devices. Step counting means for counting the number of steps and storing the number of steps executed up to now by interruption to the CPU device, and at the time of restarting the program interrupted by the interruption,
The number of execution steps stored in its own step counting means is compared with the number of execution steps stored in the step counting means in the partner processor device, and if the difference is greater than a predetermined value, the CPU on the processor device side having the smaller number of execution steps A synchronization deviation adjusting means for starting the operation of the device by the number of steps of the difference and controlling the CPU devices of both processor devices to operate in synchronization, and an interrupt received by the own CPU device. A dual computer device comprising inter-process device interrupt generation means for transmitting to a CPU device in a side processor device.