JPH0736705B2 - Neutral point clamp type power converter controller - Google Patents

Description

Detailed Description of the Invention

 [Object of the Invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation control (PWM control) converter for converting AC power into DC power, and a PWM control inverter for converting DC power into AC power.
The present invention relates to a control device for a neutral-point clamp type power converter that generates a three-level output voltage applied to a power converter or the like.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration diagram of a main circuit and a control circuit of a conventional neutral point clamp type inverter. The figure shows one phase (U phase), and in the case of a three-phase output inverter, V,
The W and phase are similarly constructed.

In the figure, V _d1 and V _d2 are DC power supplies, and S _{1 to} S ₄
The self-turn-off device, D ₁ to D ₄ is flip - wheeling diode - de, D _5, D ₆ are clamping diodes - de, LOAD if the load, CT _U is a current detector. Further, as the control circuit, comparators C _U , C ₁ and C ₂ , a current control compensation circuit G
_U (s), triangular wave generator TRG, Schmitt circuit SH ₁ ,
SH ₂ is provided.

The output voltage V _U of this inverter changes as follows by turning on and off the _four elements S _{1 to} S ₄ . However, the total DC voltage is V _d ,
Let V _d1 = V _d2 = V _d / 2. That is, when S ₁ and S ₂ are on, V _U = + V _d / 2 When S ₂ and S ₃ are on, V _U = 0 When S ₃ and S ₄ are on, V _U = −V _d / It becomes 2. At this time, two devices must be turned on each. If all three are turned on at the same time, the DC power supply is short-circuited and the device is destroyed due to overcurrent.

For example, when an ON signal is input to the elements S _{1 to} S ₃ , the DC voltage V _d1 is short-circuited by the element S ₁ -S ₂ -S ₃ -diode D ₆ and an excessive short-circuit current flows to the elements. , The element is destroyed.

In order to prevent such a DC short circuit, the elements S ₁ and S ₃ are operated in reverse and the element S ₂ S ₄ is operated in reverse. That is, when the element S ₁ is on, the element S ₃ is turned off, and when the element S ₃ is on, the element S ₁ is turned off. Similarly, when the element S ₂ is on, the element S ₄ is turned off, and when the element S ₄ is on, the element S ₂ is turned off. FIG. 8 is a time chart for explaining the conventional pulse width modulation control method for the neutral point clamp type inverter.

In the figure, X and Y are PWM control carrier signals, X is a triangular wave varying between + E _{MAX and} 0, and Y is -E.
It is a triangular wave that changes between _{MAX and} 0. Also, e _i is P
WM control input signal. Input signal e _i and triangular wave X, Y
And gate signals g ₁ and g ₂ of the elements S _{1 to} S ₄ are generated. That is, when e _i > X, g ₁ = 1 and S ₁ is turned on and S ₃ is turned off. When e _i ≤X, when g ₁ = 0, S ₁ is turned off and S ₃ is turned on. When e _i ≧ Y, when g ₂ = 0, S ₄ is turned off and S ₂ is turned on. When e _i <Y, g ₂ = 1 and S ₄ is turned on and S ₂ is turned off.

As a result, the output voltage V _U becomes as shown in the bottom of the figure, and its average value (shown by the broken line) becomes a value proportional to the input signal e _i . As described above, the neutral point clamp type inverter has three levels (+) as the output voltage V _U.
V _d / 2, 0, the voltage of -V _d / 2) is obtained, and less voltage waveform of the harmonic component. In the case of a motor load, there are advantages that the pulsation of current is reduced and the torque ripple is also reduced.

[0009]

However, the conventional neutral point clamp type inverter control device has the following problems.

That is, the elements S _{1 to} S constituting the inverter
There is no problem if ₄ is an ideal switching element, but in reality it does not turn off immediately even when an off signal is given to the element, but it turns off after a certain period of time. The same applies when shifting from off to on, but generally the turn-off time is longer than the turn-on time.

Accordingly, for example, when giving an ON signal simultaneously element S ₃ Given an off signal to the element S _1, element S ₁
However, the element S ₃ is turned on before the element is turned off, and a period in which the _three elements S _{1 to} S ₃ are turned on occurs, which short-circuits the DC power source and causes an excessive current to flow, thereby destroying the element.

9 and 10 are time charts for explaining a conventional PWM control method for solving the problem. In the figure, g ₁ and g ₂ are signals obtained by the PWM control method of FIG.

[0013] from the signal g ₁ of the element S ₁ gate - to make a door signal g _s1, from the inverted signal of the signal g ₁ of the element S ₃ gate - door signal g
make _s3 The gate signal g _s1 is kept in the “0” state for Δt _D (dead time) after the signal g ₁ is changed from “0” to “1”, and then g _s1 = g ₁ is set. In addition, the gate signal g _s3 remains in the “0” state for Δt _D (dead time) after the inverted signal of the signal g ₁ changes from “0” to “1”, and then the inverted signal of g _s3 = g ₁ And The dead time Δt _D is determined in consideration of the turn-off time of the device. Thus, the element S ₁ and S ₃ of the gate - by only each short dead time Delta] t _D the ON period of the preparative signal g _s1, g _s3, to prevent the element S ₁ and S ₃ are turned on at the same time ing. The same applies to the _gate signals g _s2 and g _{s4 of the} elements S ₂ and S ₄ . This conventional method for preventing a DC short circuit by using dead time has the following drawbacks. That is, during the dead time Δt _D , the value of the output voltage V _U of the inverter changes depending on the direction of the output current.

FIG. 9 shows the output voltage of the inverter when the element S ₂ is on (S ₄ is off) and the elements S ₁ and S ₃ are alternately turned on and off while maintaining the dead time Δt _D. .

V_{U (+)}Is the output current I_UIs the arrow in Figure 5
Output voltage when flowing in the positive direction_{U (-)}Is
Output current I_UFlow in the opposite direction (negative direction) to the arrow in Figure 7.
Indicates the output voltage when Dead time Δt_DDuring the element
S₁And S₃Are both off and I_UIs positive
Element S₂Current flows through_{U (+)}= 0, and I_U
When is negative, diode D₁, D₂Current flows through
V_{U (-)}= V_d/ 2. That is, the first gate
Issue g₁As the element S₁, S₃When turning on and off
Output voltage is V_UThen, I_UWhen> 0, V_{U (+)}= V_U-ΔV_D  I_UWhen <0, V_{U (-)}= V_U+ ΔV_D  Becomes However, ΔV_DDead time Δt_DBased on
It is an ass voltage.

Further, FIG. 10 shows an element S₃Is on (S₁Oh
F), element S₂And S_FourDead time Δt_DKeep
Inverter output voltage when turned on and off alternately
Show. V_{U (+)}Is the output current I_UIs the direction of the arrow in Fig. 7 (positive
Direction), the output voltage_{U (-)}Is the output power
Flow I_UFlows in the opposite direction (negative direction) to the arrow in FIG.
The output voltage is shown. Dead time Δt_DWhile the element S₂
And S_FourAre both off and I_UIs positive when is
Code D₃, D_FourCurrent flows through V_{U (+)}= -V_d
/ 2, I_UIs negative, the element S₃Current through
Flow, V_{U (-)}= 0. That is, the first gate
Issue g₂As the element S₂, S_FourWhen turning on and off
Output voltage is V_UThen, the same as when explained in FIG.
I_UWhen> 0, V_{U (+)}= V_U-ΔV_D  I_UWhen <0, V_{U (-)}= V_U+ ΔV_{D Becomes This dead time Δt D} Bias voltage Δ based on
V_DIs the output current I_UPWM is determined by the direction of
Control carrier wave (triangular wave) frequency f_cAnd if the following
Is represented as ΔV_D= (V_d/ 2) ・ f_c・ Δt_D  For example, f_c= 1KH_Z, Δt_D= 100 μsec
If ΔV_D= 0.1 · (V_d/ 2). This bias voltage ΔV_DIs the output current I_UControl
Control, it acts as a disturbance source and distorts the current waveform.
Problem remains. Conventionally, in order to cancel this disturbance source, P
WM control input signal e_iΔV depending on the direction of the output current
_DCompensation voltage ± Δe_DIs added. But,
It is difficult to cancel it completely, and the waveform distortion in the output current
The reality is that they will remain. Also, this compensation voltage ± Δ
e_DThe control range of PWM control is narrowed by the amount
As a result, the utilization rate of the neutral clamp type inverter is reduced.
Will be lowered.

As described above, in the conventional PWM control of the neutral point clamp type inverter, in order to prevent a DC short circuit, a dead time is required at the time of switching each of the elements S ₁ and S ₃ and the elements S ₂ and S _4. However, there is a problem in that the output current is distorted due to this dead time and the utilization rate of the inverter is reduced.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a control device for a neutral point clamp type power converter capable of eliminating dead time and preventing DC short circuit. [Constitution of Invention]

[0019]

To achieve the above object, the present invention provides four self-extinguishing elements S ₁ , connected in series.
S _2, S _3, and S _4, these flip connected antiparallel to each element - wheeling diode - de _{D 1, D 2, D 3} , D4
In the neutral point clamp type power converter composed of a diode for clamping, and diodes D ₅ and D ₆ for clamping, one is a triangular wave X that changes between zero and the positive side as a carrier for pulse width modulation control, and the other is 1. One is a triangular wave generating means for generating a triangular wave Y that changes between zero and minus side, a means for discriminating the output current of the power converter or the direction of the signal I _U corresponding to the output current, and the I _U is I _U Under the condition of ≧ 0, the two lower self-extinguishing elements S ₃ and S ₄ are turned off, the PWM control input signal e _i is compared with the triangular waves X and Y, and when e _i > X, the upper side Two self-extinguishing elements S ₁ ,
S ₂ is turned on. When Y ≦ e _i ≦ X, the upper self-extinguishing element S ₂ is turned on (S ₁ is turned off). When e _i <Y, the upper two self-extinguishing elements S ₁ ,
When the gate signal for turning off S ₂ and the I _U turn off the upper two self-extinguishing elements S ₁ and S ₂ under the condition of I _U <0, and when e _i > X, the lower Side two self-extinguishing elements S ₃ ,
Turn off S _{4 When} Y ≦ e _i ≦ X, turn on the lower self-extinguishing element S ₃ (turn off S ₄ ) When e _i <Y, turn on the two lower self-extinguishing elements S ₃ ，
It is characterized in that a means for producing a gate signal for turning on S ₄ is provided.

[0020]

According to the present invention, the gate signals of the _four elements S _{1 to} S ₄ constituting the neutral point clamp type power converter are converted into the output current I _U.
Prevents DC short circuit by limiting by the direction of
Moreover, it eliminates the dead time that has been conventionally required.

That is, when I _U ≧ 0, the output current I _U
Since not flow through the element S ₃ and S _4, leaving the element S ₃ and S ₄ in the OFF state. Conversely, when the I _U <0, since the output current I _U is not flow through the element S ₁ and S _2, leaving the element S ₁ and S ₂ in the OFF state. In this way, the upper two elements are in the off state of either one of the lower two elements, and the converter is not short-circuited by direct current.

In the conventional control device, the dead time is provided so that the elements S ₁ and S ₃ are not turned on at the same time. However, according to the present invention, when I _U ≧ 0, the element S ₃ is always turned on. Therefore, it is not necessary to provide a dead time for the gate signal of the element S ₁ . Further, when I _U <0, the element S ₁ is always off, and again, it is not necessary to provide a dead time for the gate signal of the element S ₃ . Similarly, it is not necessary to provide a dead time between the elements S ₂ and S ₄ .

That is, according to the present invention, the signal obtained by comparing the PWM control input signal e _i with the triangular wave X or Y can be directly used as the gate signal of the elements S _{1 to} S _4. As a result, a value proportional to the input signal e _i is obtained as the output voltage, and it becomes possible to control the output current without distortion. Further, the decrease in the utilization rate of the converter due to the dead time is eliminated, and the conventional problems can be solved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a neutral point clamp type inverter of the present invention.
1 is a block diagram of a main circuit configuration diagram and a control device for explaining a control device for a computer.

In the figure, V _d1 and V _d2 are DC power supplies, S ₁ and
S _2, S _3, S ₄ are self-turn-off _{device, D 1 D 2, D 3} , D
₄ flip - wheeling diode - de, D _5, D ₆ are clamping diodes - de, LOAD is the load, CT _U is a current detector. Further, as control circuits, comparators C _U , C ₁ ,
C ₂ , current control compensation circuit G _U (s), triangular wave generator TR
G, Schmitt circuits SH ₁ and SH ₂ , hysteresis circuit HS, inverters IV to IV ₃ , AND circuits AND _{1 to} AN.
D ₄ is provided. This figure shows only one phase (U phase), but in the case of three phase load, other two phases (V phase, W phase)
Phase) is similarly configured.

[0026] The load current I _U of the U-phase detected by the current detector CT _U, is input to a comparator C _U of the current control circuit. The comparator C _U has a current command value I _U ^* And the detected current value I _U are compared, and the deviation ε _U = I _U ^* -Calculate I _U. The deviation ε _U is amplified by the next control compensation circuit G _U (s) and used as the input signal e _{i for} PWM control.

The triangular wave generator TRG has two triangular waves X and Y.
Is generated and input to the comparators C ₁ and C ₂ . The comparator C ₁ compares the triangular wave X with the input signal e _i , and the Schmitt circuit S
Gate signal g for device elements S ₁ and S ₃ via H ₁
Make _one Further, the comparator C ₂ receives the triangular wave Y and the input signal e.
_i is compared and the gate signal g ₂ for the elements S ₂ and S ₄ is produced via the Schmitt circuit SH ₂ . The hysteresis circuit HS detects the direction of the output current I _U of the inverter, and its output sig is as follows. When I _U ≧ 0, sig = 1 When I _U <0, sig = 0

Inverters IV _{1 to} IV ₃ and AND circuit AN
The following logical operation is performed via D _{1 to} AND ₄ to obtain the gate signals g _{s1 to} g _s4 of the elements S _{1 to} S ₄ . That is, Becomes FIG. 2 is a time chart for explaining the operation of the present invention.

The carrier wave X for PWM control is a triangular wave having a constant frequency which varies between 0 and + E _MAX . Further, the carrier wave Y is a triangular wave having a constant frequency that varies between 0 and -E _MAX , and is in phase with the carrier wave X. The PWM control input signal e _i is compared with the triangular waves X and Y to generate signals g ₁ and g ₂ .
That is, when e _i > X, g ₁ = 1 e _i ≦ X, when g ₁ = 0 e _i <Y, and when g ₂ = 1 e _i ≧ Y, g ₂ = 0.

When the output current I _U of the inverter changes as shown by the broken line, the output si of the hysteresis circuit HS
g changes from "0" to "1" at point a and "1" at point b
Becomes "0". The _gate signal g _s1 of the element S ₁ is si
When g = 1 (I _U ≧ 0), g _s1 = g _{1 and the} element S ₁
Is turned on and off, and when sig = 0 (I _U <0), g _s1
= 0 and the element S ₁ is turned off. The _gate signal g _s2 of the element S ₂ is When sig = 0 (I _U <0), g _s2 = 0 and the element S
Turn off ₂ . The _gate signal g _s3 of the element S3 is When sig = 1 (I _U ≧ 0), g _s3 = 0 and the element S
Turn off ₃ . The _gate signal g _s4 of the element S ₄ is sig =
When 0 (I _U <0), g _s4 = g _{2 and the} element S ₄ is turned on and off. When sig = 1 (I _U ≧ 0), g _s4 = 0
Then the element S ₄ is turned off.

That is, when I _U ≧ 0, the lower element S ₃
And S ₄ are turned off, and the upper elements S ₁ and S ₂ are turned on and off according to the original signals g ₁ and g ₂ to perform PWM control.

When I _U <0, the upper element S ₁
And S ₂ are turned off, and the lower elements S ₃ and S ₄ are turned on and off according to the original signals g ₁ and g ₂ to perform PWM control.

[0033] Thus, conventional dead time Delta] t _D is no longer required, inverter - data of the output voltage V _U is the original signal g ₁ determined by comparing the triangular wave X, Y and the input signal e _i of the PWM control,
The waveform is according to g ₂ , and its average value is the input signal e.
_The value is proportional to _i .

FIG. 3 is a block diagram of a control circuit showing another embodiment of the present invention, in which MM ₁ and MM ₂ are mono-multi circuits,
AND _{1 to} AND ₉ are AND circuits, MT _{1 to} MT ₄ are minimum on-time setting circuits, and OR ₁ and OR ₂ are OR circuits. Other symbols are similar to those shown in FIG. Also, FIG.
Shows a specific circuit example of the minimum on-time setting circuit in FIG. 3, where MM ₁₁ is a mono-multi circuit and OR ₁₁ is an OR circuit. 5 and 6 are time charts for explaining the operation of the control circuit of FIG. 3 and 4 will be described below with reference to FIGS. 5 and 6.

FIG. 5 is an enlarged view of point b of the time chart of FIG. 2, in which the direction of the output current I _U is switched from positive to negative at point b. At the timing when the signal sig shifts from "1" to "0", the mono-multi circuit MM ₁ of FIG. 3 is triggered and its output m
_{1 is set} to “0” during the time Δt ₁ . In the vicinity of point b, g ₁
= 0, and g ₂ is switched from "0" to "1" by time ψ before the point b. sig = 1 (I _U
≧ 0), g _s3 and g _s4 are 0 regardless of the signals g ₁ and g ₂ , and the elements S ₃ and S ₄ are off. Switch from on to off by ψ. When at point b sig is switched to the "0" from "1", the signal g _1, g regardless ₂ g _s1, g _s2 becomes "0", the element S _1, S ₂ is turned off. That is, in this case, the ON signal is applied to the elements S ₃ and S ₄ after the time ψ after the OFF signal is applied to the element S ₂ .

In general, the switching elements S _{1 to} S ₄ forming the inverter are turned off immediately even when an off signal is given.
It cannot be turned off and there is a certain delay time. There is also a delay time when the device turns on, but the turn-off time is generally longer than the turn-on time. Therefore, when the time ψ is shorter than the turn-off time of the element S ₂ ,
Near the point b, the elements S ₃ and S ₄ are turned on before the element S ₂ is turned off, and the DC power supply V _d2 of FIG. 1 is connected to the diode D ₅ -element S.
₂ -The element S ₃ -The element S ₄ is short-circuited. This causes an excessive current to flow and destroys the element.

Therefore, as shown in FIG. 3, the monostable multi-circuit MM ₁ operating at the rising edge of the signal sig and the signal sig.
Prepare a mono-multi circuit MM ₂ that operates at the falling edge of
The output signals m ₁ and m ₂ are ANDed by the AND circuit AND ₅ , and m 3 = m ₁ · m ₂ is input to the next AND circuits AND _{6 to} AND ₉ .

As shown in FIG. 5, the mono-multi circuit MM ₁ ,
The output signals m ₁ and m ₂ of MM ₂ are “0” only during the time of Δt _1.
Becomes AND circuits AND _{6 to} AND ₉ are AND circuits A
Output signals g _{s1 to} g _{s4 of} ND _{1 to} AND ₄ and the signal m ₃
In the case of FIG. 5, the monomulti circuit MM ₁ operates at the point b, and all the elements S _{1 to} S ₄ have Δt ₁
Turn off only during the period. As a result, the _gate signals g _s3 , g _s4 of the elements S ₃ , S ₄ are g _s31 ,
It becomes g _s41 . If the set time Δt ₁ of the mono-multi circuits MM ₁ and MM ₂ is set longer than the turn-off time of the element, the above DC short circuit can be prevented. FIG. 6 shows b ′ of FIG.
This is an enlarged view of the vicinity assuming that the direction of the current changes at a point.

The mono-multi circuit MM ₁ operates at point b ',
Gate signal g to turn off all elements by Δt _{1
s11, g s21, g s31,} g s41 is given. As a result, the width of the ON period of the _gate signal g _s11 of the element S ₁ becomes narrow, and the minimum ON time Δt _ON of the element cannot be satisfied.

Generally, in a large-capacity inverter, a GTO (gate turn-off thyristor) or the like is used as a self-extinguishing element, and a snubber circuit is installed to suppress overvoltage at turn-off. In order to initialize (discharge) the voltage of the snubber circuit capacitor, when the GTO is turned on, the on state must be maintained for a certain time (minimum on time: about 100 microseconds, for example). If the element is turned off again before the voltage of the snubber capacitor becomes sufficiently low, the capacitor voltage becomes abnormally high, and an overvoltage is applied to the element to destroy the element.

In the case of FIG. 6, since the ON period of the element S ₁ is short, the snubber capacitor is not sufficiently discharged and the element S ₁ is not discharged.
There is a danger that ₁ will be damaged by overvoltage. So, in Figure 3,
Signals g _s11 , g _s21 , g _s31 , and g _s41 through the minimum on-time setting circuits MT _{1 to} MT ₄ and signals g _s12 ,
g _s22 , g _s32 , and g _s42 .

A specific circuit example of the minimum on-time setting circuit MT ₁ is shown in FIG. The mono-multi circuit MM ₁₁ operates at the rising _edge of the signal g _s11 and becomes “1” for the time Δt ₁₁ . The OR circuit OR _11, it takes the logical sum of the output signals g _s11 of the output signal m ₁₁ and AND circuit the AND ₆ monostable multivibrator circuit MM _11, a signal g _s12 indicated by a broken line in FIG. 6 is obtained. By making the set time Δt _{11 a} little longer than the above-mentioned minimum on-time Δt _ON , the voltage of the snubber capacitor can be sufficiently discharged, and overvoltage may occur.

However, another problem remains here. That is, when the ON time of the element S ₁ is increased as described above,
In the period of δ in FIG. 6, the element S ₁ is on and the element S ₂ is off. During this period of δ, the output current I _u of the inverter shown in FIG.
Direction flows in the direction of the arrow in the figure, since the element S ₂ is off, the current I _U flows through the diodes D ₃ and D _4, and the terminal on the cathode side of the element S ₂ is DC. Since the element S ₁ is connected to the negative side of the power source V _d2 and the element S ₁ is turned on, the anode side terminal of the element S ₂ is connected to the positive side of the DC power source V _d1 . Thus, the DC full voltage V _d = V _d1 + V _d2 is applied to the element S _2, so that the breaking element S ₂ Overvoltage.

In order to solve this problem, in the present invention, OR circuits OR ₁ and OR ₂ are provided as shown in FIG. That is, when the gate signal g _{s11 of} the element S ₁ is "1", the element S ₂ is also set to "1" by the OR circuit OR ₁ , and the total DC voltage is applied to the element S _2. Is being prevented. This will be described with reference to FIG. 6. When the _gate signal g _{s11 of} the element S ₁ has a long on-state like g _s12 , the element S _{2 gate} signal g _s21 also has g _s22 (shown by a broken line).
As described above, the mode in which the total DC voltage is applied to the element S ₂ is eliminated by extending the ON period. Upper 2
When the two elements S ₁ and S ₂ are on, the lower two elements S ₃ and S ₄ are always off, so that the DC power supply is not short-circuited.

This also applies to the elements S ₃ and S ₄ , and when the element S ₄ is turned on by the OR circuit OR ₂ , the element S ₃ is always turned on so that the DC total voltage V ₃ is applied to the element S _{3. It} prevents _{d from} being applied. At this time, since the upper two elements S ₁ and S ₂ are off, the DC power supply is not short-circuited.

As described above, according to the neutral point clamp type inverter control device of the present invention, either the upper two elements or the lower two elements are turned off depending on the direction of the output current of the inverter. By eliminating the mode of short-circuiting the DC power supply in this state, the dead time that was previously indispensable is eliminated. As a result, the utilization rate of the converter is improved, and it is possible to reduce the size and weight of the device or reduce the cost. Further, there is no disturbance to the current control system due to dead time, and a sinusoidal current without distortion can be supplied to the load.

In the apparatus shown in FIG. 1, in order to determine the direction of the output current, the actual current I _U is detected, and the direction is determined using the detected current. In this case, when there is a ripple in the output current, the positive and negative are frequently switched near the zero point, which makes the determination difficult.

When controlling the output current of the inverter, the current reference signal I _U ^* Is preferably used to determine the direction of the output current. That is, the current reference I _U ^* Has no ripple,
The zero point can be easily determined, and in particular, I _U =
I _U ^* Therefore, the error in the judgment of the direction becomes small. Even if the phase is slightly deviated, the current control waveform is slightly distorted and there is no risk of damaging the element. Although the above description has described the inverter for the U phase, the V phase and W phase are controlled in the same manner, and the conventional problems can be solved. Also, 3
It goes without saying that the same applies to a phase 3-wire type load. Further, although the frequencies of the carrier waves X and Y have been described as constant, it is needless to say that the same can be applied even if the frequencies are changed as long as the phases of the both are the same.

Further, in order to make the explanation easy to understand, the above-mentioned embodiment is shown as a control block diagram of hardware, but it is needless to say that the present invention can be executed by software by using a microcomputer or the like. Yes.

Although the inverter for converting the DC power into the AC power has been described above, it goes without saying that the same can be applied to the converter for converting the AC power into the DC power.

[0051]

As described above, according to the control device for a neutral point clamp type power converter of the present invention, it is possible to prevent a DC power supply short circuit which is conventionally required without providing a dead time. It will be possible. Therefore, the utilization rate of the converter is improved, the size and weight of the device can be reduced or the cost can be reduced, and the disturbance to the current control system due to dead time is eliminated, and a sinusoidal current without distortion is supplied to the load. A neutral point clamp type power converter control device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main circuit and a block diagram of a control device showing an embodiment of a control device of a neutral point clamp type power converter of the present invention.

FIG. 2 is a time chart for explaining the operation of the present invention.

FIG. 3 is a control block diagram showing another embodiment of the present invention.

FIG. 4 is a partial detailed circuit diagram of FIG. 3;

FIG. 5 is a time chart for explaining the operation of another embodiment of the modified invention shown in FIG.

FIG. 6 is a time chart for explaining the operation of another embodiment of the modified invention shown in FIG.

FIG. 7 is a configuration diagram of a main circuit of a neutral point clamp type power converter and a lock diagram of a conventional control device.

FIG. 8 is a time chart for explaining the operation of the conventional control device.

FIG. 9 is a time chart for explaining the operation of the conventional control device.

FIG. 10 is a time chart for explaining the operation of the conventional control device.

[Explanation of symbols]

V _d1 , V _d2 ... DC power supply, S _{1 to} S ₄ ... Self-extinguishing element, D
₁ ~ D ₄ ... Freewheeling diode, D ₅ , D ₆ ...
Clamping diodes - de, LOAD ... load, CT _U ... current _{detector, C U, C 1, C} 2, C 3 ... comparator, G _U (s) ...
Current control compensation circuit, TRG ... Triangular wave generator, SH ₁ , S
H _2, SH ₃ ... Schmitt circuit, HS ... hysteresis circuit, IV ₁ ~IV ₃ ... inverting circuit, AND ₁ ~AND ₉ ...
AND _{circuit, MM 1, MM 2, MM} 11 ... monostable multivibrator circuit, MT ₁ ~MT ₄ ... minimum ON time setting circuit, OR _1,
OR ₂ , OR ₁₁ ... OR circuit.

Claims (4)

[Claims] 1. Four self-extinguishing elements S connected in series
₁ , S ₂ , S ₃ and S _4, and freewheeling diodes D ₁ , D ₂ , D ₃ and D 4 which are connected in antiparallel to these elements.
In the neutral point clamp type power converter composed of a diode for clamping, and diodes D ₅ and D ₆ for clamping, one is a triangular wave X that changes between zero and the positive side as a carrier for pulse width modulation control, and the other is 1. One is a triangular wave generating means for generating a triangular wave Y that changes between zero and minus side, a means for discriminating the output current of the power converter or the direction of the signal I _U corresponding to the output current, and the I _U is I _U Under the condition of ≧ 0, the two lower self-extinguishing elements S ₃ and S ₄ are turned off, the PWM control input signal e _i is compared with the triangular waves X and Y, and when e _i > X, the upper side Two self-extinguishing elements S ₁ ,
S ₂ is turned on. When Y ≦ e _i ≦ X, the upper self-extinguishing element S ₂ is turned on (S ₁ is turned off). When e _i <Y, the two upper self-extinguishing elements S ₁ ,
When the gate signal for turning off S ₂ and the I _U turn off the upper two self-extinguishing elements S ₁ and S ₂ under the condition of I _U <0, and when e _i > X, the lower Side two self-extinguishing elements S ₃ ,
Turn off S _{4 When} Y ≦ e _i ≦ X, turn on the lower self-extinguishing element S ₃ (turn off S ₄ ) When e _i <Y, turn on the two lower self-extinguishing elements S ₃ ，
A control device for a neutral point clamp type power converter comprising means for generating a gate signal for turning on S ₄ . 2. The upper two self-extinguishing elements S ₁ , S
_{When an} on-gate signal is applied to the self-extinguishing element S ₁ of ₂ , an on-gate signal is always applied to the self-extinguishing element S ₂ .
When the on-gate signal is given to the self-extinguishing element S ₄ of the lower two self-extinguishing elements S ₃ and S ₄ , it is provided with means for giving the on-gate signal to the self-extinguishing element S ₃ without fail. The control device for the neutral point clamp type power converter according to claim 1. 3. Four self-extinguishing elements S connected in series
₁ , S ₂ , S ₃ and S _4, and freewheeling diodes D ₁ , D ₂ , D ₃ and D 4 which are connected in antiparallel to these elements.
In the neutral point clamp type power converter composed of a diode for clamping, and diodes D ₅ and D ₆ for clamping, one is a triangular wave X that changes between zero and the positive side as a carrier for pulse width modulation control, and the other is 1. One is a triangular wave generating means for generating a triangular wave Y that changes between zero and minus side, a means for discriminating the output current of the power converter or the direction of the signal I _U corresponding to the output current, and the I _U is I _U Under the condition of ≧ 0, the two lower self-extinguishing elements S ₃ and S ₄ are turned off, the PWM control input signal e _i is compared with the triangular waves X and Y, and when e _i > X, the upper side Two self-extinguishing elements S ₁ ,
S ₂ is turned on. When Y ≦ e _i ≦ X, the upper self-extinguishing element S ₂ is turned on (S ₁ is turned off). When e _i <Y, the upper two self-extinguishing elements S ₁ ,
When the gate signal for turning off S ₂ and the I _U turn off the upper two self-extinguishing elements S ₁ and S ₂ under the condition of I _U <0, and when e _i > X, the lower Side two self-extinguishing elements S ₃ ,
Turn off S _{4 When} Y ≦ e _i ≦ X, turn on the lower self-extinguishing element S ₃ (turn off S ₄ ) When e _i <Y, turn on the two lower self-extinguishing elements S ₃ ，
A means for producing a gate signal for turning on S ₄ and a chain of the gate signal for a predetermined time Δt ₁ when the direction of the output current of the power converter or the signal I _U corresponding to the output current is switched. A control device for a neutral point clamp type power converter comprising a locking means. 4. The means for securing the minimum on-time of the self-extinguishing element which has been in the on-state until then when the gate signal is locked for the predetermined time Δt _1. The control device for the neutral point clamp type power converter according to the third item.