JPH07336228A - Charge pump type D / A converter - Google Patents

Abstract

(57) [Summary] [Object] To simplify the configuration of a charge pump type D / A converter that generates an analog control amount from a digital error signal in a control loop. In a charge pump type D / A converter that converts an n-bit error signal into an analog amount in a control loop to generate a control amount of a control target circuit, a current value according to a pull-in / steady operation signal Are controlled, and m charge pump circuits 26 for outputting a current according to the weight of each bit, and among the n-bit error signals, the upper m bits are selected at the time of pull-in, and at the steady time, ,
The lower m bits are selected and the charge pump circuit 26 is selected.
And a multiplexer circuit 25 for outputting to.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art (FIGS. 7 and 8) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Action Example (a) Description of One Example (FIGS. 2 to 6) (b) Description of another embodiment Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump type D / A converter for generating an analog controlled variable from a digital error signal in a control loop.

In order to improve the recording density of magnetic disk and magneto-optical disk devices in recent years, partial response signaling has been used. In particular, PRML (Partial-response signaling with ma
ximum-likelihood sequence detection) is preferred.

In such a partial response reproducing system, the error signal in the AGC loop or the PLL loop is given as a digital value. Therefore, a converter that converts such a digital error signal into an analog control amount is required with a simple configuration.

[0005]

2. Description of the Related Art FIGS. 7 and 8 are explanatory views of a conventional technique. The automatic gain control circuit (AGC circuit) used in the partial response system has a feedback loop based on digital data as well as a feedback loop based on an analog amount. Also in the phase locked loop,
It has a PLL loop with digital data. In this digital loop, a charge pump type D / A converter is used to convert a digital error signal into an analog control amount.

As shown in FIG. 7, in order to create a control voltage in a control loop based on AGC digital data, discrete data of a waveform (digital output) obtained by a subtractor 90 through a digital equalizer (not shown) is used. ) Is subtracted from the target value (digital amplitude value) to obtain an n-bit amplitude error signal. This amplitude error signal is input to the n charge pumps 91 to 9n and converted into a current value.

Each of the n charge pumps 91 to 9n converts the current value into a value corresponding to the weight of each bit of n bits. Then, the sum of the outputs of the n charge pumps 91 to 9n is converted into a voltage by a low-pass filter (not shown) and becomes an AGC control voltage output.

Similarly, the partial response type phase locked loop circuit, as shown in FIG. 8, outputs each bit output of a 7-bit digital phase error signal from a phase error detector (not shown) to seven charge pumps. 81 to 87, and converted into a current value corresponding to the bit weight. Then, the sum of the outputs of the seven charge pumps 81 to 87 is input to the filter 70, converted into a control voltage, and the voltage controlled oscillator 71 is controlled.

Generally, in the automatic gain control circuit and the phase locked loop circuit, the loop gain at the time of pull-in is made higher than that at the steady operation so that the target amplitude is reached in a short time. Further, in the steady operation, the loop gain is lowered to prevent the rapid amplitude fluctuation due to the frequency change of the data from being followed, and to absorb the slow amplitude fluctuation such as the modulation.

Conventionally, as the loop gain changing means, as shown in FIGS. 7 and 8, one charge pump 91 to 9n or 81 to 87 is provided for each bit of output data of the error signal. Further, as shown in FIG. 7, a method has been adopted in which the current value of the charge pump for all bits is increased by the pull-in operation / steady-operation switching signal during pull-in and switched small during steady-state operation.

[0011]

However, the conventional technique has a problem that the circuit configuration is complicated because a charge pump circuit is required for each input bit.
Therefore, the device price is high.

An object of the present invention is to provide a charge pump type A / D converter for simplifying the structure.

Another object of the present invention is a charge pump type A / D for varying the loop gain with a simple structure.
To provide a converter.

[0014]

FIG. 1 shows the principle of the present invention. According to claim 1 of the present invention, in the control loop, n
In a charge pump type D / A converter that converts a bit error signal into an analog amount and generates a control amount for a controlled circuit, a current value is controlled according to a pull-in / steady operation signal, and each bit weight is controlled. M charge pump circuits 26 for outputting a current according to the above, and among the n-bit error signals, the upper m bits are selected when pulling in, and the lower m bits are selected when steady. It has a multiplexer circuit 25 for outputting to the charge pump circuit 26.

According to a second aspect of the present invention, in the charge pump type D / A converter according to the first aspect, the controlled circuit is a variable gain amplifier 10, and the control amount generated by the charge pump circuit 26 is the It is characterized in that it is a controlled variable of the variable gain amplifier 10.

According to a third aspect of the present invention, in the charge pump type D / A converter according to the second aspect, the control loop is provided after the variable gain control circuit 10 (1
+ D) filter 11, an A / D converter 12 for A / D converting the output of the filter 11, a digital equalizer 13 for equalizing the output of the A / D converter 12,
And a subtracter 23 for generating an n-bit amplitude error signal by subtracting the target amplitude from the equalized output.

According to a fourth aspect of the present invention, in the charge pump D / A converter according to the first aspect, the circuit to be controlled is a voltage controlled oscillator 36, and the control amount generated by the charge pump circuit 26 is the It is characterized in that it is a controlled variable of the voltage controlled oscillator 36.

A fifth aspect of the present invention is the charge pump type D / A converter according to the fourth aspect, wherein the control loop includes a (1 + D) filter 11 and the filter 11.
Of the output of A according to the clock of the voltage controlled oscillator 36.
A / D converter 12 for A / D conversion, digital equalizer 13 for equalizing the output of the A / D converter 12, and phase error detector for generating an n-bit phase error signal based on the equalized output. 31 and 31.

[0019]

When the error amount at the time of pulling in is large, the influence of the lower bits on the control amount is small, and the influence of the upper bits on the control amount is large. On the contrary, when the fluctuation in the steady state is small, the influence of the upper bits on the control amount is small, and the influence of the lower bits on the control amount is large. For this reason, the upper bit may be controlled at the time of pull-in, and the data may be converged during the steady state, and if the fluctuation is small, the lower bit may be controlled.

The present invention provides a multiplexer 25,
The upper bit and the lower bit are selected at the time of pulling in and in the steady state. Further, in order to change the loop gain, the charge pump circuit 2 can be operated at the time of pull-in and at the time of steady state.
The current value of 6 was changed. As a result, a digital error signal can be converted into an analog control amount with m charge pump circuits, which are smaller in number than n bits of input. As a result, the number of charge pump circuits can be reduced.

[0021]

【Example】

(A) Description of an Embodiment FIG. 2 is a block diagram of a PRML reproducing circuit for an embodiment of the present invention. As shown in FIG. 2, the variable gain amplifier (GCA) 10 amplifies a read signal read by a magnetic head from a magnetic disk. The variable gain amplifier 10 can change its gain by an external control voltage. The (1 + D) filter 11 is a filter that performs waveform equalization corresponding to (1 + D). In addition, D is
The data input one sample before is meant, and 1 + D means the sum of the data input at the current time and the data delayed by one sampling period.

The n-bit A / D converter 12 has (1+
D) Convert the analog output of the filter 11 into an n-bit digital output. The digital equalizer 13 is composed of a well-known cosine equalizer. Digital equalizer 1
3 automatically equalizes the signal according to the partial response characteristic in the radial direction of the disk.

The automatic gain control circuit 2 is an analog AGC.
It has a loop and a digital AGC loop. The amplitude detector 20 detects the difference between the analog output amplitude of the (1 + D) filter 11 and the analog target amplitude. Switching circuit 2
1 is for switching from an analog AGC loop to a digital AGC loop. Low pass filter 22
Converts the output current of the switching circuit 21 into a voltage to generate a control voltage for the variable gain amplifier 10.

The subtractor 23 subtracts the digital target value from the discrete waveform data from the digital equalizer 13 and outputs a digital error value. The n-bit charge pump D / A converter 24 converts the n-bit digital error value into an analog current amount and outputs it to the switching circuit 21.

The operation of the automatic gain control circuit 2 will be described. First, connect the switching circuit 21 to the amplitude detector 20,
Form an analog AGC loop. That is, the amplitude detector 2
The switching circuit 2 sets the analog error amount obtained by subtracting the analog target amplitude from the analog output of the 0 (1 + D) filter 11.
Output from 1 to the low pass filter 22. As a result, a control voltage is created from the analog error amount and is fed back to the variable gain amplifier 10 for amplitude control.

After the amplitude control by the analog AGC loop, the switching circuit 21 is switched to the digital AGC loop. That is, the switching circuit 21 is connected to the charge pump type D /
It is connected to the A converter 24. Therefore, the digital error value obtained by subtracting the digital target value from the discrete data of the waveform from the digital equalizer 13 of the subtractor 23 is converted into the analog current amount by the charge pump D / A converter 24, and the switching circuit 21 To enter. This analog amount is converted into a voltage by the low pass filter 22 and controls the variable gain amplifier 10.

Next, the phase synchronization circuit 3 has a ternary judging device 30 for judging the sample output Y (n) of the digital equalizer 13 in three values and outputting a ternary judgment output X (n). The ternary value determiner 30 compares the sample value Y (n) with the two slice levels S1 and S2 and determines the determination value X of +1, 0, −1.
The determination is made in (n).

The phase detector 31 outputs the sample output Y (n).
And the three-value determination output X (n), the phase difference Δτ (n) is calculated. For example, in the case of PRML class-IV, the phase detector 31 has F.Dolivo.W.Scott and G.Un.
Gerbock's paper "FAST TIMING RECOVERY FOR PARTI
AL-RESPONSE SIGNALING SYSTEMS '' (1986 IEEE CH2655-
9/89 / 0000-0573).

That is, assuming that the sampling voltage of the read signal after the partial equalization is Y (n) and the ternary decision result by the ternary decision unit 30 is X (n), the phase difference Δτ (n) is given by the following equation. expressed. Δτ (n) = Y (n−1) · X (n) −Y (n) · X
(N-1)

The frequency comparator 32 determines the frequency of the servo signal read from the servo surface of the magnetic disk and outputs a frequency error. The multiplexer circuit 33 outputs the phase error of the phase detector 31 when the magnetic disk is read, and the frequency comparator 32 when the magnetic disk is not read.
The frequency error of is output.

Charge pump type D / A converter 34
Converts the digital error signal of the multiplexer circuit 33 into an analog current amount. The loop filter 35 is composed of a low pass filter. Loop filter 35
Converts the amount of analog current into a voltage and controls the voltage controlled oscillator 36. The voltage controlled oscillator 36 generates a synchronous clock used as a sample clock of the A / D converter 12 or the like.

The operation of the phase locked loop 3 will be described. When the magnetic disk is not read, the multiplexer circuit 33 is connected to the frequency comparator 32. As a result, the voltage control oscillator 36 generates a clock synchronized with the frequency of the servo signal.

On the other hand, when reading the magnetic disk, the multiplexer circuit 33 is connected to the phase detector 31. As a result, the voltage controlled oscillator 36 generates a clock controlled by the phase error of the sample output of the digital equalizer 13.

FIG. 3 is a block diagram of the charge pump type D / A converter of the automatic gain control circuit 2 of FIG. 2, and FIG. 4 is an operation explanatory diagram thereof.

As shown in FIG. 3, a charge pump type D /
The A converter 24 includes four multiplexers 25-1.
25-4 are provided. In the output of the subtractor 23, the output terminal 1 is the most significant bit and the output terminal 8 is the least significant bit. The outputs of the output terminals 1 and 5 are input to the multiplexer 25-1. Multiplexer 25-2
Is input to the outputs of the output terminals 2 and 6. The outputs of the output terminals 3 and 7 are input to the multiplexer 25-3. The outputs of the output terminals 4 and 8 are input to the multiplexer 25-4.

An initial pull-in / steady-operation switching signal is input to each of the multiplexers 25-1 to 25-4. When the switching signal indicates the initial pull-in, each of the multiplexers 25-1 to 25-4 has the output terminal 1,
Select 2, 3 or 4 outputs. On the other hand, when the switching signal indicates a steady operation, each of the multiplexers 25-1 to 25-4
Selects the output of the output terminals 5, 6, 7, and 8, respectively.

Further, the charge pump type D / A converter 2
4 is provided with four charge pump circuits 26-1 to 26-4 connected to the multiplexers 25-1 to 25-4, respectively. The charge pump circuits 26-1 and 26-2
An initial pull-in / steady-operation switching signal is also input to 6-4. When the switching signal indicates initial pull-in, the charge pump circuits 26-1 to 26-4 output currents of 128 mA, 64 mA, 32 mA and 16 mA, respectively. When the switching signal indicates a steady operation, the charge pump circuits 26-1 to 26-4 are 8 mA and 4 m, respectively.
It outputs currents of A, 2 mA, and 1 mA.

That is, the multiplexers 25-1 to 25-4
Selects the upper 4 bits during initial pull-in, and selects the lower 4 bits during steady operation. Further, the charge pump circuits 26-1 to 26-4 each output a current corresponding to the weight of the lower 4 bits in a steady state, and output a current corresponding to 16 times the weight of the upper 4 bits at the initial pull-in. .

This operation will be described with reference to FIG. When the sampling mode switching signal is low, the switching circuit 21 is connected to the amplitude detector 20 to form an analog AGC loop. The analog error amount obtained by subtracting the analog target amplitude from the analog output of the (1 + D) filter 11 of the amplitude detector 20 is output from the switching circuit 21 to the low pass filter 22. As a result, a control voltage is created from the analog error amount and is fed back to the variable gain amplifier 10,
Amplitude control.

Next, the sampling mode switching signal becomes high, indicating the mode (sampling mode) by the digital AGC loop. As a result, the switching circuit 21
Are connected to the charge pump D / A converter 24. At the same time, the pull-in / steady-operation switching signal indicates the low pull-in mode.

As a result, the multiplexers 25-1 to 25-2
5-4 selects the upper 4 bits of the output of the 8-bit subtractor 23. In addition, the charge pump circuits 26-1 and 26-2
6-4 outputs a current corresponding to the weight of the upper 4 bits.

Therefore, the digital equalizer 13 of the subtractor 23
The upper 4 bits of the 8-bit digital error value obtained by subtracting the digital target value from the discrete data of the waveform from are converted into an analog current amount by the charge pump type D / A converter 24 and input to the switching circuit 21. This analog amount is converted into a voltage by the low pass filter 22 and controls the variable gain amplifier 10.

After the end of the pull-in operation, the pull-in / steady-operation switching signal indicates a high steady-state operation. As a result, the multiplexers 25-1 to 25-4 select the lower 4 bits of the output of the 8-bit subtractor 23. or,
The charge pump circuits 26-1 to 26-4 output a current corresponding to the weight of the lower 4 bits.

Thus, the lower 4 bits of the 8-bit digital error value of the subtractor 23 are charge pump type D / A.
It is converted into an analog current amount by the converter 24 and input to the switching circuit 21. This analog amount is converted into a voltage by the low pass filter 22, and the variable gain amplifier 10
To control.

In this way, even if the number of charge pump circuits is reduced to half, automatic gain control with variable loop gain in the control loop is possible.

FIG. 5 is a block diagram of the charge pump type D / A converter of the phase locked loop circuit 3 of FIG. 2, and FIG. 6 is a circuit diagram of the charge pump circuit of FIG.

As shown in FIG. 5, the multiplexer 37
Consists of 7-bit input and 4-bit output.
The phase error signal has 8 bits, 7 bits are used for data bits, and 1 bit is used for sign bits. The sign bit indicates the polarity of 7 data bits. The data bits of 7 bits and the bit selection signal are input to the multiplexer 37. Multiplexer 37
Is the upper 4 bits or the lower 4 depending on the bit selection signal.
Select a bit.

Four charge pump circuits 38-1 to 38
The output of the multiplexer 37, the bit selection signal, and the sign bit are input to -4. When the bit selection signal indicates initial pull-in, each charge pump circuit 38
-1 to 38-4 are 1 according to the polarity of the sign bit.
It outputs currents of 28 mA, 64 mA, 32 mA and 16 mA. When the bit selection signal indicates a steady operation, each of the charge pump circuits 38-1 to 38-4 outputs a current of 8 mA, 4 mA, 2 mA, 1 mA according to the polarity of the sign bit.

That is, the multiplexer 37 selects the upper 4 bits at the initial pull-in, and the lower 4 bits at the steady operation.
Select a bit. Further, the charge pump circuits 38-1 to 38-1
38-4 outputs a current corresponding to the weight of the lower 4 bits in the steady state, and outputs a current corresponding to 16 times the weight of the upper 4 bits in the initial pull-in.

As shown in FIG. 6, each charge pump circuit 38 includes an AND gate 380 that performs a logical product of a sign bit and a data bit, an inverting circuit 381 that inverts the sign bit, an output of the inverting circuit 381 and a data bit. AND gate 382 which ANDs with.

Further, each charge pump circuit 38 includes a first constant current source 383 for flowing a current in one direction, and a first switch circuit 384 which is opened / closed by the output of the AND gate 380.
It has a second current source 386 that allows a current to flow in one direction and a second switch circuit 385 that is opened and closed by the output of the AND gate 382.

The current sources 383 and 386 are connected in series via the switch circuits 384 and 385. And
The loop filter 35 formed of a capacitor is connected to the middle point of the current sources 383 and 386. The current switching circuit 387 responds to the bit selection signal by the current source 383,
Supply 386 reference current. This current switching circuit 38
7 controls the current sources 383 and 386 so that when the bit selection signal indicates the pull-in time, 16 times the current flows when compared with the time when the bit selection signal indicates the steady operation.

Therefore, when the sign bit is positive ("1"), the switch circuit 384 is opened and closed by the output of the data bit from the AND gate 380, and the current flows from the first current source 383. On the other hand, when the sign bit is negative (“0”), the output of the data bit from the AND gate 382 opens and closes the switch circuit 385, and a current flows in the direction of the second current source 386. In this way, a current corresponding to the polarity of the error signal is obtained.

Next, the operation of the phase locked loop 3 will be described.
When the magnetic disk is not read, the multiplexer circuit 33
Are connected to the frequency comparator 32. As a result, the voltage control oscillator 36 generates a clock synchronized with the frequency of the servo signal.

On the other hand, when reading the magnetic disk, the multiplexer circuit 33 is connected to the phase detector 31. As a result, the voltage controlled oscillator 36 generates a clock controlled by the phase error of the sample output of the digital equalizer 13. At this time, the bit select signal first indicates a low pull-in mode.

As a result, the multiplexer 37 selects the upper 4 bits of the output of the 7-bit phase error signal. Further, the charge pump circuits 38-1 to 38-4 output a current corresponding to the weight of the upper 4 bits.

Therefore, the upper 4 bits of the 7-bit digital error value are converted into an analog current amount by the charge pump type D / A converter 34, converted into a voltage by the filter 35, and the voltage controlled oscillator 36 is controlled.

After completion of this pull-in, the bit selection signal directs high steady operation. As a result, the multiplexer 37 selects the lower 4 bits of the 7-bit phase error signal. In addition, the charge pump circuits 38-1 to 38-3
8-4 outputs a current corresponding to the weight of the lower 4 bits.

As a result, the lower 4 bits of the 7-bit digital error value are the charge pump type D / A converter 3
4, the voltage is converted into an analog current amount, and the voltage is converted into a voltage by the filter 35 to control the voltage controlled oscillator 36.

(B) Description of Other Embodiments In addition to the above embodiments, the present invention can be modified as follows. Although the error signal has been described as having 8 bits, it may have another number of bits. Although the example of the magnetic disk has been described, the present invention can also be applied to a magneto-optical disk or the like. Although the present invention has been described with reference to the embodiments, various modifications are possible within the scope of the gist of the present invention, and these modifications are not excluded from the scope of the present invention.

[0061]

As described above, according to the present invention,
It has the following effects. Since the multiplexer is provided and the upper bit and the lower bit are selected and input to the charge pump,
The number of charge pumps can be greatly reduced, and the configuration becomes simple. Moreover, since the number of charge pumps can be reduced, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a PRML reproducing circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of the charge pump type D / A converter of FIG.

FIG. 4 is an operation explanatory diagram of the circuit of FIG.

FIG. 5 is a block diagram of another example of the charge pump type D / A converter of FIG.

FIG. 6 is a circuit diagram of the charge pump circuit of FIG.

FIG. 7 is an explanatory diagram (1) of a conventional technique.

FIG. 8 is an explanatory diagram (part 2) of the conventional technique.

[Explanation of symbols]

 2 Automatic Gain Control Circuit 3 Phase Lock Circuit 10 Variable Gain Amplifier 24, 34 Charge Pump D / A Converter 25-1 to 25-4 Multiplexer 26-1 to 26-4 Charge Pump 36 Voltage Controlled Oscillator 37 Multiplexer 38-1 to 38-4 Charge pump

Front page continued (72) Inventor Masahide Kanae 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

[Claims] 1. A charge pump type D / A converter for converting an n-bit error signal into an analog amount in a control loop to generate a control amount of a controlled circuit, in accordance with a pull-in / steady operation signal, Current value is controlled,
And m for outputting the current according to the weight of each bit
Of the charge pump circuits (26), among the n-bit error signals, the upper m bits are selected at the time of pulling in, and the lower m bits are selected at the time of steady operation, and are supplied to the charge pump circuit (26). A charge pump type D / A converter having a multiplexer circuit (25) for outputting. 2. The charge pump D / A converter according to claim 1, wherein the control target circuit is a variable gain amplifier (10), and the control amount generated by the charge pump circuit (26) is
A charge pump type D / A converter which is a controlled variable of the variable gain amplifier (10). 3. The charge pump type D / A converter according to claim 2, wherein the control loop includes a (1 + D) filter (11) provided at a stage subsequent to the variable gain control circuit (10) and the filter (11). ) A / D converter (12) for A / D converting the output, a digital equalizer (13) for equalizing the output of the A / D converter (12), and a target amplitude subtracted from the equalized output. And a subtractor (23) for generating an n-bit amplitude error signal. 4. The charge pump type D / A converter according to claim 1, wherein the control target circuit is a voltage controlled oscillator (36), and the control amount generated by the charge pump circuit (26) is
A charge pump type D / A converter characterized in that it is a controlled variable of the voltage controlled oscillator (36). 5. The charge pump type D / A converter according to claim 4, wherein the control loop includes a (1 + D) filter (11).
A / D converter (12) for A / D converting the output of the filter (11) according to the clock of the voltage controlled oscillator (36), digital for equalizing the output of the A / D converter (12), etc. A charge pump type D / A converter comprising a quantizer (13) and a phase error detector (31) for generating an n-bit phase error signal based on the equalized output.