JPH07327037A - Cell transmitter - Google Patents

Abstract

(57) [Abstract] [Purpose] In a multilink communication network in which a plurality of terminal stations are connected by a plurality of links, to reduce the cell read speed from the transmission buffer provided to the terminal station transmitter to the link. With the goal. A transmitter has a number of transmission buffers (B1 to Bn) equal to the total number (n) of links, and cells input from terminals are cyclically input to the transmission buffer in the order of input and equal to the link transmission rate. Store at speed. When an empty slot is acquired in any of the links, cells are cyclically read from the transmission buffer at a rate equal to a single link transmission rate, put in the empty slot, and transmitted to the link. In another embodiment, the input of cells to the transmission buffer is such that the cells input to all buffers are input, the cells are read from the buffer corresponding to the link having an empty slot and transmitted, and the cells are stored in other buffers. Discard the same cell that was deleted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilink communication network in which a plurality of terminal stations are arranged in series, and the individual terminal stations are connected by a plurality of links having the same band and the same transmission direction.
The present invention relates to a transmitter of a multilink transmission control device installed in a terminal station for transmitting / receiving cells to / from a plurality of links.

[0002]

2. Description of the Related Art A plurality of ring-shaped transmission systems (hereinafter, each ring-shaped transmission system is simply referred to as a ring) are constructed by connecting individual terminal stations of a plurality of terminal stations with a plurality of rings having the same function. However, regarding a multi-ring communication network in which a plurality of fixed-length slots are circulated continuously in each ring, Japanese Patent Application No. 3-45484 and multi-link transmission control device were announced by Mr. Kobayashi, Mr. Hakama and Mr. Sato. .

Hereinafter, as a typical example of the multi-link communication network, the case of the announced multi-ring communication network will be described in detail with reference to the drawings. In the following description, the case where the number of parallel rings is 7 is taken as an example.

FIG. 7 shows the overall configuration of a multi-ring communication network to which the prior art is applied. In FIG. 7, 01-
Reference numeral 07 is a ring-shaped transmission line, 10 is a multilink transmission control device installed in a terminal station, 11 is a transmission unit of the multilink transmission control device, 12 is a reception unit of the multilink transmission control device, 25 is a cell transmission unit, 26 is a cell extraction unit, 60 is a transmission access control unit, and 70 is a reception access control unit.

FIG. 8 shows a detailed configuration of the multilink transmission control device 10. The same numbers as in FIG. 7 indicate the same components, and in FIG. 8, 13 is a data input unit, 14 is a cell disassembly unit, 15 is a terminal transmission buffer, 50 is a cell transmission control unit, 23 is a cell assembly unit, and 24 is A data output unit, 27 is a cell output control unit, 41 is a reception buffer, and 45 is a reception buffer read control table. The transmission unit 11 includes a data input unit 13, a cell disassembly unit 14, a terminal transmission buffer 15,
The cell transmission control unit 50 and the cell transmission unit 25 are included, and the reception unit 1
2 has a cell extracting unit 26, a reception buffer 41, a cell assembling unit 23, a data output unit 24, a cell output control unit 27, and a reception buffer read control table 45.

FIG. 9 shows the arrangement of slots that continuously circulate on the ring and the phase relationship of the slots between the rings. Figure 9
01 to 07 indicate a plurality of rings similar to FIG. 7, 101 is a slot, τ is a slot phase difference between adjacent rings, and the total phase difference between the rings is 1 slot length (or 1 slot length or less). It is an appropriate value such that However, in order to simplify the description, a case where the product of τ and the number n of parallel rings is equal to one slot length will be described as an example.

FIG. 10 shows the relationship between the data input to the data input unit 13 of the multi-link transmission control device 10 and cells, 102 is data, 103 is a cell, and 104 is a cell 10.
3 is a header, 105 is an open / close identification bit of the cell 103, 1
06 is the destination address of the cell 103, 107 is the cell 103
, 108 is a data identifier of the cell 103, and 109 is a cell number indicating which part of the data 102 the cell 103 is.

The data flow will be described with reference to FIGS. 7, 8, 9 and 10.

The multilink transmission control device 10 includes a transmitter 1
1 and a receiver 12 are connected to all of the plurality of rings to form a multi-ring communication network as a whole.

At the terminal station serving as the transmitting station, the multilink transmission control device 10 transmits the transmission data 102 input to the data input unit 13 to the cell disassembling unit 1 to 6 as shown in the example of FIG. After the data is decomposed into short partial data, each of the empty block identification bit 105, the destination address 106, the source address 107, the data identifier 108 for distinguishing from other data, and the number cell of one data are identified. A header 104 having a cell number 109 of 1 is added to create a cell 103 having a one-slot length (a fixed length). These cells 103 are stored in the terminal transmission buffer 15 in the order in which they were created. The receiving unit 12 extracts the circulating slot 101 by the cell extracting unit 26 and checks whether it is an empty slot or a busy slot that has already been used with a cell. In the case of a busy slot, the destination address of the cell stored in that slot is further checked to see if it is the cell addressed to the own terminal station. In the case of a slot containing a cell addressed to its own terminal station, reception operation is performed, and the slot is changed to an empty slot and transferred to the transmission unit 11. Further, the received empty slot and the slot containing a cell other than the one addressed to the own terminal station are directly transferred to the transmission unit 11. At the time when the receiving unit checks the free / busy identification bit or the cell destination address, the transmitting unit 11 can know to which ring the empty slots circulate. The stored cells 103 are taken out in the order in which they are stored under the control of the cell transmission control unit 50, and are inserted into the empty slot 101 via the cell transmission unit 25 for transmission.

As described above, the cells to be transmitted are taken out from the transmission buffer 15 in the order in which they are created, inserted into the empty slots and transmitted. Therefore, the order of cells cannot be reversed in this process.

Now consider the rate at which cells are read from the transmit buffer. Let's consider the case where you get consecutive empty slots in adjacent rings. When cells are inserted into these empty slots without fail and the number of parallel rings is n,
In order to equivalently realize a transmission rate n times the single ring rate, it is necessary to set the time for reading cells from the transmission buffer 15 within the slot phase difference τ time between adjacent rings. In other words, the read rate needs to be n times the single ring transmission rate. That is, when the single ring transmission rate is high, or when the parallel ring number n is increased to increase the total transmission rate, there is a drawback that the reading rate must be extremely high.

On the other hand, in order to keep the read speed low, it is possible to make the read speed equal to a single ring transmission speed. In this case, the time required to read the cell from the transmission buffer may be (τ × n). On the other hand, empty slots may arrive at multiple rings at intervals of time τ. Therefore, when a cell is being transmitted to one ring, the next cell cannot be read and transmission cannot be performed until transmission of the cell is completed, even if an empty slot can be acquired in another ring. become. That is, in this case, the speed of cells that can be transmitted from one terminal station cannot exceed the speed of a single ring, and therefore, even if pipeline processing is performed using multiple rings in parallel, the transmission line There is a drawback that the efficiency of use cannot be increased sufficiently.

At the terminal station serving as the receiving station, when the cells are taken out from a plurality of rings, the order of the cells may be reversed depending on the construction method of the receiving buffer. The above-mentioned patent by Kobayashi et al. Was made from the viewpoint of preventing the cell order inversion in the receiving unit, and relates to the transmitting unit of the multilink transmission control device, and is not directly related to the receiving unit. However, in order to understand the entire multi-link communication network, it is necessary to understand the operation of the receiving unit, which will be briefly described below.

In a multi-ring communication network, empty slots may be continuously acquired in adjacent rings,
As long as there is a cell to be transmitted, the transmission section inserts the transmission cells of its own terminal station into this empty slot without fail and transmits. This corresponds to the case where the cells addressed to the own terminal station may be continuously received by the adjacent rings when viewed from the receiving unit side. It is necessary to use the receive buffer when transferring cells destined for the own terminal station, which arrive dispersedly in a plurality of rings, to the subordinate terminals. Since the order of transmitted cells cannot be reversed while being transmitted through the transmission path, the design points are the speed of reading cells from the receiving buffer and the fact that cell order inversion does not occur during reading.

There is a way to have only one common receive buffer for all rings. As described above, the cells addressed to the own terminal station may arrive at the time interval τ corresponding to the phase difference between the rings, which is the minimum interval. That is, if the arriving cells are written in the common reception buffer within τ time, the arriving cells can be written without omission, and the order of the transmitted cells is guaranteed. However, the writing speed of the cell in this case needs to be 1 / τ, that is, a high speed corresponding to (single ring transmission speed × parallel ring number n).

The Kobayashi et al. Patent was made from the perspective of reducing the cell write rate to a single ring transmission rate while maintaining the order of transmitted cells. In this method, the cell write speed is reduced to a single ring speed by temporarily accumulating cells addressed to the own terminal station in a ring-compatible individual reception buffer and writing the cells again in the reception common buffer.

On the other hand, when only the cells addressed to the own terminal station are accumulated in the individual reception buffer, the position information of the cells addressed to the other terminal station or transmitted through the transmission path is lost. Therefore, when the cells are read from the individual reception buffer and the cells are written to the common reception buffer, if the cells are simply read cyclically and written, the order inversion may newly occur. To prevent this, create a receive buffer read control table that stores the arrival positions of cells addressed to the own station and other cells separately from the individual receive buffer, and refer to the contents of this table to create an individual receive buffer. The contents are read out and stored in the common reception buffer.

The above operation will be described with reference to FIGS. 8 and 11. 8, the same numbers as those in FIG. 7 indicate the same components, 23 is a cell assembling unit, 24 is a data output unit, 27 is a cell output control unit, 41 is an individual receiving buffer,
Reference numeral 45 is a reception buffer read control table. The reception unit 12 includes a cell extraction unit 26, a reception buffer 41, a cell output control unit 27, a cell assembly unit 23, a data output unit 24,
It has a reception buffer read control table 45.

FIG. 11 shows the status of slots in the ring-shaped transmission path that has arrived at the receiving section, the relationship between the individual reception buffer 41 into which the cell addressed to the local terminal is input, and the reception buffer read control table 45. In the upper diagram of FIG. 11, “empty” is an empty slot, “closed” is a slot containing a cell having a destination other than the destination end station, and 1 to 20 are slots containing a cell addressed to the destination end station. Show. Only the cells addressed to the own terminal station are written in the individual reception buffer 41. on the other hand,
In the reception buffer read control table 45, for example, "0" is written in the "empty" slot and the "closed" slot, and "1" is written in the cell addressed to the own terminal station.

A cell is read from the individual reception buffer 41 and written in a common reception buffer (not shown),
At this time, only when the content of the reception buffer read control table 45 is “1”, the content at the beginning of the corresponding individual reception buffer 41 is read and written in the common reception buffer. First, referring to the first column of the reception buffer read control table 45, nothing is read because the first and second rows are 0, and the corresponding cell "1" is read for the first time after the third row becomes 1. , Write to common receive buffer.
Next, the contents become 1 in the 5th and 6th lines, and the corresponding cells "2" and "3" are read and written in the common reception buffer. The 7th row is 0, and at this time, the 1st column of the reception buffer read control table 45 is cleared. Next, referring to the second column, the first and second rows of the second column are 1, and the corresponding cells “4” and “5” are read and written in the common reception buffer.

By repeating the above operation, cells can be read from the individual reception buffer and written in the common reception buffer while maintaining the correct cell order.

[0023]

In the prior art, cell inversion does not occur in the process of reading cells from the transmission buffer, but on the other hand, the cell read rate is n times the single link transmission rate (parallel link number times). ) Has a drawback that it must be a high speed equal to.

It is an object of the present invention to provide a transmitter in a multi-link transmission control device which does not cause cell order inversion and can reduce the cell read speed from the transmission buffer.

[0025]

In order to achieve the above object, the cell transmitter of the present invention is a multi-link communication device comprising a plurality of links, and the number of transmission buffers B1, ... , Bn, the cells input from the terminal are cyclically entered according to the input order of the cells, such as B1, ..., Bn, B1 ,.
And means for storing at a speed equal to the link transmission speed, and B1 from the transmission buffer when an empty slot is acquired in any one of the plurality of links.
.., Bn, B1, ... Cyclicly reading cells in sequence at a rate equal to a single link transmission rate, and putting the cells in the acquired empty slots in order and transmitting It is characterized by that.

In a multi-link communication device composed of a plurality of links, a number of transmission buffers B1, ..., Bn equal to the total number n of links are provided for each link.
A means for storing cells from the terminal in all transmission buffers at a rate equal to a single link transmission rate according to the input order of the cells, and when a vacant slot is acquired in one of the multiple links. Reads a cell from the transmission buffer corresponding to the link at a rate equal to the link transmission rate, transmits the cell in the acquired empty slot, and transmits the same cell as the cell in the transmission buffer corresponding to a link other than the link. It is characterized in that a means for discarding the numbered cell is provided.

Preferably, 1 is written in the receiving unit side when the received slot is addressed to the own station, and 0 is written when the received slot is empty or the destination is not the own station.
And a means for cyclically checking the inside of the table from the 1st link to the nth link, and the value of the table is 0. In the case of 1, the value is simply read, and in the case of 1, it corresponds to the read position.
Means is provided for reading the contents of the next reception buffer and storing it in the secondary reception buffer corresponding to the source address according to the source address.

[0028]

By using the present invention having the above-described structure, in the transmission section of the multilink transmission control device in the transmission station, the transmission buffers B1, ... Cells are cyclically stored in order at a rate equal to one link transmission rate. Alternatively, in the transmission unit of the multilink transmission control device in the transmission station, all transmission buffers B1, ...
..., Store in Bn in order at a rate equal to the single link transmission rate.

When an empty slot is acquired in any one of the plurality of links, cells are transferred from the transmission buffer to a single link transmission rate such as B1, ..., Bn, B1 ,. It is cyclically read at a speed equal to, and is sequentially inserted into the acquired empty slots and transmitted. Alternatively, when an empty slot is acquired in any one of a plurality of links, cells are read from the transmission buffer corresponding to the link at a speed equal to a single link transmission speed and placed in the acquired empty slot. The cell having the same cell number as the cell in the transmission buffer other than the link is discarded.

Therefore, the present invention can reduce the cell read rate from the transmit buffer to a rate equal to a single link transmission rate without causing cell reversal at the transmitting station.

[0031]

Embodiments of the present invention will be described in detail below with reference to the drawings. In the present embodiment, an example of a multi-ring communication network having a ring configuration is described, but the same can be applied to a non-ring communication network.

(First Embodiment) The operation of the transmitter 11 will be described with reference to FIG. In FIG. 1, 13a and 13b are data input sections, 14a and 14b are cell disassembly sections, and 15a and 15b.
Is a terminal transmission buffer corresponding to each transmission data, 80 is a transmission bus, 90 is a transmission bus control unit, 16 is a transmission buffer B
1, transmission buffer B2, transmission buffer B3, transmission buffer B4, transmission buffer B5, transmission buffer B6, transmission buffers B7, 17 are gates, 50 is a cell transmission control unit, 2
5 is a cell transmission unit.

The transmission unit 11 includes data input units 13a and 13
b, cell disassembling units 14a and 14b, terminal transmission buffer 15
a, 15b, a transmission bus 80, a transmission bus control unit 90, a transmission buffer 16, a gate 17, a cell transmission control unit 50, and a cell transmission unit 25.

A case where two terminals are connected to a terminal station which is a transmitting station will be described as an example. In the terminal station which is the transmitting station, the multi-link transmission control device 10 has the data input unit 1
The transmission data 102 input to 3a and 13b are decomposed into short partial data such as 1 to 6 in the cell disassembling units 14a and 14b, respectively, in the same manner as shown in the example of FIG. After that, each of the empty block identification bits 10
5, a destination address 106, a source address 107, a data identifier 108 for distinguishing from other data, and a cell number 1 for identifying what number cell of one data
A header 104 having 09 is added to create a cell 103 having a 1-slot length. These cells 103 are stored in the terminal transmission buffers 15a and 15b in the order of creation. The above operation is exactly the same as that of the prior art.
There is also a system using a fixed-length slot such as an ATM (asynchronous transfer mode) transmission method in which a bit such as a destination address, a source address, or a space identification information is not clearly provided. VP for these systems
By referring to I (virtual path identifier) or VCI (virtual channel identifier), it is possible to use the address or free / busy identification information.

The transmission bus control circuit 90 sequentially polls the terminal transmission buffers 15a and 15b and gives the access right of the transmission bus 80 to the transmission buffer in which cells are accumulated. If cells are staying in both buffers,
In order to prevent signal collision on the bus, for example, the transmission right is initially given only to the terminal transmission buffer 15a. During this time, all cells are retained in the terminal transmission buffer 15b. When all the cells of the terminal transmission buffer 15a have been read, the transmission bus control circuit 90 now grants the terminal transmission buffer 15b access to the transmission bus 80 and reads all the cells of the terminal transmission buffer 15b. After that, this operation is repeated.

Next, an example of a procedure for storing the cells read on the transmission bus 80 in the transmission buffer 16 (B1, B2, ... B7) will be described. Transmission bus control circuit 90
Is the transmission buffer 16 (B1, B2, ... B) when the multilink transmission control device 10 is first turned on.
7) Reset. Thereafter, the transmission bus control circuit 90 controls the transmission buffer 16 and the gate 17 in front of the transmission buffer 16 so that the cells read on the transmission bus 80 are stored in the transmission buffer B1 according to the order of reading. , B2, ..., B7, B1, B2 ...
・ ・ Stores cyclically as in. For convenience of explanation, the integer m
Is represented by MOD (m, n). As a specific method of the above procedure, a cell sequence in which the cell number 109 (m) of the cell 103 is divided by the total number of parallel links 7 (n) and the remainder is 0, that is, MOD (m, n) =
A sequence of 0 is B1, a cell sequence of MOD (m, n) = 1 is B2, a cell sequence of MOD (m, n) = 2 is B3, and MOD (m, n) = 3. Cell sequence is B
4, a cell sequence with MOD (m, n) = 4 is B5, MO
A cell sequence in which D (m, n) = 5 is B6, MOD (m,
There is a method of storing a cell sequence with n) = 6 in B7. That is, this is a method of storing the cell of cell number m in the MOD (m, n) +1 (1) th transmission buffer. In general, the total number of cells from one terminal is not always an integer multiple of the number of parallel links n. Therefore, the number k of the buffer storing the last cell corresponding to this terminal is stored and the cell number is stored. The cell of m may be stored in the MOD (MOD (m, n) + k + 1, n) (2) th buffer. Expression (1) corresponds to the case of k = n.

By storing the cells as described above, the transmission buffers B1, B2, B3, B4, B5, B are stored.
Since cells can be input to the buffer even while cells are being read from 6 and B7, it is not necessary to wait until all cells are read, and efficiency can be improved.

The receiving unit 12 (not shown) extracts the circulating slot 101 by the cell extracting unit 26 and checks whether it is an empty slot or a busy slot which has already been used with a cell. In the case of a busy slot, the destination address of the cell stored in that slot is further checked to see if it is the cell addressed to the own terminal station. In the case of a slot containing a cell addressed to its own terminal station, reception operation is performed, and the slot is changed to an empty slot and transferred to the transmission unit 11. The received empty slots and slots containing cells other than those addressed to the own terminal station are transferred to the transmission unit 11 as they are. At the time when the receiving unit checks the free / busy identification bit or the destination address of the cell, the transmitting unit 11 can know to which ring the vacant slot circulates. Therefore, the cell transmission control unit 50 is a transmission buffer B1, B2, B3, B
Cells 103 stored in 4, B5, B6 and B7
Are cyclically taken out according to the order in which the cells are stored in the transmission buffer, are inserted into the empty slot 101, and are transmitted.

With the above configuration, if the rate at which cells are taken out from the transmission buffer is set equal to the transmission rate for a single link, even if empty slots are consecutively acquired in adjacent links, all slots can be acquired. The empty slot can be used without lowering the transmission efficiency.
That is, if the number of parallel links is n, it is possible to equivalently realize the case of transmitting cells to a system having a transmission speed n times the speed of a single link. This operation will be described in more detail with reference to FIG.

FIG. 2 shows an example in which cells from two terminals are stored in the transmission buffers B1, B2, B3, B4, B5, B6 and B7. As an example, the total number of cells of each terminal is 15
There is. The cell number shown in FIG. 2 is (terminal number-
Cell number). In FIG. 2, the time interval between adjacent slots is τ, and after the slot 101 reaches the receiving unit 12 of the multilink transmission control device 10 of the receiving station and the receiving operation is performed, the transmitting unit 11 of FIG. It is assumed that the vehicle arrives in the state shown in the upper row. “Empty” described in the slot 101 of FIG. 2 is an empty slot (a slot in which the empty / closure identification bit 105 is empty),
The "block" represents the slot 101 in which the cell 103 not addressed to the multilink transmission control device shown in FIG. 2 is contained.

Further, in order to simplify the explanation, the slot 101 (S1) of the ring 01 shown in FIG.
When the cell arrives at 5, cells from all terminals have been input to the transmission buffer, and it is assumed that cells are taken out from the transmission buffer for the first time from this point.

The slot 1 is provided in the cell sending unit 25 of the ring 01.
When 01 (S1) arrives, this slot 101 is “closed”, and the cell transmission control unit 50 passes this slot as it is. Next, slot 101 of ring 02
(S1) arrives at the cell transmission unit 25. This slot 1
01 is also “closed”, and the cell transmission control unit 50 allows this slot to pass through as it is. Then ring 03 slot 1
01 (S1) arrives at the cell transmission unit 25. This slot 101 is “empty”, and the cell transmission control unit 50 reads the first cell 1-1 of the transmission buffer B1 at a speed equal to the link transmission speed, and inserts it into this slot for transmission.

Next, the slot 101 of the ring 04 (S1)
Arrives at the cell transmission unit 25. This slot 101 is “closed”, and the cell transmission control unit 50 allows this slot to pass through as it is.

Next, the slots 101 (S1) sequentially arrive at the cell transmission units of the rings 05 and 06. Each slot 101 is “empty”, and the cell transmission control unit 50 links the leading cell 1-2 stored in the transmission buffer B2 and the leading cell 1-3 stored in the transmission buffer B3. The data is read at a rate equal to the transmission rate, and the slot 101 (S
1) and slot 101 (S1) in ring 06
Insert each slot into and transmit. Thereafter, every time a slot that is “empty” is acquired, the transmission control unit 50
Reads a cell cyclically from the transmission buffer, inserts it into the empty slot and transmits.

Now, consider the time when the cell 1-7 is about to be input to the slot 101 (S2) of the ring 03. At this point, cells 1-2 to 1-6 are all being stored in the corresponding empty slots. Since the cell read rate is the same as the single link transmission rate, when the empty slot 101 is acquired at the time S2 in the ring 03, the reading of the cell 1-1 is just finished. Therefore, the transmission control unit 50 can read the next cell 1-7 from the transmission buffer B7, insert the cell in the slot 101 (S2) acquired in the ring 03, and transmit.

In this case, the minimum interval of empty cells acquired is τ. On the other hand, considering that the cell length is (τ × n), if a 7 × 7 non-blocking switch (generally, an n × n non-blocking switch) is used for the cell transmission control unit 50, no collision occurs and the acquisition is obtained. All the cells that have been used can be used.

FIG. 3 shows the state of the slots when they are sent to the transmission line. That is, it can be seen that all slots are used without waste, and this multi-link communication device is equivalent to a system having a transmission rate n times the link transmission rate.

For the terminal transmission buffers 15a and 15b and the transmission buffer 16 in the first embodiment, a normal FIFO memory shown in FIG. 5 described later can be used.

(Second Embodiment) The second embodiment is similar to that of FIG. 1, but the operation is different. The operation of decomposing the data input from the terminal into cells and placing them on the transmission bus 80 is exactly the same as in the case of the first embodiment, so description thereof will be omitted.

Next, the cells read on the transmission bus 80 are transferred to the transmission buffers B1, B2, B3, B4, B5, B.
6, an example of a procedure of storing in B7 will be described. The transmission bus controller 90 transmits the transmission buffers B1, B2, B3, B4, and B when the multilink communication device is first powered on.
5, B6, B7 are reset. Thereafter, the transmission bus control circuit 90 controls the transmission buffers so that the cells are sequentially arranged in all the transmission buffers B1, B2, B3, B4, B5, B6, and B7 according to the order of the cells read on the transmission bus 80. Store.

FIG. 4 shows an example in which cells from two terminals are stored in the transmission buffers B1, B2, B3, B4, B5, B6 and B7. As an example, the total number of cells of each terminal is 11
There is. The cell number shown in FIG. 4 is (terminal number-
Cell number). 4, the slot 101 arrives at the receiving unit 12 of the multilink transmission control device 10 of the receiving station at a time interval as shown in FIG. 9, and the slot is sent to the transmitting unit 11 after receiving operation. It is assumed that the vehicle arrives in the state shown in the upper row. "Empty" described in the slot 101 of FIG. 4 is an empty slot (a slot in which the empty / encapsulation identification bit 105 is empty),
The "block" represents the slot 101 in which the cell 103 not addressed to the multilink transmission control device shown in FIG. 4 is contained.

Further, to simplify the explanation, it is assumed that all cells from the terminal are stored in the transmission buffer 16 at the time of slot 101 (S1) of the ring 01 shown in FIG. It is assumed that cells are taken out from the buffer.

The slot 1 is provided in the cell sending unit 25 of the ring 01.
When 01 (S1) arrives, this slot 101 is “closed”, and the cell transmission control unit 50 passes this slot as it is. Next, slot 101 of ring 02
(S1) arrives at the cell transmission unit 25. This slot 1
01 is also “closed”, and the cell transmission control unit 50 allows this slot to pass through as it is. Then ring 03 slot 1
01 (S1) arrives at the cell transmission unit 25. This slot 101 is "empty", and the cell transmission control unit 50 reads the first cell 1-1 of the transmission buffer B3 at a rate equal to the link transmission rate, and inserts it into this slot for transmission. At the same time, a transmission buffer B other than the transmission buffer B3
Cell 1 at 1, B2, B4, B5, B6 and B7
Discard -1.

Next, the slot 1 is provided in the cell sending portion of the ring 04.
01 (S1) arrives. This slot 101 is "closed"
Therefore, the cell transmission control unit 50 allows this slot to pass through as it is. Next, slot 101 of ring 05 (S1)
Arrives at the cell transmission unit 25. Slot 101 is "empty"
Therefore, the cell transmission control unit 50 reads the first cell 1-2 stored in the transmission buffer B5 at a rate equal to the link transmission rate, and the slot 101 in the ring 05 is read.
It is inserted in (S1) and transmitted. Send buffer B at the same time
The cells 1-2 in the transmission buffers B1, B2, B3, B4, B6 and B7 other than 5 are discarded. However, at this time, the cell 1-1 is still being read from the transmission buffer B3, and as shown in the description of the FIFO described later, in order to read the bits of the cell 1-1 in order, the output enable signal and the data are read. S to shift
The operation of alternately inputting the hit Out signal to the transmission buffer B3 is repeated for the number of bits of the cell. Therefore, it is necessary to pay attention to the timing of discarding the cells 1-2 in the transmission buffer B3. That is, considering the operation of the FIFO memory, it is sufficient to accurately input the Shift Out signal input after reading an appropriate bit of the cell 1-1 to all the selective reset terminals corresponding to the cell 1-2. Alternatively, in order to simplify the processing, after reading the last bit of the cell 1-1, the
When the t Out signal is input, that is, the ring 03
It is also possible to perform the same operation at the time of S2 in. In the latter method, it is necessary to discard all five cells of cell 1-2 to cell 1-6 in the example shown in FIG.

Similarly, every time the slot which is "empty" is acquired, the transmission controller 50 reads the cell from the transmission buffer provided in the ring which acquired the empty slot,
It is inserted into the empty slot and transmitted. At the same time, the corresponding cell stored in the transmission buffer provided in the other ring is discarded.

Also in this case, the state of the slot when it is sent to the transmission line is as shown in FIG. That is, all slots are used without waste, and this multi-link communication device can realize a system equivalent to a system having a transmission rate n times the link transmission rate.

(FIFO capable of selectively resetting cells
Embodiment of Memory) Incidentally, a FIFO memory capable of selectively discarding cells can be used for the transmission buffer in the second embodiment. An embodiment of this FIFO memory will be described in detail below with reference to the drawings.

An example of the structure of the FIFO memory is described in Yoshikazu Yamamoto, Transistor Technology, March 1984, p.
For example, it is disclosed in "Usage and Configuration of FIFO Memory" on page 331. As an example, FIG. 5 shows a configuration example of a 4-bit FIFO memory. The operation principle of this FIFO memory will be shown below, and an embodiment of the FIFO memory which can be applied to the present invention and which can selectively discard cells will be described by modifying this.

In FIG. 5, the upper part is a 4-bit data register in which data is stored, and the lower part is a status register that indicates whether or not data is stored in the data register. For convenience of explanation, each terminal of the status register is named S, R, Q and QB as shown in the figure. If R is set to L for a certain period of time, Q = L, QB
= H and the status register is reset. This state indicates that no data is stored in the corresponding data register. On the other hand, when S is set to L for a certain fixed time, Q = H and QB = L, and the status register is set. This state indicates that data has been set in the corresponding data register.

The Master Clear signal is always H
Therefore, all the status registers can be reset by setting the Master Clear signal to L for a certain period of time. The Input Ready signal is the Q of the status register (204) closest to the input.
B, indicating whether or not the status register (204) is set. That is, Input Re
If ady = L, the status register (204) is set, and no more data can be input. If Input Ready = H, the status register (204) is reset and data can be input. Show.

When Input Ready = H, I
When nput Clock is input, the output of the gate 201 becomes L when the output Q of the F / F (217) becomes H. As a result, the gate 202 is opened and the data Di
Is read into the data register 203. On the other hand, as a result of the output of the gate 201 becoming L, the status register 20
4 is set and Q = H. The output is passed through the gate 205 which is open, and the output of the gate 205 is set to L. On the other hand, when the output of the gate 205 becomes L, the status register 204 is reset again and QB = L,
The gate 201 is closed. When the gate 201 is closed, its output becomes H, and the gate 2 passes through the inverter.
02 is closed and subsequent data input is prohibited. The above operation is performed in one clock.

With the above operation, the output of the gate 205 becomes L for a fixed time. As a result, the gate 207 is opened via the inverter, and the data is transferred from the data register 203 to the data register 208. On the other hand, the status register 206 is set and reset again after a fixed time, and as a result, the output of the gate 209 is set to L for a fixed time.

The above series of operations are repeated, and finally the data is written in the data register 212 and the status register 213 is set. At the next clock, the same operation is performed again, the status register 210 is set, and the corresponding data is transferred to the data register 2
16 is written. The above operation is repeated one after another.

Next, the operation of outputting data from the FIFO memory will be described by taking the case where data is set in the data registers 216 and 212 as an example. First, in order to output the data of the data register 212, a signal for a certain time L is given to the output Enable. At this point, the status register 213 is set, so the NAND gate 211 is closed and its output is L. Therefore, the gate 214 is closed via the inverter, and the data register 21
Up to 6 data cannot be read. When the data in the data register 212 has been output, Sh
As the if Out signal, a signal that becomes L for a certain period of time is input. As a result, the status register 213 is reset and the output of the gate 211 becomes L. As a result, the gate 214 is opened and the data in the data register 216 is transferred to the data register 212 via the inverter. On the other hand, since the output of the gate 211 becomes L, the status register 210 is reset and the final state is settled.

FIG. 6 shows an embodiment of a FIFO which can be applied to the present invention and which can selectively reset cells. For simplification of description, an example of a 4-bit length FIFO in which the data series Di is one series is shown, but in practice, it is used as a FIFO having a longer bit length made of a plurality of data series. It is common.

Consider the case where data is set in the data registers 212, 216 and 208 in accordance with the operation described above, so that the status register 204 is reset and the status registers 206, 210 and 213 are in the set state. It is assumed that a signal that becomes L for a certain period of time is added to the reset signal R3. This operation is basically the same operation as adding the Shift Out signal described above. In this state, the gates 214, 2
15, 207, 211 and 209 are closed, and the status register 210 is reset by adding R3. As a result, the gate 209 is opened and its output becomes L, so that the gate 215 is opened, the contents of the data register 208 are transferred to the data register 216, and the contents of the data register 216 are discarded. The status register 210 is also set after a certain time and its output closes the gate 209. As a result of the output of the gate 209 becoming L, the status register 206 is reset, the gate 205 is opened, and the gate 209 is opened.
Output becomes H again and settles in the final state. In this way, the cells stored in the data register 216 (cell length in this case is 1 bit) can be selectively discarded.

Since a cell is generally composed of a plurality of bits, in this case, all of the selection reset signals connected to each status register forming one cell are set to L.
Input the signal that becomes

[0068]

As described above, according to the present invention,
In a multi-link communication network composed of a plurality of link-like transmission lines, a single link transmission speed is obtained by transmitting a plurality of cells formed by decomposing one data using n link-like transmission lines. It is possible to equivalently realize a system having a transmission speed n times as high. On the other hand, there is an effect that the speed of reading cells from the transmission buffer can be maintained at a low speed equal to the link transmission speed.

Further, in the cell transmitting apparatus according to claim 1,
The cells input from the terminal are cyclically stored in the transmission buffer according to the input order of the cells, which is advantageous in that the amount of the transmission buffer can be small. Are stored in all transmission buffers according to the input order of the cell, and when an empty slot is acquired in any of the multiple links, cells are acquired from the transmission buffer corresponding to the link Since the data is put in the slot for transmission, the cell transmission control unit does not need an n × n switch, and the configuration of the cell transmission control unit can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multi-link transmission control device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of a transmitting unit in the first embodiment.

FIG. 3 is a diagram illustrating a situation of cells transmitted from a transmission unit to a transmission line in the first and second embodiments.

FIG. 4 is a diagram for explaining an operation of a transmitting unit in the second embodiment.

FIG. 5 is a diagram for explaining the operation of a normal FIFO memory.

FIG. 6 is a diagram for explaining an operation in an embodiment of a FIFO memory that can be selectively reset.

FIG. 7 is a diagram showing an overall configuration of a ring-shaped multilink communication network.

FIG. 8 is a configuration diagram showing a conventional multilink transmission control device.

FIG. 9 is a diagram showing an array of slots that continuously circulate on a ring and a phase relationship of slots between rings.

10 is a diagram showing the relationship between data and cells input to the data input unit 13 of the multilink transmission control device 10. FIG.

FIG. 11 is a diagram illustrating an operation of a receiving unit of a multilink transmission control device in the related art.

[Explanation of symbols]

01 to 07 ring-shaped transmission line 10 multi-link transmission control device installed in terminal station 11 transmission unit of multi-link transmission control device 12 reception unit of multi-link transmission control device 13, 13a, 13b data input unit 14, 14a, 14b Cell disassembly unit 15, 15a, 15b Terminal transmission buffer corresponding to each transmission data 16 Transmission buffer B1, transmission buffer B2, transmission buffer B3, transmission buffer B4, transmission buffer B5, transmission buffer B6, transmission buffer B7 17 AND gate 23 Cell assembly unit 24 Data output unit 25 Cell transmission unit 26 Cell extraction unit 27 Cell output control unit 41 Reception buffer 45 Reception buffer read control table 50 Cell transmission control unit 60 Transmission access control unit 70 Reception access control unit 80 Transmission bus 90 Transmission bus Control unit 101 Slot 102 data 103 cell 104 header of cell 103 105 open / close identification bit of cell 103 106 destination address of cell 103 107 source address of cell 103 108 data identifier of cell 103 109 what number part of the data 102 the cell 103 is Cell numbers 201 to 216 NAND gate 217 flip-flop

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H04Q 3/00 (72) Inventor Yoshinao Sueyoshi 1-6 Uchiyukicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Within the corporation

Claims (4)

[Claims] 1. Information capable of identifying a destination and a transmission source,
A header including information capable of identifying whether the slot is empty or not, and a fixed-length slot composed of data, a first link,
2nd link and nth (where n is any integer)
To each link, a transmission section that continuously transmits the phases of the slots in each link so that they are all different from each other within a range where the total phase difference between the links is within one slot length, and a slot from the transmission section. Received in order on each link, inspecting the open / close identification information of the slot. If the open / close identification information is closed, the destination address is inspected. And send it to
1 for each transmission line that receives the cell of the contents of the slot
In a cell transmission device comprising a receiving unit for storing in one provided primary reception buffer, the transmitting unit side is provided with a number of transmission buffers B1, ..., Bn equal to the total number n of links, Means for cyclically storing the input cells according to the input order of the cells such as B1, ..., Bn, B1, ... And at a rate equal to a single link transmission rate; When an empty slot is acquired in any one of the links, the transmission buffer B1, ...
, Bn, B1, ... Cyclically, cells are sequentially read at a rate equal to a single link transmission rate, and the cells are sequentially placed in the acquired empty slots and transmitted. A cell transmission device characterized by being provided. 2. A slot for writing 1 to the receiving side when the received slot is addressed to the own station, and 0 when the received slot is empty or the destination is not the own station. And a means for cyclically checking the inside of the table from the 1st link to the nth link, and when the value of the table is 0, simply 2. A means for reading out the value and, in the case of 1, reading out the content of the primary reception buffer corresponding to the read position and storing it in the secondary reception buffer corresponding to the transmission source address according to the transmission source address. The cell transmission device described. 3. Information capable of identifying a destination and a transmission source,
A header including information capable of identifying whether the slot is empty or not, and a fixed-length slot composed of data, a first link,
The phase of the slot in each link between the second link and the nth link (where n is an arbitrary integer)
Transmitters that transmit continuously so that they are all different from each other within a range where the total phase difference between links is within one slot length, and slots from these transmitters are sequentially received on each link and the slots are vacated. The identification bit is inspected, and if the empty identification bit is closed, the destination address is inspected. If the address is addressed to itself, the slot is emptied and sent to the link, and the contents of the slot (cell) In a cell transmission device comprising a receiving unit for storing in a primary reception buffer provided for each transmission line that has received, the number of transmission buffers B1 equal to the total number n of parallel links in the transmission unit, .., means for storing Bn corresponding to each link and storing cells from terminals in all transmission buffers at a rate equal to a single link transmission rate according to the input order of the cells, When an empty slot is acquired in any one of the links, a cell is read from the transmission buffer corresponding to the link at a rate equal to a single link transmission rate, and the cell is placed in the acquired empty slot and transmitted. And a means for discarding a cell having the same cell number as the cell in a transmission buffer corresponding to a link other than the link. 4. A slot for writing 1 to the receiving unit when the received slot is addressed to the own station, and 0 when the received slot is empty or the destination is not the own station. And a means for cyclically checking the inside of the table from the 1st link to the nth link, and when the value of the table is 0, simply 4. A means for reading the value and, in the case of 1, reading the content of the primary reception buffer corresponding to the read position and storing it in the secondary reception buffer corresponding to the transmission source address according to the transmission source address. The cell transmission device described.