JPH07326935A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor integrated circuit device that eliminates the influence of common impedance due to load fluctuation by devising the grounding position of a transistor. In a semiconductor integrated circuit device incorporating an amplifier circuit, the ground terminal of an input resistor Ri of an input-stage transistor is connected to a reference voltage that does not contact the semiconductor substrate, and the input circuit unit, the output circuit unit, and other circuits are connected. The ground end is configured to connect to a ground line in contact with the semiconductor substrate. [Effect] Since the ground line that is in contact with the semiconductor substrate is completely separated, the circuit operation is stable without being affected by the parasitic current flowing through the semiconductor substrate. Further, the distortion of the amplifier circuit is improved without being affected by the common impedance due to the ground resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which an amplifier circuit is incorporated on a semiconductor chip, and more particularly to a semiconductor integrated circuit device in which a ground potential portion (ground portion) of an input resistance portion is improved in grounding location. is there.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit device will be described with reference to FIGS. 2 is a circuit block diagram showing a conventional semiconductor integrated circuit device, and FIG. 3 is a schematic diagram showing an example of a ground structure of the conventional semiconductor integrated circuit device shown in FIG.

First, the configuration of a conventional semiconductor integrated circuit device will be described with reference to FIG. Reference numeral 1 indicates a semiconductor integrated circuit device showing a part of the internal configuration. Generally, the semiconductor integrated circuit device 1 is configured to include an input terminal 6, an output terminal 7, a ground terminal 8, a power supply terminal 9 (hereinafter simply referred to as “power supply”), and the like.

The input terminal 6 is connected to the base of an input transistor 11 which constitutes the input circuit section 2. The base of the input transistor 11 is connected to the ground terminal 8D via the input resistor 10 and the collector thereof is connected to the power supply 9A. , And the emitters thereof are respectively grounded to the ground terminal 8E via the constant current circuit 12. The constant current circuit 12 connected to the emitter of the input transistor 11 sets appropriate operating conditions for the input transistor 11.

The output terminal 13 of the input circuit section 2 is connected to the input of the driver circuit section 3, and the driver circuit section 3 is grounded to the ground terminal 8G. The output side of the driver circuit section 3 is connected to the input end 14 of the output circuit section 5. This output circuit section 5 is normally used for the purpose of obtaining a high-performance output and for the reason that the configuration of the semiconductor integrated circuit device 1 is easy and the like.
The so-called quasi-complementary push-pull circuit configuration, which is composed of 5 and the composite PNP-NPN Darlington circuit 16, is adopted.

The base junction of the composite NPN-NPN Darlington circuit 15 and the composite PNP-NPN Darlington circuit 16 is the input terminal 14 of the output circuit unit 5, and the collector of the composite NPN-NPN Darlington circuit 15 is connected to the power supply 9C. Connected, the emitter of the composite PNP-NPN Darlington circuit 16 is grounded to the ground terminal 8J, and the junction between the emitter of the composite NPN-NPN Darlington circuit 15 and the collector of the composite PNP-NPN Darlington circuit 16 is the output terminal 7. It is connected to the. Furthermore, this semiconductor integrated circuit device 1 is provided with a reference voltage generator 4, which is connected to a power supply 9B and grounded to a ground terminal 8H.

Next, the operation of the semiconductor integrated circuit device 1 having such a configuration will be described. The electric resistance input from the input terminal 6 is received by the input resistor 10 connected to the base of the input transistor 11, and the impedance matching of the input transistor 11 is measured. The electric signal processed by the input circuit unit 2 is input to the driver circuit unit 3 via the output terminal 13 of the input circuit unit 2. The driver circuit 3 plays a role of giving sufficient electric signal energy to the output circuit section 5 at the final stage. Specifically, an appropriate bias is supplied to the output circuit unit 5, and the output circuit unit 5 is controlled by phase tuning and impedance matching.

The reference voltage generating section 4 generates a stable voltage against various voltage fluctuation factors based on the power source 9B, supplies voltage to necessary circuit sections in the semiconductor integrated circuit device 1, and External Vref terminal 17 (Voltage
Output as Reference). The reference voltage generator 4 is also considered in terms of temperature characteristics. For example, the temperature T = −55 to +12 for a voltage of 5 V at the power supply 9.
It is designed so that a stable DC reference voltage of Vref = 1.234 to 1.238 V can be obtained in the range of 5 ° C.
The reference voltage generated by the reference voltage generator 4 is +
-In the case of a power supply, it may be possible to output 0 V, which is the midpoint voltage. Further, the reference voltage generator 4 can be used as an extremely stable ground terminal having a low impedance in AC. The gist of the present invention is that the output of the reference voltage generator 4 that can be used as a ground terminal for AC is used as a ground terminal. The output circuit section 5 current-amplifies the input from the driver circuit section 3.

Next, the ground structure of the semiconductor integrated circuit device 1 will be described. When a circuit section that handles a large current, such as the output circuit section 5, is integrated on a semiconductor chip, it is necessary to pay particular attention to the arrangement of the ground terminal. That is, the ground terminal 8J of the output circuit unit 5, the ground terminal 8D of the input resistor 10, the ground terminal 8E of the input transistor 11, the ground terminal 8F of the input circuit unit 2, the ground terminal 8G of the driver circuit unit 3, and the reference voltage generation. When all the ground terminals 8H of the section 4 are connected to the common ground line (not shown), the common ground line has a slight resistance component, that is, a common impedance. Therefore, a large operating current of the output circuit section 5 flows through this common impedance to raise the potential, and is fed back to the input circuit section 2 through the common ground line.
Adversely affects noise. Therefore, a configuration is known in which the ground lines of the input circuit section 2 and the output circuit section 5 are separated. The two examples will be introduced below.

First, in the first structure, as is well known, the second ground line (not shown) connected to the IC substrate (semiconductor substrate) via the PN isolation region is grounded to the output circuit section 5. Ground terminal 8J. Then, a new first ground line (not shown) not connected to the substrate is provided, and the ground terminal 8 of the input resistor 10 is connected to the first ground line.
D, the ground terminal 8E of the input transistor, the ground terminal 8F of the input circuit section 2, the ground terminal 8G of the driver circuit section 3, and the ground terminal 8H of the reference voltage generation section 4 are all grounded,
The output circuit unit 5 is completely separated from the ground terminal 8J to avoid the influence of the output circuit unit 5. According to the first configuration, the potential increase of the second ground line due to the large operating current of the output circuit unit 5 is fed back to the first ground line by separating the first ground line and the second ground line. Since it does not exist, it is possible to prevent the above-mentioned adverse effect on the input circuit section 2 due to the potential increase. Further, the second ground line can also absorb the parasitic current generated by various factors such as the influence of the large operating current by the output circuit section 5.

However, in the method of grounding the ground terminal in the semiconductor integrated circuit device 1 according to the first structure, the second method described above is used.
Since the ground line is short, there are few portions that absorb the parasitic current flowing through the substrate, and the effect of stabilizing the potential of the substrate is insufficient. Therefore, the potential of the substrate of the semiconductor integrated circuit device 1 partially rises, which adversely affects the circuit operation. Further, if the second ground line connected to the substrate is extended in parallel with the first ground line, the instability of the substrate potential can be improved, but the chip size of the semiconductor integrated circuit device 1 increases. was there.

As a second structure for separating the ground line, which is devised for the purpose of mainly solving this problem, an actual fairness 5
The "semiconductor integrated circuit device" disclosed in the specification No. 26769 can be mentioned. The outline will be described again in FIG. The internal configuration of the semiconductor integrated circuit device 1 is the same as the circuit block showing the conventional semiconductor integrated circuit device shown in FIG. 2, the same reference numerals are used, and the description of those configurations is omitted. However, the difference from the circuit components of FIG. 2 is that the ground line connected to the substrate via the PN isolation region is the second ground line 22, and the ground line not connected to the substrate is the first ground line 21. That is the point.

An input resistor 1 is connected to the first ground line 21.
Only the 0 ground terminal 8D was grounded. Other than that, namely, the ground terminal 8E of the input transistor, the ground terminal 8F of the input circuit unit 2, the ground terminal 8G of the driver circuit unit 3, the ground terminal 8H of the reference voltage generation unit 4, and the ground terminal 8J of the output circuit unit 5. All are grounded to the second ground line 22, and the ground terminal 8D of the input resistor 10 is completely separated from the second ground line 22.

According to the second structure, the first ground line 21 and the second ground line 22 are separated from each other, so that the large operating current of the output circuit section 5 raises the potential of the second ground line 22 and the second ground line 22. It is stated that the rise in the potential of the second ground line 22 due to the parasitic current collected by the ground line 22 can eliminate the adverse effect that the ground potential of the base terminal of the input transistor 11 has an adverse effect such as a voltage fluctuation.

[0015]

However, in the method of grounding the ground terminal in the semiconductor integrated circuit device according to the second configuration shown in FIG. 3, only the ground terminal 8D of the input resistor 10 of the input circuit section 2 is the first terminal. Since a slight ground resistance component of the first ground line 21 is connected to the ground line 21 and has a common impedance as in the first example, a large operating current of the output circuit unit 5 flows. Increase in potential of the second ground line 22 and the second ground line 2
The increase in the potential of the second ground line 22 due to the parasitic current collected by 2 is returned to the first ground line 21 via the common impedance, and there is a limit to completely removing the influence of the increase in the potential of the first ground line 21. However, there are drawbacks such that the input circuit section 2 and the entire circuit are adversely affected, and the distortion rate of the amplifier circuit is deteriorated. An object of the present invention is to solve the above-mentioned inconvenient points.

[0016]

In order to solve the above problems, the present invention provides a base input transistor, an input circuit section having an input resistance between the base of the base input transistor and a ground potential section (ground section), In a semiconductor integrated circuit device in which a reference voltage generating section for generating independent voltage and an output circuit section for current amplification are incorporated on the same semiconductor chip, a ground potential section (ground section) of the input resistor is connected to a ground line. The problem has been solved by adopting a configuration of connecting to the reference voltage generating unit which is not connected.

[0017]

The ground terminal 8D of the input resistor 10 connected to the base of the input transistor 11 is separated from the second ground line 22 so that the reference voltage generator 4 of the AC voltage has a low impedance and is an ideal ground line. By grounding to the reference voltage output line 20, it is possible to avoid an adverse effect such that the influence of a large operating current of the output circuit unit is fed back to the input circuit unit and electrically excites the input circuit unit or the entire circuit. It was possible to prevent the distortion rate of the amplifier circuit from deteriorating.

[0018]

Embodiments of the semiconductor integrated circuit device of the present invention will be described below with reference to FIG. FIG. 1 is a schematic view showing a ground structure of a semiconductor integrated circuit device of the present invention. The same parts as those in the schematic diagram showing an example of the ground structure of the semiconductor integrated circuit device shown in FIG. 2 and the conventional semiconductor integrated circuit device shown in FIG. The description of the configuration and the like is omitted.

The semiconductor integrated circuit device of the present invention has a structure in which the ground terminal 8 of the input transistor 11 is connected to the second ground line 22 connected to the substrate through the PN isolation region.
E, ground terminal 8F of input circuit unit 2, driver circuit unit 3
The ground terminal 8G, the ground terminal 8H of the reference voltage generator 4, and the ground terminal 8J of the output circuit unit 5 are all grounded. Further, a reference voltage output line 20 is newly taken out from the output of the reference voltage generating section 4 and made to exist as a dedicated wiring line. The reference voltage output line 20 is completely separated from the first ground line 21 and the second ground line 22, and only the ground terminal 8D of the input resistor 10 is grounded to the reference voltage output line 20. However, it is configured to be completely separated from the second ground line 22.

Since the reference voltage generator 4 is an ideal ground line with an AC low impedance, the ground terminal 8D of the input resistor 10 is connected to the reference voltage output line 20 of the reference voltage generator 4 (of course, The fact that the input resistance has a direct-current potential has been taken into consideration such as level shift.), So that the influence of the common impedance generated in the second ground line 22 can be eliminated. .

The present invention is not limited to the above embodiment, and various embodiments can be adopted. For example, it goes without saying that the present invention can be applied to a case where a differential amplifier (not shown) is used as the input amplifier and only one input of the differential amplifier is affected by the parasitic current.

[0022]

As described above, according to the semiconductor integrated circuit device 1 of the present invention, as in the method of grounding the ground terminal in the semiconductor integrated circuit device 1 of the second example shown in FIG.
The ground terminal 8D of the input resistor 10 of the input circuit unit 2 is the first
A common impedance generated in the ground line when grounded to the reference voltage output line 20 which is not grounded to either the ground line 21 or the second ground line 22 and extends completely separated from the ground line. The input circuit section 2 is not affected by the parasitic current collected by the input circuit section 2 and does not return an unnecessary electric signal component to the input circuit section 2.
Also, there is no adverse effect such as electrically exciting the entire circuit.

When the ground terminal 8D of the input resistor 10 of the input circuit section 2 is connected to the reference voltage output line 20, the common impedance due to the ground resistance of the first ground line 21 and the second ground line 22 is increased. Since the influence can be reduced, the influence of noise or the like fed back to the input circuit section 2 through the common impedance is reduced, and the distortion rate of the amplifier circuit is not deteriorated.

Further, generally, the place for absorbing the leakage current is set by connecting to the ground line through the isolation region of the substrate, but there is no restriction on the place for absorbing the leakage current, and it is necessary. It is possible to freely set the location to absorb the leakage current. Further, it is not necessary to newly provide a new ground line such as the first ground line 21, and the chip size of the semiconductor integrated circuit device 1 can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a ground structure of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a circuit block diagram showing a conventional semiconductor integrated circuit device.

FIG. 3 is a schematic diagram showing an example of a grounding structure of a semiconductor integrated circuit device of a conventional technique.

[Explanation of symbols]

 1 semiconductor integrated circuit device 2 input circuit section 3 driver circuit section 4 reference voltage generation section 5 output circuit section 6 input terminal 7 output terminal 8 ground terminal 8D input resistor ground terminal 8E input transistor ground terminal 8F input circuit ground terminal 8G Ground terminal for driver circuit 8H Ground terminal for reference voltage generator 8J Ground terminal for output circuit 9 Power supply 9A Power supply for input transistor 9B Power supply for reference voltage generator 9C Power supply for output circuit 10 Input resistance 11 Input transistor 12 Constant Current circuit 13 Output terminal 14 Input terminal 15 Complex NPN-NPN Darlington circuit 16 Complex PNP-NPN Darlington circuit 17 Vref terminal 20 Reference voltage output line 21 First ground line 22 Second ground line

Claims (1)

[Claims] 1. A base input transistor, an input circuit section having an input resistance between the base of the base input transistor and a ground potential section, a reference voltage generation section for generating an independent voltage, and an output circuit section for current amplification. A semiconductor integrated circuit device incorporated on the same semiconductor chip, wherein a ground potential part of the input resistor is connected to the reference voltage generating part.