JPH07302171A - Disk controller - Google Patents

Abstract

(57) [Summary] [Structure] In a disk control device, control information that has conventionally been centrally managed is stored in a distributed memory provided in each microprocessor. [Effect] By decentralizing the control information, the access bottleneck to the control information is eliminated and the performance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a disk system which enables high performance input / output operation.

[0002]

2. Description of the Related Art In a general computer system, data required by a high-order side such as a CPU is stored in a secondary storage device, and the CPU writes and reads data to and from the secondary storage device as needed. ing. A non-volatile storage medium is generally used as the secondary storage device, and typical examples thereof include a magnetic disk device (hereinafter referred to as a drive) and an optical disk. In such a secondary storage device, there is generally a disk control device (hereinafter referred to as DKC) that controls data transfer between a CPU and a drive.

An example of the disk control device will be described below. In the DKC 1, as shown in FIG. 7, the channel data control circuit (CDC) 5 and the drive data control circuit (DDC)
Data transfer is executed by 13. The channel data control circuit (CDC) 5 transfers data between the CPU and the cache memory 10 in the DKC 1, and the drive data control circuit (DDC) 13 transfers data between the cache memory 10 and the drive 12. The CDC 5, cache memory 10 and DDC 13 are connected to a common bus (DBS) 7 for data. Data transfer control in DKC1 is performed for each CD
Microprocessor for controlling C5 and DDC13 (M
P) It is carried out under the control of 6. Each MP6 is connected to a common bus (CBS) 8 for control signals.

As described above, each MP6 in the DKC1 has a multiprocessor configuration, and each MP6 efficiently uses shared resources such as the bus, the cache memory 10 and the drive 12 for smooth data transfer. Has been realized. As described above, in order for the MP6 to operate cooperatively, it is necessary to repeatedly refer to and update the control information in the control information memory (CM) 9 in the DKC1 via the CBS8. In the conventional DKC 1, the control information is thus collected in the CM 9 and collectively managed.

[0005]

In the conventional DKC1, since each MP6 operates in cooperation with each other, it is necessary to access the CM9 many times through the CBS8 in one input / output process. Therefore, if the number of MP6s in the DKC1 increases or the processing performance of MP6s improves in the future, CBS8,
There is a bottleneck between CM9.

[0006]

In order to solve the above problems, the present invention provides a distributed memory (DM) 11 in each MP 6 in a disk controller to distribute control information in a CM 9.

[0007]

When the DM11 is provided in each MP6 and the data in the CM9 is dispersed in this way, if the control information required by the MP6 exists in the DM11, the access to the CM9 is not necessary, so that the CBS8 and the CM9 are not required. The neck between is eliminated.

[0008]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows the structure within DKC1 of the present invention. As shown in FIG. 1, the DKC 1 sandwiches the cache memory 10 and the control information memory 9 and the clusters 0 and 1 are symmetrical.
The DKC 1 is composed of a data transfer system that actually transfers data between the CPU and the drive 12, and a control system that manages this data transfer. Since the clusters 0 and 1 have exactly the same configuration, the following description will be given for the cluster 0.

First, the data transfer system in the DKC 1 will be described. First, a data transfer method between the CPU and DKC1 will be described. The CPU and the DKC1 are connected by the channel path 3, and the channel path 3 is connected to the channel switch circuit 4 in the DKC1. The channel switch circuit 4 is a circuit that selects a maximum of four channel paths 3 that can operate simultaneously in the DKC 1 because a maximum of four channel paths 3 are selected. Each channel switch 4 has four channel data control circuits (C
DC) 5 is connected. The CDC 5 is connected to a data common bus (DBS) 7. The cache memory 10 is also connected to the DBS 7.

The data transferred from the CPU is CDC
Under the control of 5, the cache memory 1 passes through the DBS 7.
Stored in 0. Also, from the cache memory 10 to CP
When transferring data to U, conversely, cache memory 1
The data is read from 0 and transferred to the CPU through the DBS 7 under the control of the CDC 5. Thus, the CDC
A circuit 5 controls data transfer between the CPU and the DKC 1.

Next, a data transfer method between the DKC 1 and the drive 12 will be described. DBS7 has two drive data control circuits (DDC) in addition to CDC5 and cache memory 10.
13 is connected. The data transferred from the drive 12 is stored in the cache memory 10 through the DBS 7 under the control of the DDC 13. When storing data from the cache memory 10 to the drive 12, on the contrary, the data is read from the cache memory 10,
Drive 1 through DBS7 under the control of DDC13
2 is transferred. Thus, the DDC 13 is a circuit that controls data transfer between the CPU and the drive 12. As described above, in DKC1, CP is set by CDC5 and DDC13.
Data transfer between the U, the cache memory 10 and the drive 12 is performed.

Next, a control system for controlling the above data transfer will be described. Each cluster of DKC1 has 6 microprocessors (MPs) 6 respectively distributed memory (DM)
It is connected via 11 to a common bus (CBS) 8 for control signals. In addition, this CBS8 has a control information memory (C
M) 9 is connected. MP6 includes MPC that controls CDC5 and MPD that controls DDC13.

The MPC is a CDC 5 which is in charge of control.
The MPC refers to the control information, and instructs the CDC 5 to transfer data between the CPU and the cache memory 10 based on the reference result.

Specifically, as shown in FIG. 2, when a data write request is issued from the CPU to the DKC 1, the MPC that receives this request is the cache memory 1
Go to control information to see if data transfer to 0 is possible (15). At this time, the MP1 is DM1
It is checked whether or not the control information is stored in 1 (16). When the control information is stored in the DM 11 of the MPC (hit), the control information in the DM 11 is referenced (21).

Since the cache memory 10 can be used by referring to the control information, when the CBS 8 can be used (18), the MP1 registers the use of the cache memory 10 for the control information in the CM 9 (19). If the CBS 8 cannot be used at this time, wait until the CBS 8 becomes available (20), and register the use of the cache memory 10 in the control information in the CM 9 as soon as the bus becomes available (19). At this time, if the same control information is stored in the other DM 11, the MP1 for reference and registration invalidates the control information in the other DM 11 in which the same control information is stored (26). .

On the other hand, when the control information is not stored in the DM 11 of the MPC (miss), the MPC is C.
It is checked whether the BS 8 can be used (22). If the BS 8 is usable, the control information in the CM 9 is referred to. If the cache memory 10 is usable, the MPC in question responds to the control information in the CM 9 by the cache memory 10. Register the use of (23). If you cannot use CBS8, CB
Wait until S8 becomes available (24), and as soon as the bus becomes available, refer to the control information in CM9 for cache memory 1
When 0 is available, the MPC registers the use of the cache memory 10 for the control information in the CM 9 (2
3). At this time, when the same control information is stored in the other DM 11, the MPC that performs reference and registration invalidates the control information in the other DM 11 in which the same control information is stored.

In this way, after the use of the cache memory 10 is registered, the MPC reports the data transfer permission to the CPU. The CPU that has received the data transfer permission from the MPC transfers the data to the DKC 1. DKC1 is C
After receiving the data from the PU, the data is stored in the cache memory 10 according to the procedure described in the previous data transfer system.

Next, a case where the data thus stored in the cache memory 10 is stored in the drive 12 will be described. When the data stored in the cache memory 10 is stored in the drive 12, the control right is transferred from MPC to MPD. MPD also controls DDC13
Is determined, the MPD refers to the control information, and the cache memory 1 is referred to the DDC 13 based on the reference result.
0, data transfer between the drive 12 is instructed.

Specifically, data writing from the MPC to the drive 12 from the cache memory 10 is performed by the MPC.
The MPD requested by the CPU refers to the control information to check whether data transfer from the cache memory 10 to the drive 12 is possible. The control information referred to at this time is control information regarding the drive path 14 between the cache memory 10, the DKC 1, and the drive 12 and the usage status of the drive 12. First, the MPD checks whether or not the control information is stored in the DM 11 (16). The MPC
When the control information is stored in the DM 11 (hit), the control information in the DM 11 is referenced (21).

By referring to these control information, when the cache memory 10, the drive path 14 and the drive 12 are available and data can be transferred, if the CBS 8 is available (18), the MPD will be the control information in the CM 9. For the cache memory 10, drive path 14 and drive 12
Register the use of (19). If CBS8 cannot be used at this time, wait until CBS8 becomes available (2
0), as soon as the bus becomes available, the use of the cache memory 10, the drive path 14, and the drive 12 is registered in the control information in the CM 9 (19). At this time, when the same control information is stored in the other DM 11, the MP1 to be referred to and registered is the other DM 1 in which the same control information is stored.
The control information in 1 is invalidated (26).

On the other hand, when the control information is not stored in the DM 11 of the MPD (miss), the MPD is C
It is checked whether the BS 8 can be used (22). If it is available, the control information in the CM 9 is referred to. If the cache memory 10, the drive path 14 and the drive 12 are available, the MPD is stored in the CM 9. The use of the cache memory 10, drive path 14 and drive 12 is registered in the control information (23). If the CBS8 cannot be used, wait until the CBS8 becomes available (24),
As soon as the bus becomes available, the control information in the CM 9 is referred to. If the cache memory 10, the drive path 14 and the drive 12 are available, the MPD uses the cache memory 10, the drive path 14 and the drive for the control information in the CM 9. 1
Register the use of 2 (23). At this time, if the same control information is stored in another DM 11, the MPD to be referred to and registered is the other D that stores the same control information.
The control information in M11 is invalidated.

In this way, after the use of the cache memory 10, drive path 14 and drive 12 is registered, M
The PD instructs the DDC 13 to transfer data from the cache memory 10 to the drive 12. Upon receiving the data transfer instruction from the MPD, the DDC 13 transfers the data from the cache memory 10 to the drive. Data transfer to the drive 12 by the DDC 13 is performed according to the procedure described in the above data transfer system.

The operation of the control system for controlling data transfer in the case of writing data from the CPU to the DKC1 and in the case of writing data from the DKC1 to the drive 12 has been described. On the contrary, when the data is read from the drive 12 to the DKC1 and the data is read from the DKC1 to the CPU, the operation of the control system is CP
The operation of the control system for controlling data transfer when writing data from U to DKC1 and when writing data from DKC1 to drive 12 is the same.

In this embodiment, as described above, the control information in the DM 11 is for reference only. Among the control information, control information having a relatively high reference frequency is stored in the DM 11 in advance. When registering in the control information, C via CBS8
Performed on M9. This is because the control information is very important information in the DKC 1 and therefore is reliably managed in the CM 9. Therefore, it is desirable that the CM 9 be backed up by a battery so that the control information is not lost due to an accident such as a power failure, and that the CM 9 is duplicated. As described above, if the control information is backed up by the battery and is surely centralized in the duplicated CM 9, a volatile semiconductor memory may be used for the DM 11 and a single memory may be used.

(Embodiment 2) This embodiment shows an example in which the control information in the DM 11 can be dynamically changed. The configuration inside the DKC 1 in this embodiment is as shown in FIG. 1 as in the first embodiment, and the operation of the data transfer system is also the same as in the first embodiment. Therefore, the operation of the control system will be mainly described below with reference to FIG.

When it is necessary to refer to or register the control information in the MP6 (31), the MP6 first checks whether the control information exists in its DM11.
(32). If the control information is present in its own DM 11 (hit), whether or not to register the control information is recognized (33). MP6 is CB in case of registration
It is checked whether or not S8 can be used (34), and if it can be used, the CM 9 is registered (35). At this time, other DM
When the same control information is stored in 11, the MP1 to be registered has another D that stores the same control information.
The control information in M11 is invalidated (36). on the other hand,
If the CBS8 cannot be used, wait until the CBS8 becomes available (37), register the control information in the CM9 as soon as the bus becomes available (35), and store the same control information in the other DM11. If so, the MP1 to be registered invalidates the control information in another DM 11 in which the same control information is stored (36).

When it hits in its own DM11 (32) and the reference is made, the DM11 refers to the control information as in the first embodiment (38).

On the other hand, if the control information does not exist in the DM 11 of its own (miss), whether or not the control information is registered is first recognized as in the case of a hit (3).
9). If it is a registration, it is registered in the CM 9 as in the case of the hit (40), (41), (42), (43). If it is a reference, it is checked whether the CBS 8 can be used (44). If the CBS 8 is not usable, wait until the CBS 8 becomes available 4
8. CM9 or other MP6 DM1 if available
MP trying to refer to the control information referenced from 1
It is determined whether or not to hold it in DM 11 of 6 (4
5). If you want to keep it, CM9 or other MP6
The control information referenced from the DM 11 is stored in the DM 11 (46) and simultaneously referenced (47). If not held, the control information is only referenced (49) from the CM 9 or DM 11 of another MP6.

In this embodiment, if a mistake is made at the time of reference, C
Since the control information can be held in the DM 11 at the same time as referring to the control information from the M 9, it is possible to dynamically move the control information stored in the DM 11.

Also in this embodiment, as in the first embodiment, DM11
The control information inside is for reference only. When registering in the control information, it is carried out for the CM 9 via the CBS 8. CM
9 is preferably backed up by a battery so that the control information is not lost due to an accident such as a power failure, and moreover, it is preferable that the control information is duplicated. As described above, if the control information is backed up by the battery and is reliably centrally managed in the duplicated CM 9, the DM 11 uses a volatile semiconductor memory, and may be a single layer.

(Third Embodiment) FIG. 4 shows the internal structure of the DKC 1 in this embodiment. In this embodiment, each DM
11 has a non-volatile distributed memory (NDM) 30 backed up by a battery.
The feature is that registration can be performed for 0, and the other constituent elements are the same as in the first embodiment.

The operation of the control system of this embodiment will be mainly described below with reference to FIGS. In the second embodiment, when the DM 11 is missed, the control information is sent from the CM 9 to the DM 1 at the time of reference.
An example has been shown in which it is possible to retain the value of 1. In the present embodiment, this is further expanded so that the NDM 30 can be registered. This embodiment differs from the registration processing in FIG. Therefore, only the part of registration for which processing is different is shown in FIG. 5 and will be described below. Here, the process 51 of FIG. 5 is the process 33 of FIG.
In addition, the process 54 of FIG. 5 corresponds to the process 36 of FIG.

When it is necessary to refer to or register the control information in the MP6 (31), the MP6 first checks whether or not the control information exists in its DM11 (32). If the control information is present in its own DM 11 (hit), whether or not to register the control information is recognized (33). In the case of registration, the MP6 determines whether to register the control information in the NDM 30 (52).

A method of determining MP6 at this time will be described below with reference to FIG. As shown in the address map of FIG. 6, the control information in the DKC1 is managed by addresses in the memory space, and whether or not the control information can be decentralized depends on the characteristics of the control information.
How to decentralize is determined. aaa to b
The control information specified by the addresses up to bbb may be decentralized, but the control information needs to be non-volatile (non-volatile distributed control information). The control information designated by the addresses from bbbb to cccc may be distributed,
The control information does not need to be non-volatile (volatile distributed control information). The control information designated by the addresses from cccc to dddd is control information that should not be decentralized (decentralized control information). The non-volatile distributed control information is control information that is registered relatively continuously. The registered control information needs to be stored in a non-volatile memory because it is difficult to lose it due to a power failure or the like. In case of continuous access, if it is stored in DM11,
You do not need to refer to CM9 and register. Further, the volatilization / dispersion control information is control information that is relatively continuously referred to.
In this embodiment, the volatile dispersion control information is premised on having a copy of it in the CM 9.

Since the control information that is mainly referred to is rarely changed by registration, there is always a copy in the CM 9, and even if the control information stored in the volatile DM 11 is lost due to a power failure or the like, the CM 9 recovers it. it can. The non-distributed control information is control information that is frequently referred to and updated by many MP6s. In this way, if a large number of MP6s are frequently referred to and updated, another DM 11 or CM 9 is updated every time.
It is necessary to invalidate the same control information within. After being invalidated in this way, when another MP6 refers to and registers, a mistake is always made and the CM 9 must refer to the control information. As described above, the data that is frequently invalidated with respect to the other DM 11 or CM 9 is stored in the CM 9 and the centralized control is easier to control than the decentralized control, and the performance is good. In this way, the presence or absence of decentralization and the method are determined according to the characteristics of the control information.

MP6 follows this address map,
If the control information to be registered is the non-volatile distributed control information, it is determined that the control information is registered in the control information in the NDM 30, and the registration is performed (53). If it is the volatile dispersion control information, it is judged to be registered with respect to the control information in the DM 11, and it is registered (53). If it is the non-distributed control information, it is checked whether the CBS 8 can be used as in the first and second embodiments (55), and the CM 9 is registered (56).

On the other hand, in the case of registration even when there is a mistake, registration is performed as shown in FIG.

Also in this embodiment, as in the second embodiment, if a mistake is made at the time of reference, it is possible to refer to the control information from the CM 9 and hold it in the DM 11 or NDM 30 at the same time. At this time, as in the case of registration, according to the address map of FIG. 6, it is determined whether the information is non-volatile decentralized control information, volatile decentralized control information or non-dispersed control information.

In this embodiment, unlike the first and second embodiments, DM
11 or the control information in NDM 30 can be used for both reference and registration. Also, as in the first and second embodiments, CM9
It is desirable that the control data be backed up by a battery so that the control information will not be lost due to an accident such as a power failure, and that the control information will be duplicated. Further, it is desirable that the NDM 30 is also duplicated because the reliability is higher.

In the first and second embodiments, it is possible to use the address map shown in this embodiment to determine whether the control information is distributed control information. Also DM11 or ND
The control information registered in M30 can be registered in CM9 at the same time. In this way, if the registration information is also registered in the CM 9 at the same time, the control information in the CM 9 can be used even if the registered control information in the DM 11 and NDM 30 disappears.

(Embodiment 4) In the present embodiment, the CM 9 and the NDM 30 are duplicated and non-volatile for the purpose of improving the reliability of control information, but it is premised that the DM 11 is a non-duplicated volatile memory. . In the present embodiment, under the above assumption, it is possible to store a part of the non-volatile decentralized control information in the DM11 while maintaining the access time of the CBS 8 and the reliability of the control information equivalent to those of the third embodiment. Here is an example.

In general, the dual / nonvolatile memory such as the NDM 30 has a higher realization cost than the single / volatile memory such as the DM 11. Therefore, it is desirable that the capacity of the NDM 30 is as small as possible. If a part of the non-volatile decentralized control information can be stored in the DM 11, the required capacity of the NDM 30 can be reduced and the control information decentralization cost can be reduced. The configuration of the DKC 1 in this embodiment is as shown in FIG. 4 as in the third embodiment, and the operation of the data transfer system is the same as in the first embodiment. In the operation of the control system, the operation of the volatile decentralized control information and the non-decentralized control information is performed in the third embodiment
Is the same as. Therefore, the operation of the non-volatile distributed control information in the operation of the control system will be mainly described below with reference to FIGS. 4, 8 and 9.

It is usually possible to store only the volatile dispersion control information in the DM 11. However, even in the case of the non-volatile decentralized control information, if the same non-volatile decentralized control information exists in the CM 9, it can be stored in the DM 11. This is because the control information remains on the non-volatile CM 9 even if the contents of the DM 11 are lost due to an accident such as a power failure. Therefore, the non-volatile distributed control information in which the same non-volatile distributed control information exists in the CM 9 is stored in the DM 11. Further, the non-volatile distributed control information in which the same non-volatile distributed control information does not exist in the CM 9 is stored in the NDM 30. The non-volatile distributed control information does not exist in both DM 11 and NDM 30 at the same time. Hereinafter, FIG. 8 is a process flow for the non-volatile distributed control information reference request (81), and FIG. 9 is a process flow for the non-volatile distributed control information registration request (91). Each will be described below.

When the reference hits, the CBS8 access does not occur because the reference is made to the own DM 11 or the own NDM (83). In the case of reference error, CBS access such as CM9 reference time phase occurs (84), (85).
When the same control information does not exist in the other DM 11 and the other NDM 30, the reference control information is stored from the CM 9 to the own DM 11 (87). When the same control information exists in another DM 11,
The reference control information is stored from the other DM 11 to the own DM 11 (8
9). When the same control information exists in the other NDM 30, the reference information is moved from the other NDM 30 to the other DM 11 (81
0), registration is performed in the CM 9 (811), and reference control information is stored in the own DM 11 from another DM 11 (89). The reference information is moved from another NDM 30 to another DM 11 by CBS8.
Not through. Further, since the registration in the CM 9 is performed at the same time as the storage in the own DM 11 by another DM 11, the bus access time does not become long.

When there is a registration hit in the own NDM 30 and when the same control information exists only in the CM 9 at the time of registration error, the own NDM 30
Registered on 30, no CBS8 access occurs
(94). Registration hit to own DM11, and other DM11
If the same control information does not exist in (1), the own DM 11 is invalidated (96) and registered in the own NDM 30 (94). This is because the control information is from the own DM11 to the own NDM3.
It means that it moved to 0. No CBS8 access occurs when moving. Misregistered in own NDM30, other D
When the same control data exists in M11 or another NDM 30, CBS access such as CM9 registration time phase occurs (97), (98). Other DM11 or other NDM30
Invalidation (99), registration in CM9 (910), own DM
Registration (911) to 11 is performed. Since the above three processes are simultaneously performed during the CM9 registration time, the bus access time does not become long.

[0046]

Since the conventional DKC centrally manages the control information, there is a risk that access to the control information will be a bottleneck. However, since the present invention enables decentralization of control information, there is no risk of access to control information being a bottleneck, and performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a disk control device according to a first embodiment of the present invention.

FIG. 2 is a processing flowchart of the first embodiment of the present invention.

FIG. 3 is a processing flowchart of a second embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a disk control device according to a third embodiment of the present invention.

FIG. 5 is a processing flowchart of a third embodiment of the present invention.

FIG. 6 is an address map diagram of control information according to the third embodiment of this invention.

FIG. 7 is a block diagram showing the configuration of a conventional disk system.

FIG. 8 is a processing flowchart of the fourth embodiment of the present invention.

FIG. 9 is a processing flowchart of the fourth embodiment of the present invention.

[Explanation of symbols]

1 ... Disk controller (DKC), 3 ... Channel path,
4 ... Channel switch circuit, 5 ... Channel data control circuit (CDC), 6 ... Microprocessor (MP), 7 ... Data common bus (DBS), 8 ... Control information common bus (CBS), 9 ... Control information memory (CM), 10 ... Cache memory, 11 ... Distributed memory (DM), 12 ... Drive, 13 ... Drive data control circuit (DDC), 14 ...
Drive path, 30 ... Non-volatile distributed memory (NDM).

Claims (20)

[Claims] 1. A disk device storing or storing the data in response to a data input / output request from a host device, and a control device for managing data input / output between the disk device and the host device. 2. A disk control device according to claim 1, wherein a semiconductor memory that stores control information that is referred to and registered by a microprocessor that manages input / output of data in the control device is divided into two or more in the control device. 2. The control information for controlling the input / output of data in the control device according to claim 1,
Disk control device divided into more than one. 3. The semiconductor memory divided into two or more in the control device according to claim 1, wherein the microprocessor for managing input / output of data in the control device stores control information for reference and registration. A disk controller in which at least one of them is non-volatile. 4. A disk according to claim 1, wherein each microprocessor for managing input / output of data in the control device is provided with a semiconductor memory for storing control information for managing input / output of data in the control device. Control device. 5. The semiconductor memory according to claim 1, which is provided in each microprocessor for managing input / output of data in the control device, and semiconductor memory for storing control information for managing input / output of data in the control device. Disk controller with both. 6. The micro control device according to claim 5, wherein a part of the control information in a semiconductor memory storing control information for managing the input / output of data in the control device is stored in each micro controller for managing the input / output of data in the control device. A disk control device for storing in a semiconductor memory provided in a processor. 7. A copy of a part of control information in a semiconductor memory storing control information for managing input / output of data in the control device, and a management of input / output of data in the control device according to claim 5. A disk control device stored in a semiconductor memory provided in each microprocessor. 8. The semiconductor memory provided in each microprocessor for managing data input / output in the control device according to claim 4, wherein the microprocessor for managing data input / output in the control device is a control device. A disk controller that stores control information that is referenced when managing the input / output of data in the disk. 9. The semiconductor memory according to claim 8, wherein the microprocessor for managing the input / output of data in the control device refers to the microprocessor for managing the input / output of data in the control device. A disk control device that refers to the control information from a semiconductor memory provided in a microprocessor that refers to the control information when the control information is present therein. 10. The semiconductor memory according to claim 9, wherein the microprocessor for managing the input / output of data in the control device refers to the microprocessor for managing the input / output of data in the control device. Since the control information does not exist inside, when the control information is referenced from another semiconductor memory, the control information referenced from the other semiconductor memory is stored in the semiconductor memory provided in the microprocessor that performs the reference. Disk controller to store. 11. A disk control device according to claim 4, wherein a part of a semiconductor memory provided in a microprocessor in the control device is made nonvolatile by a battery. 12. The disk control device according to claim 1, wherein an area for storing information regarding control information storage is secured in a semiconductor memory in the control device. 13. The microprocessor according to claim 11, wherein the microprocessor for managing data input / output in the control device controls in a semiconductor memory provided in the microprocessor when managing data input / output in the control device. A disk controller that registers information. 14. The nonvolatile semiconductor device according to claim 13, wherein the microprocessor for managing input / output of data in the control device is provided in the microprocessor when managing input / output of data in the control device. A disk controller that registers control information in memory. 15. The microprocessor for managing the input / output of data in the control device determines the storage destination of the control information according to the information about the storage of the control information stored in the semiconductor memory in the control device. Disk controller to judge. 16. The semiconductor memory according to claim 13, wherein the microprocessor that manages the input / output of data in the control device performs registration when managing the input / output of data in the control device. A disk control device for registering the control information in a semiconductor memory provided in a microprocessor for registration when the control information is present therein. 17. The semiconductor memory according to claim 13, wherein the microprocessor that manages the input / output of data in the control device performs registration when managing the input / output of data in the control device. A disk control device for registering the control information in a semiconductor memory provided in a microprocessor that performs registration when the control information is registered in another semiconductor memory because the control information does not exist therein. 18. The semiconductor memory according to claim 17, wherein the microprocessor that manages the input / output of data in the control device performs registration when managing the input / output of data in the control device. And a disk control device that registers the control information in both the semiconductor memory and the other semiconductor memory. 19. The microprocessor according to claim 14, which manages the input / output of data in the control device, is a nonvolatile memory provided in the microprocessor when managing the input / output of data in the control device. From within the semiconductor memory,
A disk control device for moving control information necessary for managing input / output of data in the control device into a non-volatile semiconductor memory provided in the microprocessor. 20. The microprocessor for managing data input / output in the control device according to claim 19, wherein the microprocessor is non-volatile provided in the microprocessor when managing data input / output in the control device. A disk control device that moves control information necessary for managing data input / output in a control device from a non-existing semiconductor memory to a non-volatile semiconductor memory provided in the microprocessor.