JPH0730195A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0730195A JPH0730195A JP19315493A JP19315493A JPH0730195A JP H0730195 A JPH0730195 A JP H0730195A JP 19315493 A JP19315493 A JP 19315493A JP 19315493 A JP19315493 A JP 19315493A JP H0730195 A JPH0730195 A JP H0730195A
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- substrate
- refractive index
- semiconductor device
- dielectric film
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子及びその製造
方法に係り、特にリッジ型ないし埋め込み型半導体の形
成に好適に利用できる半導体素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of manufacturing a semiconductor device that can be suitably used for forming a ridge type or buried type semiconductor.
【0002】[0002]
【従来の技術】従来、リッジ型半導体レーザ素子の横方
向の光閉じ込め構造を形成するプロセスは、次のような
プロセスで行われていた。2. Description of the Related Art Conventionally, a process for forming a lateral optical confinement structure for a ridge type semiconductor laser device has been performed as follows.
【0003】図6(a)〜(e)は従来のリッジ型半導
体レーザ素子の製造方法を説明するための工程図であ
る。FIGS. 6A to 6E are process drawings for explaining a conventional method for manufacturing a ridge type semiconductor laser device.
【0004】まず図6(a)に示すような平坦な半導体
基板101上に、図6(b)に示すように、活性層10
2、クラッド層103、キャップ層104を積層して、
平坦な半導体レーザウエハーを形成する。First, as shown in FIG. 6B, an active layer 10 is formed on a flat semiconductor substrate 101 as shown in FIG.
2. Laminate the clad layer 103 and the cap layer 104,
Form a flat semiconductor laser wafer.
【0005】続いて、図6(c)に示すように、フォト
リソグラフィー工程と反応性イオンビームエッチング
(RIBE)法等のエッチング工程で、キャップ層10
4の下層であるクラッド層103の所定の深さの所まで
エッチングし、横方向の光閉じ込め構造を形成する。Subsequently, as shown in FIG. 6C, a cap layer 10 is formed by a photolithography process and an etching process such as a reactive ion beam etching (RIBE) method.
4 is etched to a predetermined depth in the clad layer 103, which is the lower layer of 4, to form a lateral optical confinement structure.
【0006】その後、図6(d)、(e)に示すよう
に、半導体レーザウエハーに絶縁膜105を成膜し、リ
ッジの頂き部の絶縁膜105を除去し、電流注入窓を形
成する。 このように従来のリッジ型半導体レーザ素子
の横方向の光閉じ込め構造を形成するプロセスは、半導
体基板101上へ所望の構造をエピタキシャル成長した
後、エッチングを行う工程が用いられていた。Thereafter, as shown in FIGS. 6D and 6E, an insulating film 105 is formed on the semiconductor laser wafer, the insulating film 105 at the top of the ridge is removed, and a current injection window is formed. As described above, in the conventional process of forming the lateral optical confinement structure of the ridge type semiconductor laser device, a step of performing epitaxial growth of a desired structure on the semiconductor substrate 101 and then performing etching is used.
【0007】また、従来、埋め込み型の半導体レーザ素
子の横方向の光閉じ込め構造を形成するプロセスは、図
7(a)〜(d)に示すように、平坦な半導体基板上2
01に活性層202、クラッド層203、キャップ層2
04を積層して平坦な半導体レーザウエハーを構成した
後、フォトリソグラフィー工程と反応性イオンビームエ
ッチング法等のエッチング工程で、活性層202の下層
の基板201までエッチングし、さらに、光閉じ込めと
電流狭窄を行うための埋め込み層205を形成する。Further, conventionally, a process of forming a lateral optical confinement structure of a buried type semiconductor laser device is performed on a flat semiconductor substrate 2 as shown in FIGS. 7 (a) to 7 (d).
01 to the active layer 202, the cladding layer 203, the cap layer 2
After stacking 04 to form a flat semiconductor laser wafer, the substrate 201 below the active layer 202 is etched by a photolithography process and an etching process such as a reactive ion beam etching method, and further, light confinement and current confinement are performed. A buried layer 205 for performing the above is formed.
【0008】この従来の埋め込み型の半導体レーザ構造
を形成するプロセスは、半導体基板201上へのエピタ
キシャル成長後、エッチングし、さらに再成長を行う工
程が用いられていた。In the conventional process of forming the buried type semiconductor laser structure, a step of performing epitaxial growth on the semiconductor substrate 201, etching, and then re-growing is used.
【0009】[0009]
【発明が解決しようとしている課題】しかしながら、上
記従来のリッジ型半導体レーザ素子を形成するプロセス
では、次のような課題があった。However, the conventional process for forming the ridge-type semiconductor laser device has the following problems.
【0010】・ドライエッチング工程を必要とするた
め、歩留まりが悪い。 ・ドライエッチングプロセスで半導体レーザの活性層近
くまでエッチングするため、活性層にダメージを与えて
しまい、半導体レーザ素子の寿命を縮めたり、電気的特
性に悪影響を及ぼしてしまう。 ・ドライエッチングプロセスでリッジを形成する場合、
深さ、幅の要求精度がきびしく(深さ精度2.0μm±
0.1μm、幅の精度3μm以下)、プロセス制御が困
難で再現性が悪い。Since the dry etching process is required, the yield is low. Since the active layer of the semiconductor laser is etched close to the active layer by the dry etching process, the active layer is damaged, shortening the life of the semiconductor laser device and adversely affecting the electrical characteristics. -When forming a ridge by a dry etching process,
The required accuracy of depth and width is severe (depth accuracy 2.0 μm ±
0.1 μm, width accuracy of 3 μm or less), process control is difficult, and reproducibility is poor.
【0011】また、埋め込み型の半導体レーザ素子を形
成するプロセスでは、次のような課題があった。Further, the process of forming a buried type semiconductor laser device has the following problems.
【0012】まず、ドライエッチング工程を必要とする
ため、上記3つの課題がある。さらに、再成長プロセス
を必要とするため、非常にスループット、歩留まりが悪
い。First, since the dry etching process is required, there are the above three problems. Furthermore, since the regrowth process is required, the throughput and the yield are very poor.
【0013】本発明は、上記の課題を解決するためにな
されたものであり、その目的は、各プロセスが容易に実
施できて、失敗がなく、作業時間が短縮され、しかも寿
命の長い、屈折率導波型半導体レーザ素子等の半導体素
子を製造することのできる方法及びその半導体素子を提
供することにある。The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to make it possible to carry out each process easily, to prevent failures, to shorten the working time, and to prolong the life of the refraction. It is an object of the present invention to provide a method capable of manufacturing a semiconductor device such as a rate-guided semiconductor laser device and the semiconductor device.
【0014】[0014]
【課題を解決するための手段】本発明の半導体素子ない
しその製造方法は、少なくとも半導体基板上に所望の屈
折率導波路となる領域以外にパターン状のマスク層を設
け、この基板を任意の深さエッチングして溝部を形成
し、この基板に誘電体膜を形成し、溝部の底面の誘電体
膜だけを除去し、さらに、この基板上に選択的に任意の
半導体層構成をエピタキシャル成長により形成すること
を特徴とする。According to the present invention, there is provided a semiconductor device and a method for manufacturing the same, in which a patterned mask layer is provided on at least a region other than a region to be a desired refractive index waveguide, and the substrate is formed at an arbitrary depth. Then, a groove is formed by etching, a dielectric film is formed on this substrate, only the dielectric film on the bottom surface of the groove is removed, and further, an arbitrary semiconductor layer structure is selectively formed on this substrate by epitaxial growth. It is characterized by
【0015】詳細には、本発明の半導体素子の製造方法
では、半導体基板上に、所望の屈折率導波路となる領域
以外にマスク層を設け、この基板をエッチングして所望
の屈折率導波路となる領域に溝部を形成し、さらに前記
基板の溝部に底面を除いて誘電体膜を形成し、前記溝部
底面上に前記誘電体膜を選択マスクとして、選択的に導
波路構造を形成することを特徴とする。Specifically, in the method for manufacturing a semiconductor device of the present invention, a mask layer is provided on a semiconductor substrate in a region other than a region to be a desired refractive index waveguide, and the substrate is etched to obtain a desired refractive index waveguide. Forming a groove portion in a region to be formed, further forming a dielectric film on the groove portion of the substrate except the bottom surface, and selectively forming a waveguide structure on the bottom surface of the groove portion using the dielectric film as a selection mask. Is characterized by.
【0016】また、本発明の半導体素子では、半導体基
板上に、所望の屈折率導波路となる領域以外にマスク層
が設けられ、この基板をエッチングして所望の屈折率導
波路となる領域に溝部が形成され、さらに前記基板の溝
部に底面を除いて誘電体膜が形成され、前記溝部底面上
に前記誘電体膜を選択マスクとして、選択的に導波路構
造が形成されていることを特徴とする。Further, in the semiconductor device of the present invention, a mask layer is provided on the semiconductor substrate in a region other than the region where the desired refractive index waveguide is formed, and this substrate is etched to form a region where the desired refractive index waveguide is formed. A groove is formed, a dielectric film is formed on the groove of the substrate except the bottom surface, and a waveguide structure is selectively formed on the bottom of the groove using the dielectric film as a selection mask. And
【0017】より具体的には、前記導波路構造は、活性
層を含んで形成されたり、前記屈折率導波路はリッジで
形成されたり、前記溝部は充分深く形成されて、前記屈
折率導波路は、埋め込んで形成されたり、前記活性層の
エネルギーギャップは、前記半導体基板のエネルギーギ
ャップより小さく形成されたりする。More specifically, the waveguide structure is formed to include an active layer, the refractive index waveguide is formed by a ridge, and the groove portion is formed sufficiently deep to form the refractive index waveguide. Are buried or the energy gap of the active layer is smaller than the energy gap of the semiconductor substrate.
【0018】[0018]
【実施例1】以下、図1を用いて、本発明の実施例につ
いて説明する。本実施例は、本発明をリッジ型半導体レ
ーザ素子に用いたものである。[Embodiment 1] An embodiment of the present invention will be described below with reference to FIG. In this embodiment, the present invention is applied to a ridge type semiconductor laser device.
【0019】図1(a)〜(d)は、本発明の半導体素
子の製造方法の代表的な一実施態様例を説明するための
工程図である。FIGS. 1A to 1D are process drawings for explaining a typical embodiment of the method for manufacturing a semiconductor device of the present invention.
【0020】まず、図1(a)に示すように、n型半導
体基板21上に、ストライプ状の領域が形成された誘電
体膜25を設置し、誘電体膜25が形成された領域以外
の領域を任意の深さエッチングし、ストライプ状の溝2
1aを形成する。誘電体膜25は、SiO2、SiN、
Al2O3等の誘電体膜をプラズマCVD法、スパッタ法
等、材料に応じて適宜選定した成膜法によって形成す
る。First, as shown in FIG. 1A, a dielectric film 25 having a stripe-shaped region is provided on an n-type semiconductor substrate 21, and a region other than the region where the dielectric film 25 is formed is provided. The area is etched to an arbitrary depth, and stripe-shaped grooves 2
1a is formed. The dielectric film 25 is made of SiO 2 , SiN,
A dielectric film such as Al 2 O 3 is formed by a film forming method appropriately selected according to the material, such as a plasma CVD method or a sputtering method.
【0021】続いて、図1(b)に示すように、誘電体
膜26を上記と同様にして、基板21、誘電体25上に
形成する。Subsequently, as shown in FIG. 1B, the dielectric film 26 is formed on the substrate 21 and the dielectric 25 in the same manner as described above.
【0022】次に、図1(c)に示すようにストライプ
状の溝25aの底面の誘電体膜26をエッチングし、基
板21を露出させる。エッチング法としては、SF6、
CF4等のガス雰囲気を用いた反応性イオンエッチング
法が挙げられる。Next, as shown in FIG. 1C, the dielectric film 26 on the bottom surface of the stripe-shaped groove 25a is etched to expose the substrate 21. As an etching method, SF 6 ,
A reactive ion etching method using a gas atmosphere such as CF 4 may be used.
【0023】次に、図1(d)に示すように、この半導
体ウエハー上に多重量子井戸型構造の活性層22、p型
半導体クラッド層23、p型半導体キャップ層24を順
に溝25aに沿ってストライプ状に選択的に積層し、リ
ッジ型の半導体レーザウエハーとする。Next, as shown in FIG. 1D, an active layer 22, a p-type semiconductor cladding layer 23, and a p-type semiconductor cap layer 24 having a multiple quantum well structure are sequentially formed on this semiconductor wafer along a groove 25a. By selectively stacking in stripes to form a ridge type semiconductor laser wafer.
【0024】ただし、半導体レーザウエハーはこのよう
なものに限らず、リッジ型に適用できるものであれば、
構造、材料に関しては、特に制限はなく使用することが
できる。However, the semiconductor laser wafer is not limited to this, and any semiconductor laser wafer applicable to the ridge type can be used.
There are no particular restrictions on the structure and materials, and they can be used.
【0025】例えば、上記のpとnとを入れ換えても勿
論良いし、活性層としては多重量子井戸型構造(MQ
W)に限らず、単量子井戸型構造(SQW)、ダブルヘ
テロ(DH)構造のものが、また、レーザウエハーとし
ては、加工した基板にグレーティングを形成した上にレ
ーザ構造の各層を成長させたもの等が利用できる。For example, the above p and n may be replaced with each other, and the active layer may have a multiple quantum well structure (MQ).
Not only W), but also a single quantum well structure (SQW) structure and a double hetero structure (DH) structure. As a laser wafer, a grating is formed on a processed substrate and each layer of the laser structure is grown. Things can be used.
【0026】更に、半導体レーザの材料としてはGaA
s・AlGaAs系の他、InP・InGaAsP系、
AlGaInP系等が使用できる。Further, as a material for the semiconductor laser, GaA is used.
s ・ AlGaAs system, InP ・ InGaAsP system,
AlGaInP type etc. can be used.
【0027】以上説明した工程により作製されたものに
対し、電極等の別部が付設される他に、物理的処理(例
えば、共振面形成のための処理、熱処理等)等の必要処
理がなされるが、そのような必要処理を受けたもの、受
けてないもの共に本実施態様例でいうリッジ型半導体レ
ーザ素子である。In addition to the additional parts such as electrodes attached to the product manufactured by the steps described above, necessary processing such as physical processing (for example, processing for forming a resonance surface, heat treatment, etc.) is performed. However, both the ridge type semiconductor laser device that has undergone such necessary processing and the one that has not undergone such necessary processing are the ridge type semiconductor laser devices described in this embodiment.
【0028】なお、上記共振面形成はへき開によっても
よいし、共振面の片面または両面にウェットエッチング
プロセスまたはドライエッチングプロセス等を施すこと
によって作製してもよい。The resonance surface may be formed by cleavage, or may be formed by subjecting one or both surfaces of the resonance surface to a wet etching process or a dry etching process.
【0029】また、本実施態様例は、上記屈折率導波型
のリッジ型半導体レーザ素子の製造ばかりでなく、同様
なストライプ状の屈折率導波型の導波路、光スイッチ、
光変調器などの半導体素子の製造にも適用できる。この
場合、半導体素子とは、前記リッジ型半導体レーザ素子
と同様な工程や必要処理がなされたものをいう。Further, this embodiment is not limited to the manufacture of the above-mentioned index-guided ridge type semiconductor laser device, but is also applicable to a similar stripe-shaped index-guided waveguide, an optical switch,
It can also be applied to the manufacture of semiconductor devices such as optical modulators. In this case, the semiconductor element means an element that has undergone the same steps and necessary processing as those of the ridge type semiconductor laser element.
【0030】なお、図1(a)〜(d)までのプロセス
を、マルチチャンバー型の真空装置を用い、真空一貫プ
ロセスで行ってもよい。The processes shown in FIGS. 1 (a) to 1 (d) may be carried out in a vacuum consistent process using a multi-chamber type vacuum device.
【0031】以下、上記実施態様例を更に具体化した実
施例について、前述した図1(a)〜(d)と図2
(a)、(b)で説明する。Hereinafter, an embodiment in which the above embodiment is further embodied will be described with reference to FIGS. 1 (a) to 1 (d) and FIG.
This will be described with reference to (a) and (b).
【0032】まず、n型InP基板21上に、SiOか
らなる誘電体膜25を厚さ1200Åで全面にスパッタ
蒸着法により形成し、フォトリソグラフィ工程により幅
3μmのストライプ状のネガパターンを形成した後、4
PaのSF6雰囲気での反応性イオンエッチング(RI
E)により、幅3μmのストライプ状に誘電体膜25を
選択的にエッチングする。続いて、残った誘電体膜25
をマスクとして、塩素雰囲気での反応性イオンビームエ
ッチングにより、InP基板21を深さ0.3μmエッ
チングし、ストライプ状の溝25aを形成した。(図1
(a)参照)続いて、このウエハーにSiOからなる誘
電体膜26を厚さ2000Åでスパッタ蒸着法により形
成し(図1(b)参照)、更に、4PaのSF6雰囲気
での反応性イオンエッチングにより、図1(c)に示す
ように、ストライプ状の溝25aの側壁の誘電体膜26
及び基板21上の誘電体膜25以外の誘電体膜26をエ
ッチングし、溝の底部にn−InP基板21を露出させ
た。First, a dielectric film 25 made of SiO 2 having a thickness of 1200 Å is formed on the entire surface of the n-type InP substrate 21 by the sputter vapor deposition method, and a striped negative pattern having a width of 3 μm is formed by a photolithography process. Four
Reactive ion etching in SF 6 atmosphere Pa (RI
By E), the dielectric film 25 is selectively etched in a stripe shape having a width of 3 μm. Then, the remaining dielectric film 25
Using as a mask, the InP substrate 21 was etched to a depth of 0.3 μm by reactive ion beam etching in a chlorine atmosphere to form stripe grooves 25a. (Fig. 1
(See (a)) Subsequently, a dielectric film 26 made of SiO 2 is formed on this wafer with a thickness of 2000 Å by a sputter deposition method (see FIG. 1 (b)), and further reactive ions in an SF 6 atmosphere of 4 Pa are used. By etching, as shown in FIG. 1C, the dielectric film 26 on the sidewall of the stripe-shaped groove 25a is formed.
The dielectric film 26 other than the dielectric film 25 on the substrate 21 was etched to expose the n-InP substrate 21 at the bottom of the groove.
【0033】さらに、n−InP基板21のストライプ
状の溝部25aのみに、ケミカルビームエピタキシャル
(CBE)法により、ノンドープInGaAs(40Å
厚)、InGaAsP(200Å厚)を4回繰り返し積
層して多重量子井戸構造を形成した活性層22、p-I
nPクラッド層23(2.0μm厚)、p+-InGaA
sPキャップ層24(0.5μm厚)を順次選択成長
し、リッジ部を形成して横方向の光閉じ込めを行うスト
ライプ構造とした。Furthermore, non-doped InGaAs (40 Å) is formed only in the stripe-shaped groove portion 25a of the n-InP substrate 21 by the chemical beam epitaxial (CBE) method.
Thickness) and InGaAsP (200 Å thickness) are repeatedly laminated four times to form a multi-quantum well structure active layer 22, p-I
nP clad layer 23 (2.0 μm thick), p + -InGaA
An sP cap layer 24 (0.5 μm thick) was sequentially grown selectively to form a ridge portion to form a stripe structure for confining light in the lateral direction.
【0034】続いて、このリッジが形成されたレーザウ
エハー上に、SiNから成る絶縁膜27(厚さ1200
Å)をプラズマCVD法によって形成し、SiN絶縁膜
27上にレジストを約1.0μmスピンコートした。そ
の後、4PaのO2雰囲気でのRIE(反応性イオンエ
ッチング)法によって、リッジの頂き部に成膜されたレ
ジストのみを除去し、リッジの頂き部のSiN絶縁膜2
7を露出させ、更に4PaのCF4ガス雰囲気でのRI
E法を実施してリッジの頂き部の露出したSiN絶縁膜
27を選択的にエッチングする。その後、残存している
レジストを4PaのO2雰囲気でのRIE法により除去
した。Subsequently, an insulating film 27 (thickness 1200) made of SiN is formed on the laser wafer on which the ridge is formed.
Å) was formed by a plasma CVD method, and a resist was spin-coated on the SiN insulating film 27 by about 1.0 μm. Then, only the resist formed on the top of the ridge is removed by RIE (reactive ion etching) in an O 2 atmosphere of 4 Pa, and the SiN insulating film 2 on the top of the ridge is removed.
7 is exposed, and RI is further applied in a CF 4 gas atmosphere of 4 Pa.
By performing the E method, the SiN insulating film 27 exposed at the top of the ridge is selectively etched. After that, the remaining resist was removed by the RIE method in an O 2 atmosphere of 4 Pa.
【0035】次いで、リッジの頂き部に形成された表面
酸化膜を塩酸によってウェットエッチングして電流注入
窓とし、続いて、上部電極としてAu−Zn−Auオー
ミック用電極28を真空蒸着法で形成し、InP基板2
1をラッピングで100μmの厚さまで削った後にn型
オーミック用電極29としてAu−Sn−Au電極を蒸
着した。そして、p型、n型の電極のオーミックコンタ
クトをとる為の熱処理を行い、リッジ型光半導体素子と
した。Next, the surface oxide film formed on the top of the ridge is wet-etched with hydrochloric acid to form a current injection window, and subsequently an Au-Zn-Au ohmic electrode 28 is formed as an upper electrode by a vacuum evaporation method. , InP substrate 2
1 was lapped to a thickness of 100 μm, and then an Au—Sn—Au electrode was vapor-deposited as an n-type ohmic electrode 29. Then, heat treatment for making ohmic contact with the p-type and n-type electrodes was performed to obtain a ridge-type optical semiconductor element.
【0036】最後に、共振面をへき開により形成し、E
B(エレクトロンビーム)蒸着によってSiO2系の高
反射膜、低反射膜をそれぞれコーティングし、スクライ
ブで分離し、電極28、29はワイヤーボンディングに
より取り出す。Finally, the resonance surface is formed by cleavage, and E
A SiO 2 -based high-reflection film and a low-reflection film are each coated by B (electron beam) vapor deposition, separated by scribing, and the electrodes 28 and 29 are taken out by wire bonding.
【0037】繰り返し、同様な工程により、半導体レー
ザ装置を形成したところ、長寿命(室温下2000時間
以上レーザ発振可能)の特性をもつ装置が再現性良く得
られた。When a semiconductor laser device was formed by repeating the same steps, a device having a long life (capable of laser oscillation for 2000 hours or more at room temperature) was obtained with good reproducibility.
【0038】[0038]
【他の実施例】図3は、埋め込み型の屈折率導波型のD
FB半導体レーザ素子の第2実施例を示す上面図、図
4、図5は図3のA−A′、B−B′断面図である。[Other Embodiments] FIG. 3 shows an embedded type index-guided type D.
FIG. 4 is a top view showing a second embodiment of the FB semiconductor laser device, and FIGS. 4 and 5 are sectional views taken along the lines AA 'and BB' in FIG.
【0039】以下、第2実施例のプロセス手順について
説明する。まず、n型In-P基板31上に、SiNか
らなる誘電体膜37(厚さ2000Å)を全面にプラズ
マCVD法により形成し、フォトリソグラフィ工程とR
IE法により幅3μmのストライプ状の溝を形成したの
ち、SiN誘電体37をマスクとして、塩素雰囲気での
RIBE法により、n型In-P基板31を深さ3.0
μmエッチングし、ストライプ状の溝を形成した。The process procedure of the second embodiment will be described below. First, a dielectric film 37 (thickness 2000 Å) made of SiN is formed on the entire surface of an n-type In-P substrate 31 by a plasma CVD method, and a photolithography process and R
After a stripe-shaped groove having a width of 3 μm is formed by the IE method, the n-type In-P substrate 31 is made to have a depth of 3.0 by the RIBE method in a chlorine atmosphere using the SiN dielectric 37 as a mask.
μm etching was performed to form stripe-shaped grooves.
【0040】続いてSiOからなる誘電体膜38(厚さ
1200Å)をスパッタ蒸着法によりウエハー全体に形
成し、更に、4PaのSF6雰囲気でのRIEにより、
溝底面のSiO誘電体膜38をエッチングし、下地であ
るn型InP基板31を露出させる。Subsequently, a dielectric film 38 (thickness 1200 Å) made of SiO is formed on the entire wafer by a sputter deposition method, and further, by RIE in an SF 6 atmosphere of 4 Pa.
The SiO dielectric film 38 on the bottom of the groove is etched to expose the underlying n-type InP substrate 31.
【0041】さらに、二光束干渉露光法とRIBEによ
り、図3のA−A′方向に垂直なグレーティングgを溝
底面に形成した。Further, a grating g perpendicular to the AA 'direction in FIG. 3 was formed on the groove bottom surface by the two-beam interference exposure method and RIBE.
【0042】続いて、MOCVD法により、n−InG
aAsP光ガイド層32(1000Å厚)、ノンドープ
InGaAs(40Å厚)、InGaAsP(2000
Å厚)を4回繰り返し積層して多重量子井戸構造を形成
した活性層33、p−InGaAsP光ガイド層34
(1000Å厚)、p−InPクラッド層35(1.5
μm厚)、p+−InGaAsPキャップ層36(0.
5μm厚)を、順次、ストライプ状溝部に選択成長して
埋め込み、横方向の光閉じ込めを行う埋め込み型の屈折
率導波構造とした。Then, n-InG is formed by MOCVD.
aAsP optical guide layer 32 (1000 Å thickness), undoped InGaAs (40 Å thickness), InGaAsP (2000
Å) is repeatedly laminated four times to form an active layer 33 and a p-InGaAsP optical guide layer 34.
(1000Å thickness), p-InP clad layer 35 (1.5
.mu.m thick), p.sup . + -InGaAsP cap layer 36 (0.
5 .mu.m thick) was sequentially grown selectively in the stripe-shaped trenches and buried therein to form a buried-type refractive index waveguide structure for laterally confining light.
【0043】続いて、上部電極としてAu−Zn−Au
オーミック用電極39を真空蒸着法で形成し、InP基
板31をラッピングで100μmの厚さまで削った後に
n型オーミック用電極40としてAuSnAu電極を蒸
着した。そして、p型、n型の電極39、40のオーミ
ックコンタクトをとる為の熱処理を行い、埋め込み型半
導体素子とした。Subsequently, Au--Zn--Au was used as the upper electrode.
The ohmic electrode 39 was formed by a vacuum vapor deposition method, the InP substrate 31 was lapped to a thickness of 100 μm, and then an AuSnAu electrode was vapor deposited as an n-type ohmic electrode 40. Then, heat treatment for making ohmic contact between the p-type and n-type electrodes 39 and 40 was performed to obtain a buried semiconductor element.
【0044】最後に、共振面をへき開により形成し、E
B蒸着によってSiO等の高反射膜、低反射膜をそれぞ
れコーティングし、スクライブで分離し、電極39、4
0はワイヤーボンディングにより取り出した。Finally, the resonance surface is formed by cleavage, and E
A high reflection film and a low reflection film such as SiO are coated by B vapor deposition and separated by scribing, and electrodes 39, 4 are formed.
0 was taken out by wire bonding.
【0045】本実施例についても、繰り返し、同様な工
程により、低しきい値(Ith<15mA)、長寿命の特
性をもつ半導体レーザ装置が再現性良く得られた。Also in this example, by repeating the same steps, a semiconductor laser device having a low threshold value (I th <15 mA) and a long life was obtained with good reproducibility.
【0046】[0046]
【発明の効果】以上説明したように、本発明の半導体素
子の製造方法では、高精度のエッチング制御が必要でな
いため、製造の失敗がなく、時間もかからず、歩留ま
り、制御性が向上する。As described above, in the method for manufacturing a semiconductor device of the present invention, since highly precise etching control is not required, there is no manufacturing failure, no time is required, and the yield and controllability are improved. .
【0047】また、活性層付近および活性層をエッチン
グすることがないため、ダメージも受けないので、半導
体素子の長寿命化を可能にすることができる。更に真空
一貫プロセスで行うことができるので、スループットが
大幅に向上する。Further, since the vicinity of the active layer and the active layer are not etched, no damage is caused, so that the life of the semiconductor element can be extended. Furthermore, since it can be performed by a vacuum integrated process, the throughput is significantly improved.
【0048】本発明は、光通信、光情報伝送装置に利用
される半導体素子の製造に極めて有効である。The present invention is extremely effective for manufacturing semiconductor elements used in optical communication and optical information transmission devices.
【図1】本発明の半導体素子の製造方法の代表的な一実
施態様例を説明するための工程図。FIG. 1 is a process drawing for explaining a typical embodiment of a method for manufacturing a semiconductor device of the present invention.
【図2】本発明の第1実施例の上面図(a)、本発明の
第1実施例の図2(a)のA−A′断面図(b)。FIG. 2 is a top view (a) of the first embodiment of the present invention, and an AA ′ sectional view (b) of FIG. 2 (a) of the first embodiment of the present invention.
【図3】本発明の第2実施例の上面図。FIG. 3 is a top view of the second embodiment of the present invention.
【図4】本発明の第2実施例の図3のA−A′断面図。FIG. 4 is a sectional view taken along the line AA ′ in FIG. 3 of the second embodiment of the present invention.
【図5】本発明の第2実施例の図3のB−B′断面図。FIG. 5 is a sectional view taken along the line BB ′ of FIG. 3 of the second embodiment of the present invention.
【図6】従来のリッジ型半導体レーザ素子の製造方法を
説明するための工程図。FIG. 6 is a process drawing for explaining a conventional method for manufacturing a ridge-type semiconductor laser device.
【図7】従来の埋め込み型半導体レーザ素子の製造方法
を説明するための工程図。7A to 7C are process diagrams for explaining a conventional method for manufacturing a buried semiconductor laser device.
21、31、101、201 半導体基板 22、33、102、202 活性層 23、35、103、203 クラッド層 24、36、104、204 キャップ層 25、26、37、38 誘電体膜 28、29、39、40 電極 32、34 光ガイド層 g グレーティング 21, 31, 101, 201 Semiconductor substrate 22, 33, 102, 202 Active layer 23, 35, 103, 203 Clad layer 24, 36, 104, 204 Cap layer 25, 26, 37, 38 Dielectric film 28, 29, 39, 40 Electrodes 32, 34 Light guide layer g Grating
Claims (10)
なる領域以外にマスク層を設け、この基板をエッチング
して所望の屈折率導波路となる領域に溝部を形成し、さ
らに前記基板の溝部に底面を除いて誘電体膜を形成し、
前記溝部底面上に前記誘電体膜を選択マスクとして、選
択的に導波路構造を形成することを特徴とする半導体素
子の製造方法。1. A semiconductor substrate is provided with a mask layer in a region other than a region to be a desired refractive index waveguide, and the substrate is etched to form a groove portion in a region to be a desired refractive index waveguide. Dielectric film is formed in the groove of
A method of manufacturing a semiconductor device, wherein a waveguide structure is selectively formed on the bottom surface of the groove using the dielectric film as a selection mask.
される請求項1記載の半導体素子の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the waveguide structure is formed to include an active layer.
請求項1記載の半導体素子の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the refractive index waveguide is formed of a ridge.
折率導波路は、埋め込んで形成される請求項1記載の半
導体素子の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed sufficiently deep, and the refractive index waveguide is embedded.
記半導体基板のエネルギーギャップより小さく形成され
る請求項2記載の半導体素子の製造方法。5. The method of manufacturing a semiconductor device according to claim 2, wherein an energy gap of the active layer is formed smaller than an energy gap of the semiconductor substrate.
なる領域以外にマスク層が設けられ、この基板をエッチ
ングして所望の屈折率導波路となる領域に溝部が形成さ
れ、さらに前記基板の溝部に底面を除いて誘電体膜が形
成され、前記溝部底面上に前記誘電体膜を選択マスクと
して、選択的に導波路構造が形成されていることを特徴
とする半導体素子。6. A mask layer is provided on a semiconductor substrate in a region other than a region to be a desired refractive index waveguide, and the substrate is etched to form a groove in a region to be a desired refractive index waveguide. A semiconductor device, wherein a dielectric film is formed in a groove portion of a substrate except a bottom surface, and a waveguide structure is selectively formed on the bottom surface of the groove portion by using the dielectric film as a selection mask.
される請求項1記載の半導体素子。7. The semiconductor device according to claim 1, wherein the waveguide structure includes an active layer.
請求項1記載の半導体素子。8. The semiconductor device according to claim 1, wherein the refractive index waveguide is formed of a ridge.
折率導波路は、埋め込んで形成される請求項1記載の半
導体素子。9. The semiconductor device according to claim 1, wherein the groove is formed sufficiently deep, and the refractive index waveguide is embedded.
前記半導体基板のエネルギーギャップより小さく形成さ
れる請求項2記載の半導体素子。10. The energy gap of the active layer is
The semiconductor device according to claim 2, wherein the semiconductor device is formed to have an energy gap smaller than that of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19315493A JPH0730195A (en) | 1993-07-08 | 1993-07-08 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19315493A JPH0730195A (en) | 1993-07-08 | 1993-07-08 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0730195A true JPH0730195A (en) | 1995-01-31 |
Family
ID=16303187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19315493A Pending JPH0730195A (en) | 1993-07-08 | 1993-07-08 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0730195A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09252165A (en) * | 1996-03-18 | 1997-09-22 | Fujitsu Ltd | Method for manufacturing compound semiconductor device |
| JP2008218996A (en) * | 2007-02-07 | 2008-09-18 | Sumitomo Electric Ind Ltd | Method for fabricating a semiconductor optical device |
-
1993
- 1993-07-08 JP JP19315493A patent/JPH0730195A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09252165A (en) * | 1996-03-18 | 1997-09-22 | Fujitsu Ltd | Method for manufacturing compound semiconductor device |
| JP2008218996A (en) * | 2007-02-07 | 2008-09-18 | Sumitomo Electric Ind Ltd | Method for fabricating a semiconductor optical device |
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