JPH0730117A - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] A thin film transistor and a manufacturing method thereof,
By a simple means, it is possible to suppress the leak current generated between the gate electrode and the source electrode or the drain electrode along the mesa-shaped side surface of the TFT. [Structure] Stacked source electrode 25S, source electrode contact layer 26S, and stacked drain electrode 25D
A drain electrode contact layer 26D and a drain electrode contact layer 26D are formed on the glass substrate 21, and an operating semiconductor layer 29, a gate insulating film 30, and a gate electrode 31 are further laminated thereon to form a sidewall of the gate electrode 31 and an underlying gate insulating layer. The gate electrode 31 is narrowed with respect to the underlying gate insulating film 30 so as to have a step with respect to the side wall of the film 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (thi) used for matrix driving a liquid crystal display device.
n film transistor (TFT) and an improved manufacturing method thereof.

A liquid crystal display device driven by a TFT matrix is
With the recent expansion of the flat display market, it is being used in projection televisions and laptop computers, but it has problems in terms of manufacturing yield and cost.

Therefore, in the future, it is necessary to make efforts to further simplify the structure and manufacturing method of the TFT in order to improve the manufacturing yield and enable the cost reduction.

[0004]

2. Description of the Related Art FIGS. 31 to 33 are side sectional views showing a staggered TFT at a process step required for explaining a conventional technique. Hereinafter, referring to these figures, FIG. The details will be described.

See FIG. 31 31- (1) ITO (indium) is formed on a transparent insulating substrate 1 such as glass.
A transparent conductive film made of, for example, m tin oxide) is formed. 31- (2) An amorphous Si film containing impurities is laminated on the transparent conductive film.

31- (3) The impurity-containing amorphous Si film and the transparent conductive film are patterned to form a source electrode contact layer 3S and a drain electrode contact layer 3D, and a source electrode 2S.
And the drain electrode 2D is formed. The source electrode 2S
A channel region should be provided between the opposing edges of the drain electrode 2D.

See FIG. 32 32- (1) An amorphous Si film to be an operating semiconductor layer, a SiN film to be a gate insulating film, and an Al film to be a gate electrode are formed on the entire surface. 32- (2) A resist film 7 is formed and patterned.

33- (1) The Al film, the SiN film and the amorphous Si film are etched in a mesa shape by using the resist film 7 as a mask to form the gate electrode 6,
The gate insulating film 5 and the operating semiconductor layer 4 are formed.

In the staggered TFT thus manufactured, the side walls of the gate electrode 6, the gate insulating film 5 and the operating semiconductor layer 4 are flush with each other, as is apparent from the figure.

[0010]

In the conventional technique described with reference to FIGS. 31 to 33, since the side walls of the gate electrode 6, the gate insulating film 5, and the operating semiconductor layer 4 are on the same plane, as described above, Along the creeping surface, the source electrode 2S
Alternatively, there is a problem that a leak current flows between the drain electrode 2D and the gate electrode 6.

The present invention aims to make it possible to suppress a leak current generated between a gate electrode and a source electrode or a drain electrode along a mesa-shaped side surface of a TFT by a simple means.

[0012]

According to the experiments by the present inventors, the leakage current between the gate electrode and the source electrode or the drain electrode is caused by the side wall of the gate electrode and the side wall of the underlying gate insulating film. The structure that does not become the same plane, that is,
We have found that it is possible to significantly reduce the difference by adopting a step shape. Also, although it is a very touched method,
Good results can be obtained even when an insulating film is used in combination with the above step shape.

However, regarding the step shape and the method of providing the insulating film, the structure of the stagger type TFT is taken into consideration.
It is necessary to take unique and appropriate measures, and the present invention resides therein.

FIGS. 1 to 4 are side sectional views showing essential parts of a TFT at a process step for explaining the principle of the present invention, which will be described below in detail with reference to these figures.

See FIG. 1 1- (1) A transparent conductive film made of ITO or the like is formed on a transparent insulating substrate 11 such as glass.

1- (2) An amorphous Si film containing impurities is laminated on a transparent conductive film. 1- (3) The impurity-containing amorphous Si film and the transparent conductive film are patterned to form a source electrode contact layer 13S and a drain electrode contact layer 13D, and a source electrode 12S and a drain electrode 12D.

See FIG. 2 2- (1) An amorphous Si film to be an operating semiconductor layer, a SiN film to be a gate insulating film, and an Al film to be a gate electrode are formed on the entire surface. 2- (2) A resist film 17 is formed and patterned by applying a resist process in the lithography technique.

Referring to FIG. 3, 3- (1) For example, by applying a wet etching method using an etchant of H ₃ PO ₄ system as an etchant, the Al film is etched using the resist film 17 as a mask to form the gate electrode. 16 is formed.

The gate electrode 16 formed here is narrowed as compared with the pattern of the resist film 17 by the side etching. Therefore, the wet etching method is adopted for the etching here.

3- (2) Subsequently, for example, reactive ion etching (reactive io) using a CHF ₃ system gas as an etching gas is performed.
By applying the etching (RIE) method, the SiN film, the amorphous Si film, the source electrode contact layer 13S and the drain electrode contact layer 13D are mesa-etched to form the gate insulating film 15 and the operating semiconductor layer 14. At the same time, unnecessary portions of the source electrode contact layer 13S and the drain electrode contact layer 13D are removed.

3- (3) The resist film 17 is removed by immersing it in a resist stripping solution. Here, it should be noted that the side surfaces of the gate insulating film 15 and the operating semiconductor layer 14 and the side surface of the gate electrode 16 are not flush with each other, that is, have a step shape.

See FIG. 4. 4- (1) By applying the electrodeposition method, the exposed portion of the gate electrode 16 is entirely covered with the resin film 18.

According to the electrodeposition method, a resin film made of a polymer called an electrodeposition resist can be formed, and the resin film has good adhesion to the base and good followability. It can be applied as a uniform thin film to a base having a complicated shape. The electrodeposition method will be described in more detail later in one of the examples.

Therefore, the resin film 18 can cover the gate electrode 16 having a complicated shape with good coverage.
It is possible to prevent a leak current from flowing between the gate electrode 16 and the source electrode 12S or the drain electrode 12D.

From the above, in the thin film transistor and the manufacturing method thereof according to the present invention, (1) stacked source electrodes (for example, the source electrode 25)
S) and the source electrode contact layer (for example, the source electrode contact layer 26S) and the stacked drain electrode (for example, the drain electrode 25D) and the drain electrode contact layer (for example, the drain electrode contact layer 26D) on which a transparent insulating substrate (for example, An operating semiconductor layer (for example, operating semiconductor layer 2) formed by further stacking on the glass substrate 21.
9) and a gate insulating film (for example, the gate insulating film 30) and a gate electrode (for example, the gate electrode 31), and the gate electrode is formed such that the side wall of the gate electrode and the side wall of the underlying gate insulating film have a step difference. Characterized in that it is narrowed with respect to the underlying gate insulating film, or

(2) In (1) above, a protective film (for example, a resin film 33) covering the gate electrode is formed, and the side wall of the protective film and the side wall of the underlying gate insulating film are flush with each other. Or

(3) In the above (1), the protective film covering the gate electrode is a resin film formed by applying an electrodeposition method, or

(4) In the above (1), the protective film covering the gate electrode is an anodic oxide film formed by applying an anodic oxidation method, or

(5) In the above (1), a protective film (for example, a protective film 3 made of polymer) is formed only on the side wall of the gate electrode.
4) is formed and the side wall of the protective film and the side wall of the underlying gate insulating film are flush with each other, or

(6) In the above (5), the protective film formed only on the side wall of the gate electrode is a resin film obtained by applying an electrodeposition method, or

(7) In (5), the protective film formed only on the side wall of the gate electrode is an anodic oxide film obtained by applying an anodic oxidation method to the gate electrode (for example, a protective film made of Al ₂ O _3). Membrane 35), or

(8) An electrode material film (for example, ITO film) and an electrode contact layer (for example, n ⁺ -amorphous Si layer) are laminated and formed on a transparent insulating substrate (for example, glass substrate 21) and then patterned to form a source. A step of forming an electrode (for example, source electrode 25S) and a source electrode contact layer (for example, source electrode contact layer 26S), a drain electrode (for example, drain electrode 25D) and a drain electrode contact layer (for example, drain electrode contact layer 26D), and then A step of stacking an operating semiconductor layer (for example, an operating semiconductor layer 29 made of amorphous Si), a gate insulating film (for example, gate insulating film 30) and an electrode material film (for example, Al film) on the entire surface, and then an uppermost electrode material The film (Al film) is patterned to form a gate electrode (for example, a gate electrode). 31), and then a protective film (for example, a resin film 33 formed by an electrodeposition method) covering the gate electrode is formed, and then the underlying gate insulating film, operating semiconductor layer, source electrode contact layer, and drain electrode are formed. Or a step of patterning a contact layer, or

(9) In the above (8), a protective film made of an electrodeposition resin covering the gate electrode by applying an electrodeposition method after removing the etching mask (for example, the resist film 32) on the surface of the gate electrode. (For example, resin film 33) is included, or

(10) In the above (8), a step of removing the etching mask on the surface of the gate electrode and then applying an anodic oxidation method to form a protective film made of an anodic oxide film covering the gate electrode is included. It is characterized by being

(11) In the above (8), a protective film (for example, protective film 34) is formed on the surface of the gate electrode to cover only the side wall while leaving the etching mask, and then the underlying gate insulating film and the operating semiconductor are formed. A layer and a source electrode contact layer and a drain electrode contact layer are patterned, or

(12) In the above (8) or (11), a step of removing the protective film after patterning the underlying gate insulating film, operating semiconductor layer, source electrode contact layer and drain electrode contact layer is included. Or

(13) In (11) above, the uppermost electrode material film on which the etching mask is formed is exposed to the plasma of a mixed gas of the etching gas for the electrode material film and the gas for forming the protective film. Or a step of forming a protective film made of a polymer covering the side wall of the gate electrode while forming a gate electrode, or
Alternatively,

(14) In the above (11), a step of forming a protective film made of a polymer by exposing the surface of the gate electrode to plasma of a gas for forming a protective film while leaving an etching mask is included. Or

(15) In the above (11), the anodic oxidation method is applied with the etching mask left on the surface of the gate electrode to cover only the side wall of the gate electrode (for example, made of Al ₂ O _3). Or a step of forming a protective film made of the protective film 35), or

(16) In the above (11), the electrodeposition method is applied with the etching mask left on the surface of the gate electrode so as to cover only the side wall of the gate electrode. It is characterized by including a step of forming a protective film 36) made of resin.

[0041]

By adopting the above-mentioned means, it is possible to easily suppress the leak current generated between the gate electrode and the source electrode or the drain electrode along the mesa-shaped side surface of the TFT, which is a waste. It is possible to realize a liquid crystal display device driven by a TFT matrix, which consumes less current.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 5 to 14 are side sectional views showing a staggered type TFT at a process step for explaining a first embodiment of the present invention. While explaining in detail.

See FIG. 5 5- (1) By applying the vacuum deposition method, the light shielding film 22 made of Cr and having a thickness of 700 [Å] is formed on the glass substrate 21.

5- (2) The resist process and etchant in the lithography technique are dicerium ammonium nitrate + perchloric acid +
The light shielding film 22 is patterned into a desired shape by applying a wet etching method using water. 5- (3) P-CVD (plasma chemical vap)
By applying the our deposition method, the interlayer insulating film 23 made of SiO _{2 having} a thickness of, for example, 4000 [Å] is formed.

See FIG. 6 6- (1) By applying the sputtering method, the thickness is, for example, 5
An ITO film of 00 [Å] is formed.

6- (2) By applying the P-CVD method, the thickness is, for example, 350.
[Å] n ⁺ -amorphous Si film, thickness of eg 500
An SiO ₂ film of [Å] is formed. 6- (3) A resist film 28 having an opening 28A defining a channel region is formed by applying a resist process in the lithography technique.

See FIG. 7 7- (1) By applying a wet etching method using an HF + NH ₄ OH + H ₂ O mixed solution as an etchant, the SiO ₂ film is etched using the resist film 28 as a mask to n ⁺ -. A mask film 27 having an opening 27A for etching the amorphous Si film is formed.

The opening 27A of the mask film 27 is formed larger than the opening 28A of the resist film 28 by the side etching, so that the edge of the opening 27A is deeper than the edge of the opening 28A. Become.

7- (2) By applying the RIE method using a CCl ₄ system gas as an etching gas, n ⁺ is used with the resist film 28 as a mask.
-The amorphous Si film is etched to form the source electrode contact layer 26S and the drain electrode contact layer 26D.

7- (3) By applying the wet etching method using HCl + HNO ₃ + H ₂ O mixed solution as the etchant, the resist film 28 and the n ⁺ -amorphous Si source electrode contact layer 26S and the n ⁺ -amorphous Si are applied. The ITO film is etched by using the drain electrode contact layer 26D as a mask to remove the source electrode 25S and the drain electrode 25.
Form D.

See FIG. 8 8- (1) The resist film 28 is removed by immersing it in a resist stripping solution. Here, n ⁺ - amorphous Si source electrode contact layer 26S and n ⁺ - edge of the amorphous Si drain electrode contact layer 26D is in a state of protruding from the edge of the mask layer 27.

See FIG. 9 9- (1) By applying the RIE method using CCl ₄ gas as an etching gas, the mask film 27 is used and the source electrode contact layer 26S and the drain electrode contact layer 26 are used.
D is etched to align the edges.

See FIG. 10. 10- (1) The mask film 27 made of SiO ₂ is removed by immersing in a mixed solution of HF + NH ₄ OH + H ₂ O.

See FIG. 11 11- (1) By applying the P-CVD method, an amorphous Si film having a thickness of, for example, 500 [Å] and a thickness of, for example, 3 are formed on the entire surface.
000 [Å] SiN film and thickness, for example, 4000 [Å]
Al film is sequentially formed.

11- (2) By applying a resist process in the lithography technique, a resist film 32 is formed and patterned.

See FIG. 12 12- (1) For example, an etchant is H ₃ PO ₄ + HNO ₃ + CH ₃ C
By applying a wet etching method using an etching solution composed of a mixed solution of OOH + H ₂ O, the Al film is etched using the resist film 32 as a mask to form the gate electrode 31.

The gate electrode 31 formed here is narrowed compared to the pattern of the resist film 32 by the side etching.

12- (2) Subsequently, for example, the SiN film, the amorphous Si film, the source electrode contact layer 26S, and the drain electrode contact layer 26D are formed by applying the RIE method using CHF ₃ gas as an etching gas. The gate insulating film 30 and the operating semiconductor layer 29 are formed by etching in a mesa shape, and unnecessary portions of the source electrode contact layer 26S and the drain electrode contact layer 26D are removed.

See FIG. 13 13- (1) The resist film 32 is removed by immersion in a resist stripping solution.

See FIG. 14 14- (1) By applying the electrodeposition method, the exposed portion of the gate electrode 31 is entirely covered with the resin film 33 having a thickness of, for example, 1000 [Å]. To carry out the electrodeposition method, the TFT is dipped in a water-soluble photosensitive resin, a voltage of 5 [V] is applied with the gate electrode 31 as an anode, and a polymer is deposited by a pH change due to electrolysis of water. Then, the resin film 33 is formed.

According to the embodiment described above, a TFT having almost the same structure as the TFT described in the principle of the present invention can be obtained.
No leak current flows between the gate electrode 31 and the source electrode 25S or the drain electrode 25D.

FIG. 15 is a sectional side view of a main part of a TFT in a process step for explaining the second embodiment of the present invention, which will be described below with reference to the drawing. The same symbols as those used in FIGS. 5 to 14 represent the same parts or have the same meanings.

In this embodiment, FIG. 14 in the first embodiment is used.
After completing the steps described for
The resin film 33 is made to flow as shown in FIG. 15 by performing heat treatment for 20 [° C.] and time is 5 [minutes], and the gate insulating film 30, the operating semiconductor layer 29, and the source electrode contact layer 26S. , Drain electrode contact layer 2
The side surface such as 6D is also covered with the resin film 33.

According to the second embodiment, the leakage current suppression between the gate electrode 31 and the source electrode 25S or the drain electrode 25D becomes more complete.

FIGS. 16 to 18 are side sectional views showing a stagger type TFT at a process step for explaining the third embodiment of the present invention, which will be described below with reference to the drawings. The details will be described. The same symbols as those used in FIGS. 5 to 15 represent the same parts or have the same meanings. The steps of this embodiment are the same as steps 5- (1) to 11- (2) of the first embodiment, that is, the steps until the resist film 32 is formed, and therefore the description thereof will be omitted. Let's start with.

See FIG. 16 16- (1) For example, an etchant is H ₃ PO ₄ + HNO ₃ + CH ₃ C
By applying a wet etching method using a mixed solution of OOH + H ₂ O, the Al film is etched using the resist film 32 as a mask to form the gate electrode 31.

The gate electrode 31 formed here is formed by side etching as seen in the first embodiment.
It is not necessary to narrow the pattern as compared with the pattern of the resist film 32. However, the resist film 32 is formed as small as the limit of the current lithography technique, and the gate electrode 3
This is not the case when it is desired to form 1 smaller than the resist film 32.

16- (2) The resist film 32 is removed by immersing it in a resist stripping solution.

See FIG. 17 17- (1) By applying the electrodeposition method, the exposed portion of the gate electrode 31 is entirely covered with the resin film 33 having a thickness of, for example, 1000 [Å]. 17- (2) A heat treatment is performed at a temperature of, for example, 60 [° C.] and a time of, for example, 5 [minutes] to evaporate the water and the resin film 33.
Cure.

See FIG. 18 18- (1) For example, RIE using an etching gas of CHF ₃ system gas
By applying the method, the resin film 33 is used as a mask for the S
The iN film, the amorphous Si film, the source electrode contact layer 26S and the drain electrode contact layer 26D are mesa-etched to form the gate insulating film 30 and the operating semiconductor layer 29, and the source electrode contact layer 26S and the drain electrode contact layer 26D are formed. Unnecessary parts are removed.

According to the third embodiment described above, the same TFT as the TFT manufactured according to the first embodiment can be obtained. Therefore, the second embodiment is applied to the TFT obtained according to the third embodiment, the resin film 33 is made to flow, and the gate insulating film 30, the operating semiconductor layer 29, the source electrode contact layer 26S, the drain electrode contact layer are formed. The side surface such as 26D can be covered.

By the way, in any of the above embodiments,
Although the structure in which the gate electrode 31 is completely covered with the electrodeposition resin film 33 has been described, if at least a part of the gate electrode 31 needs to be exposed, the embodiment described below is adopted. good.

FIG. 19 to FIG. 21 are side sectional views showing a main part of the TFT in the process steps for explaining the fourth embodiment of the present invention, which will be described in detail below with reference to the drawings. explain. The same symbols as those used in FIGS. 5 to 18 represent the same parts or have the same meanings. The process of this embodiment is the same as the process 5 of the first embodiment.
Since it does not change from (1) to step 11- (2), that is, until the resist film 32 is formed, description thereof will be omitted, and description will be given from the next step.

See FIG. 19 19- (1) For example, by applying the RIE method in which the etching gas is a mixed gas of Cl ₂ + CH ₂ F ₂ , the resist film 3 is formed.
The Al film is etched using 2 as a mask to form the gate electrode 31.

The conditions for this etching are, for example, Cl ₂ : 20 [sccm] CH ₂ F ₂ : 20 [sccm] gas pressure in the reaction chamber: 5 [Pa] power: 500 [W].

In this etching, the protective film 34 made of polymer is formed on the side wall of the gate electrode 31 simultaneously with the etching. The thickness of the protective film 34 can be made 0.2 [μm] by continuing etching excessively after the exposed Al film is removed by 100 [%]. The protective film 34 is formed thicker as the etching time is lengthened.

After forming the protective film 34, heat treatment can be performed to improve the adhesion at the interface between the protective film 34 and the insulating film 28. However, the heat treatment temperature in this case is preferably 120 [° C.] or less.

See FIG. 20. 20- (1) For example, by applying the RIE method using CF ₄ gas as the etching gas, the protective film 34 and the resist film 3 are formed.
2 is used as a mask to etch the SiN film, the amorphous Si film, the source electrode contact layer 26S and the drain electrode contact layer 26D into a mesa shape,
The operating semiconductor layer 29 is formed and unnecessary portions of the source electrode contact layer 26S and the drain electrode contact layer 26D are removed.

21- (1) The resist film 32 is removed by immersing it in a resist stripping solution,
Further, the protective film 34 is removed by applying an ashing method using O ₂ gas. The ashing conditions in this case are, for example, O ₂ flow rate: 50 [sccm] pressure: 5 [Pa] power: 300 [W].

As seen in the fourth embodiment, the gap between the side wall of the gate electrode 31 and the side wall of the gate insulating film 30 is 0.2.
Due to the existence of the [μm] step, the leakage current between the gate electrode 31 and the source electrode 25S or the drain electrode 25D is reduced to such an extent that it is not a problem in practical use.

22 and 23 are side sectional views showing a TFT in a process essential part for explaining the fifth embodiment of the present invention, which will be described in detail below with reference to the drawings. explain. The same symbols as those used in FIGS. 5 to 21 represent the same parts or have the same meanings.
The process of this embodiment is the same as the process 5 of the first embodiment.
Since it does not change from (1) to step 11- (2), that is, until the resist film 32 is formed, description thereof will be omitted, and description will be given from the next step.

22- (1) By applying the RIE method using Cl ₂ gas as an etching gas, the Al film is etched using the resist film 32 as a mask to form the gate electrode 31.

See FIG. 23. 23- (1) By exposing to a CH ₂ F ₂ gas atmosphere, a protective film 34 made of polymer having a thickness of, for example, 0.2 [μm] is formed on the side wall of the gate electrode 31. 23- (2) After this, the TFT is completed through the same steps as and after the step 20- (1) in the fourth embodiment.

According to this embodiment, although it takes a lot of trouble,
There is an advantage in that the thickness of the protective film 34 can be selected regardless of the formation of the gate electrode 31 only by controlling the time of exposure to the CH ₂ F ₂ gas.

FIG. 24 and FIG. 25 are side sectional views showing the main part of the TFT in the process steps for explaining the sixth embodiment of the present invention, and FIG. 26 explains the formation of the protective film. FIG. 3 is a perspective view of a main part of an anodizing device for use in the present invention, which will be described below in detail with reference to the drawings. The same symbols as those used in FIGS. 5 to 23 represent the same parts or have the same meanings. Further, the steps of this embodiment are up to step 22- (1) in the fifth embodiment, that is,
Since the steps up to forming the gate electrode 31 are the same, they are omitted and description will be given from the next step.

24 and 26. 24- (1) Gate electrode 3 is formed by etching using resist film 32 as a mask.
After forming No. 1 and removing the resist film 32, the glass substrate 21 is dipped in the tartaric acid solution 42 contained in the container 41 to face the similarly dipped Pt electrode 43.

24- (2) Between the glass substrate 21 and the Pt electrode 43, for example, 150
A voltage of [V] is applied to anodize the exposed entire surface of the gate electrode 31 made of Al, and the thickness is, for example, 0.1.
A protective film 35 made of Al ₂ O ₃ of 5 [μm] is formed. The protective film 35 can be formed thicker by increasing the voltage applied between the glass substrate 21 and the Pt electrode 43.

See FIG. 25. 25- (1) For example, by applying the RIE method in which the etching gas is a CF ₄ system gas, Si is used with the protective film 35 as a mask.
N film, amorphous Si film, source electrode contact layer 2
6S and the drain electrode contact layer 26D are etched in a mesa shape to form the gate insulating film 30 and the operating semiconductor layer 29, and unnecessary portions of the source electrode contact layer 26S and the drain electrode contact layer 26D are removed.

According to the present embodiment, the gate electrode 31 is entirely covered with the protective film 35 made of Al ₂ O ₃ except for the surface facing the gate insulating film 29. If the resist film 32 is left on the upper surface of the gate electrode 31, the protective film 35 is formed only by the side wall of the gate electrode 31 by anodic oxidation. In this way, the increase in resistance of the gate electrode 31 due to anodic oxidation can be reduced.

FIG. 27 and FIG. 28 are side sectional views showing the essential part of the TFT in the process steps for explaining the seventh embodiment of the present invention, and FIG. 29 explains the formation of the protective film. It is an explanatory view of a main part of an electrodeposition device for
A detailed description will be given with reference to each drawing. Incidentally, FIGS.
The same symbols as those used in represent the same parts or have the same meanings. The process of this embodiment is the same as the process 22- (1) of the fifth embodiment, that is, the process until the gate electrode 31 is formed, and therefore the description thereof is omitted, and description will be given from the next stage.

27 and 29 27- (1) The gate electrode 3 is etched by using the resist film 32 as a mask.
When 1 is formed, the glass substrate 21 is immersed in the electrodeposition resin solution 44 contained in the container 41 to face the Pt electrode 43 which is also immersed.

27- (2) Between the glass substrate 21 and the Pt electrode 43, for example, 5 [V]
Is applied to form a protective film 36 made of an electrodeposition resin having a thickness of 0.5 [μm] on the side wall of the gate electrode 31. The protective film 36 can be formed thicker by increasing the voltage applied between the glass substrate 21 and the Pt electrode 43.

28- (1) For example, by applying the RIE method in which the etching gas is a CF ₄ system gas, the protective film 36 and the resist film 3 are formed.
2 is used as a mask to etch the SiN film, the amorphous Si film, the source electrode contact layer 26S and the drain electrode contact layer 26D in a mesa shape to form a gate insulating film 30,
The operating semiconductor layer 29 is formed and unnecessary portions of the source electrode contact layer 26S and the drain electrode contact layer 26D are removed. 28- (2) The resist film 32 is removed by immersion in a resist stripping solution.

FIG. 30 shows the gate voltage V _g and the drain current I _{d for} explaining the characteristics of the TFT obtained according to the present invention.
In the figure, the horizontal axis represents the gate voltage V _g , the vertical axis represents the drain current I _d , and the parameter is the step d. In the figure, L indicates the channel length, W indicates the channel width, and 1E-13 means 1 × 10 ⁻¹³ , for example.

As is clear from the figure, d <0.05 [μ
In the case of m], a negative leak current between the gate and the source occurs, and the off characteristics deteriorate. That is, the completely off state cannot be maintained.

When d> 1 [μm], the operating semiconductor layer made of amorphous Si protruding from the gate electrode in the gate length direction is completely off even when a negative voltage is applied to the gate electrode. Since it is not in a state, a positive leak current flows between the drain and source.

From the above, the step d is 0.0
When the range is 5 [μm] ≦ d ≦ 1.0 [μm], it is possible to obtain a TFT with a small leak current in the off state.

[0098]

According to the thin film transistor and the method of manufacturing the same according to the present invention, the gate electrode is different from the underlying gate insulating film in such a manner that there is a step between the sidewall of the gate electrode and the sidewall of the underlying gate insulating film. Have been narrowed.

By adopting the above structure, it is possible to suppress the leak current generated between the gate electrode and the source or drain electrode along the mesa-shaped side surface of the TFT by a simple means. Therefore, it is possible to realize a liquid crystal display device driven by a TFT matrix with less wasted current consumption.

[Brief description of drawings]

FIG. 1 is a cross-sectional side view showing a main part of a TFT in a process step for explaining the principle of the present invention.

FIG. 2 is a cross-sectional side view showing a main part of a TFT in a process main part for explaining the principle of the present invention.

FIG. 3 is a cross-sectional side view showing a main part of a TFT in a process main part for explaining the principle of the present invention.

FIG. 4 is a cross-sectional side view showing a main part of a TFT at a process step for explaining the principle of the present invention.

FIG. 5 is a cutaway side view showing a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 6 is a cutaway side view of a main part of a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 7 is a cutaway side view of an essential part of a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 8 is a cutaway side view of an essential part of a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 9 is a side sectional view showing a main part of a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 10 is a side sectional view showing a main part of a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 11 is a side sectional view showing a main part of a staggered TFT at a process step for explaining the first embodiment of the present invention.

FIG. 12 is a side sectional view showing a staggered TFT at a main part of a process for explaining a first embodiment of the present invention.

FIG. 13 is a side sectional view showing a main part of a staggered TFT at a process key point for explaining the first embodiment of the present invention.

FIG. 14 is a cutaway side view of a main part showing a staggered TFT at a process key point for explaining the first embodiment of the present invention.

FIG. 15 is a side sectional view showing a main part of a TFT in a process main part for explaining a second embodiment of the present invention.

FIG. 16 is a fragmentary side view showing a staggered type TFT in a process essential part for explaining a third embodiment of the present invention.

FIG. 17 is a sectional side view showing a main part of a staggered TFT at a process key point for explaining a third embodiment of the present invention.

FIG. 18 is a fragmentary side view showing a staggered type TFT at a process step for explaining a third embodiment of the present invention.

FIG. 19 is a side sectional view showing a main part of a TFT in a process main part for explaining a fourth embodiment of the present invention.

FIG. 20 is a side sectional view showing a main part of a TFT in a process step for explaining a fourth embodiment of the present invention.

FIG. 21 is a side sectional view showing an essential part of a TFT in a process essential part for explaining a fourth embodiment of the present invention.

FIG. 22 is a side sectional view showing an essential part of a TFT in a process essential part for explaining a fifth embodiment of the present invention.

FIG. 23 is a side sectional view showing an essential part of a TFT in a process essential part for explaining a fifth embodiment of the present invention.

FIG. 24 is a side sectional view showing a main portion of a TFT in a process key point for explaining a sixth embodiment of the present invention.

FIG. 25 is a side sectional view showing a main part of a TFT in a process essential part for explaining a sixth embodiment of the present invention.

FIG. 26 is a perspective view of a main part of the anodizing device for explaining the formation of the protective film in the sixth embodiment.

FIG. 27 is a side sectional view showing an essential part of a TFT in a process essential part for explaining a seventh embodiment of the present invention.

FIG. 28 is a side sectional view showing a main part of a TFT in a process essential part for explaining a seventh embodiment of the present invention.

FIG. 29 is a perspective view of the main part of the electrodeposition apparatus for explaining the formation of the protective film in the seventh example.

FIG. 30 is a diagram showing the relationship between the gate voltage V _g and the drain current I _d for explaining the characteristics of the TFT obtained according to the present invention.

FIG. 31 is a fragmentary side view showing a staggered TFT at a process essential point for explaining the conventional technique.

FIG. 32 is a fragmentary side view showing a staggered TFT at a process essential point for explaining the conventional technique.

FIG. 33 is a side sectional view showing an essential part of a staggered TFT at a process essential point for explaining the conventional technique.

[Explanation of symbols]

 11 Transparent Insulating Substrate such as Glass 12S Source Electrode 12D Drain Electrode 13S Source Electrode Contact Layer 13D Drain Electrode Contact Layer 14 Operating Semiconductor Layer 15 Gate Insulating Film 16 Gate Electrode 17 Resist Film 18 Resin Film 21 Glass Substrate 22 Light Shading Film 23 Interlayer Insulation Film 25S Source electrode 25D Drain electrode 26S Source electrode Contact layer 26D Drain electrode Contact layer 27 Mask film 27A Opening 28 Resist film 28A Opening 29 Operating semiconductor layer 30 Gate insulating film 31 Gate electrode 32 Resist film 33 Resin film 34 Polymer protective film 35 protective film 36 protective film 41 container 42 tartaric acid 43 Pt electrode 44 electrodeposition resin liquid

Front page continued (72) Inventor Kenichi Oki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa within Fujitsu Limited

Claims (16)

[Claims] 1. An operating semiconductor layer and a gate insulating film, which are further stacked on a transparent insulating substrate on which a stacked source electrode and a source electrode contact layer and a stacked drain electrode and a drain electrode contact layer are formed. And a gate electrode, wherein the gate electrode is narrowed with respect to the underlying gate insulating film so that a side wall of the gate electrode and a sidewall of the underlying gate insulating film have a step difference. . 2. The thin film transistor according to claim 1, wherein a protective film covering the gate electrode is formed, and the side wall of the protective film and the side wall of the underlying gate insulating film are flush with each other. 3. The thin film transistor according to claim 1, wherein the protective film covering the gate electrode is a resin film formed by applying an electrodeposition method. 4. The thin film transistor according to claim 1, wherein the protective film covering the gate electrode is an anodic oxide film formed by applying an anodic oxidation method. 5. The thin film transistor according to claim 1, wherein a protective film is formed only on the side wall of the gate electrode, and the side wall of the protective film and the side wall of the underlying gate insulating film are flush with each other. 6. The thin film transistor according to claim 5, wherein the protective film formed only on the side wall of the gate electrode is a resin film obtained by applying an electrodeposition method. 7. The thin film transistor according to claim 5, wherein the protective film formed only on the side wall of the gate electrode is an anodized film obtained by applying an anodizing method to the gate electrode. 8. A step of forming an electrode material film and an electrode contact layer on a transparent insulating substrate and then patterning to form a source electrode and a source electrode contact layer and a drain electrode and a drain electrode contact layer, and A step of stacking an operating semiconductor layer, a gate insulating film, and an electrode material film on the entire surface, a step of patterning the uppermost electrode material film to form a gate electrode, and a protective film covering the gate electrode. And then patterning the underlying gate insulating film, the operating semiconductor layer, the source electrode contact layer, and the drain electrode contact layer. 9. The method comprises the steps of removing an etching mask on the surface of the gate electrode and then applying an electrodeposition method to form a protective film made of an electrodeposition resin covering the gate electrode. Item 9. A method for manufacturing a thin film transistor according to Item 8. 10. The method comprises the steps of removing an etching mask on the surface of the gate electrode and then applying an anodizing method to form a protective film made of an anodized film covering the gate electrode. Item 9. A method for manufacturing a thin film transistor according to Item 8. 11. A step of patterning the underlying gate insulating film, the operating semiconductor layer, the source electrode contact layer and the drain electrode contact layer after forming a protective film on the surface of the gate electrode while covering the sidewall while leaving an etching mask. 9. The method of manufacturing a thin film transistor according to claim 8, further comprising: 12. The method according to claim 8, further comprising a step of removing the protective film after patterning the underlying gate insulating film, the operating semiconductor layer, the source electrode contact layer and the drain electrode contact layer. 11. The method for manufacturing a thin film transistor according to item 11. 13. A gate electrode is formed by patterning the uppermost electrode material film having an etching mask by exposing it to plasma of a mixed gas of an etching gas for the electrode material film and a gas for forming a protective film. The method of manufacturing a thin film transistor according to claim 11, further comprising the step of forming a protective film made of a polymer covering the side wall of the thin film transistor. 14. The method according to claim 11, further comprising the step of forming a protective film made of a polymer by exposing the gate electrode to a plasma of a gas for forming a protective film while leaving an etching mask on the surface of the gate electrode. A method for manufacturing the thin film transistor described. 15. The method further comprises the step of applying an anodic oxidation method while leaving an etching mask on the surface of the gate electrode to form a protective film made of an anodic oxide film covering only the side wall of the gate electrode. The method of manufacturing a thin film transistor according to claim 11. 16. A step of applying an electrodeposition method while leaving an etching mask on the surface of the gate electrode to form a protective film made of an electrodeposition resin covering only the side wall of the gate electrode. The method of manufacturing a thin film transistor according to claim 11.