JPH07273300A - CMOS negative logic circuit structure and layout wiring method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a CMOS negative logic circuit structure and a layout wiring method thereof which can reduce the process-induced damage of a gate oxide film without lowering the layout efficiency. A C including two N-channel transistors 30 and 31 connected in series with each other via a common diffusion layer 29.
In the MOS negative logic circuit structure, in the common diffusion layer 29,
At least one connection hole 36 is formed, and the wiring 37 is connected to the common diffusion layer 29 through the connection hole 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS negative logic circuit structure and its layout wiring method, and more particularly to a CMO.
The present invention relates to a structure of an N-channel transistor forming an S-NAND circuit and a P-channel transistor forming a CMOS-NOR circuit, and a layout wiring method thereof.

[0002]

2. Description of the Related Art Replacement of LSI generations is accompanied by miniaturization of devices. The miniaturization of this device includes thinning of the gate oxide film. However, when the gate oxide film is thinned, the miniaturization of the LSI can be promoted, but on the other hand, there is a possibility that the reliability is lowered, and the damage received during the process tends to become more serious. For example, the technique used for wiring processing is RIE (Reactive Ion Etching), which cuts wiring by RIE,
When processing the gate electrode, the wiring is likely to be charged up.

In consideration of this charge-up, in a normal transistor having one gate electrode and two diffusion layers, wiring is connected to the two diffusion layers through connection holes, respectively. The electric potentials of the two diffusion layers are charged up to almost the same electric potential. Therefore, the potential difference between the gate electrode and the two diffusion layers is approximately 0 (V).
Therefore, it is difficult to apply a large potential to the gate oxide film.

[0004]

However, the CMOS-
When laying out a NAND circuit or the like, there is a diffusion layer having no connection hole and no wiring. Figure 7 shows the CMO
An S2 input NAND circuit is shown. In the figure, two P
The channel transistors Q _p1 and Q _p2 are connected in parallel with each other, and their common source connection point is connected to the power supply (V _DD ). Two N-channel transistors Q _n1 and Q _n2 are connected in series with each other between the common drain connection point of the P-channel transistors Q _p1 and Q _p2 and the ground (V _SS ).

The gates of the P-channel transistor Q _p1 and the N-channel transistor Q _n2 are commonly connected, and the input signal V _in 1 is applied to the common connection point. Also,
Gates of the P-channel transistor Q _p2 and the N-channel transistor Q _n1 are commonly connected, and the input signal V _in 2 is applied to the common connection point. Then, from the drain end of the N-channel transistor Q _n1 (the common drain connection point of the P-channel transistors Q _p1 and Q _p2 ), the output signal V
_out is derived.

In the CMOS 2-input NAND circuit having the above structure, the common diffusion layer of the two N-channel transistors Q _n1 and Q _n2 connected in series does not have a connection hole or wiring. That is, the point A has no stray capacitance due to the wiring. FIG. 8 shows an equivalent circuit of the N-channel transistor Q _n1 . In the figure, wiring capacitances C1 and C3 are connected to the gate electrode 81 and the diffusion layer 82, respectively, and the plasma density is uniform during etching and C1≈C.
3, the potential V1 of the gate electrode 81 and the potential V3 of the diffusion layer 82 become V1≈V3, and therefore the gate oxide film 8
No potential difference is generated in 3.

On the other hand, the common diffusion layer 84 is in a so-called floating state because it has no connection hole and no wiring.
Generally, the value is about the potential V5 (= C5 / Q) of the substrate 85 plus the built-in voltage. Where the substrate 85
If the wiring capacitance of C5 is C5 and the charge is Q, then V5 = C5 / Q
Is. Further, the built-in voltage means the height of the potential barrier generated in the PN junction in the state where no voltage is applied.

However, when a factor such as a current flowing through the substrate is added due to non-uniformity of plasma density or time change, the value of the potential Vx of the diffusion layer 84 cannot be known and control is performed. It is impossible. Therefore, the common diffusion layer 84 may have a potential difference of about several tens (V) with respect to the gate electrode 81 depending on the situation. In general,
Since the common diffusion layer 84 overlaps the gate electrode 81, a voltage of about several tens (V) is applied to the gate oxide film 83 in the overlapping portion, which causes a breakdown voltage failure. There's a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a CMOS negative logic circuit structure capable of reducing the damage due to the process of the gate oxide film without lowering the layout efficiency and the same. It is to provide a layout wiring method.

[0010]

In order to achieve the above object, the present invention provides a CMOS negative logic circuit structure including two transistors connected in series with each other via a common diffusion layer on the common diffusion layer. At least one connection hole is formed, and the wiring is connected to the common diffusion layer through the connection hole. Further, in the layout wiring, data for forming the connection hole and the wiring is defined in advance on the common diffusion layer located between the two gate electrodes.

Further, according to the present invention, in a CMOS negative logic circuit type gate array, a gate electrode having data for forming a connection hole and a wiring is selected from all transistors, and a diffusion adjacent to the gate electrode is selected. A layer is selected, and if there is no data for forming a connection hole and wiring in the selected diffusion layer, that data is generated.

[0012]

In the CMOS negative logic circuit structure, by forming at least one connection hole and wiring in the common diffusion layer of two transistors connected in series with each other, this common diffusion layer is formed by the wiring capacitance of the substrate. It is possible to maintain a certain potential regardless of the potential of. Therefore, no large voltage is applied to the gate oxide film in the portion where the common diffusion layer overlaps the gate electrode.

In the CMOS negative logic circuit type gate array, the transistor of the gate electrode having data for forming the connection hole and the wiring is a transistor for use. Therefore, the diffusion layer of this transistor is selected, and the connection hole and the wiring are formed only in the selected diffusion layer. As a result, the connection hole and the wiring are always formed on the common diffusion layer of the two transistors only for the transistor to be used.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a plan pattern diagram showing an embodiment of the present invention, and shows a case where it is applied to a CMOS 2-input NAND circuit, for example. 2 (A) and (B)
1A and 1B show cross sections taken along arrows AA ′ and BB ′ in FIG. 1, respectively. 1 and 2, the n-type semiconductor substrate 11
Two p ⁺ -type diffusion layers 12 and 13 constituting the source region is formed on the surface side of the two p ⁺ -type diffusion layer 12,
P ⁺ -type common diffusion layer 1 forming a drain region between 13
4 are formed.

Each of the two p ⁺ type diffusion layers and p ⁺
Two P-channel transistors 17 and 18 are formed by disposing the gate electrodes 15 and 16 on the channel region between the common diffusion layer 14 and the type. In the interlayer insulating film 19 on the n-type semiconductor substrate 11, the p ⁺ -type diffusion layer 1
Connection holes 20 and 21 are formed on 2 and 13. Wirings 23 and 24 for supplying power (V _DD ) are connected to the p ⁺ type diffusion layers 12 and 13 through the connection holes 20 and 21, respectively. Further, a connection hole 22 is formed on the drain region 14, and a wiring 25 is formed through this connection hole 22.
Are connected.

On the other hand, a p-well 26 is formed on the n-type semiconductor substrate 11, and two n ⁺ -type diffusion layers 27 and 2 forming a drain region and a source region are formed on the surface side thereof.
8 is formed, and an n ⁺ type common diffusion layer 29 forming a source region and a drain region is formed between the two n ⁺ type diffusion layers 27 and 28. By arranging the gate electrodes 15 and 16 on the channel region between each of the two n ⁺ type diffusion layers 27 and 28 and the n ⁺ type common diffusion layer 29, the two N channel transistors 30 and 31 are formed. Is configured.

In the interlayer insulating film 19, the n ⁺ type diffusion layer 2
Connection holes 32 and 33 are formed on the wirings 7 and 28, and wirings 34 and 35 are connected through the connection holes 32 and 33, respectively. Then, the wiring 34 is connected to the power supply (V _SS ). The connection hole 36 is also formed on the n ⁺ type common diffusion layer 29.
Is formed, and the wiring 37 is connected through the connection hole 36.

In the CMOS 2-input NAND circuit having the above structure, N-channel transistors 30 connected in series,
The wiring capacitance for each gate electrode 15 and 16 of 31 is C
1, C2, the wiring capacitances for the n ⁺ type diffusion layers 27, 28 are C3, C4, the wiring capacitance for the substrate 11 is C5, and the wiring capacitance for the n ⁺ type common diffusion layer 29 is C6, the equivalent circuit is shown in FIG. As shown. Here, the wiring capacitance C
Reference numeral 6 is not for giving or reading a potential in the operation of the transistors 30 and 31.

As mentioned above, CMOS 2-input NAND
In the circuit, the connection hole 36 is formed also on the n ⁺ -type common diffusion layer 29 which is normally in a floating state, and
By connecting the wiring 37 through the connection hole 36, the n ⁺ -type common diffusion layer 29 can maintain a certain potential regardless of the potential V5 of the substrate 11 due to the wiring capacitance C6. That is, assuming that the potentials of the wiring capacitors C1 to C6 are V1 to V6, the gate electrodes 15 and 16 and n ⁺
The potential difference with the type common diffusion layer 29 is (V1-V6),
(V2-V6) and (V1-V3), (V1-V4)
Becomes

As a result, a large voltage is not applied to the gate oxide film 38 in the portion where the n ⁺ -type common diffusion layer 29 overlaps the gate electrodes 15 and 16, so that wiring during the manufacturing process is not affected. Damage to the gate oxide film 38 due to charge-up that occurs during processing can be reduced without lowering layout efficiency. In this embodiment, one connection hole 36 and one wiring 37 are formed in the n ⁺ -type common diffusion layer 29, but the number is not limited to one, and two or more connection holes 36 and wirings 37 may be formed if necessary. It may be formed.

As described above, the formation of the connection hole 36 and the wiring 37 also on the n ⁺ -type common diffusion layer 29 can be easily realized by using a so-called handwritten layout wiring, but CAD (computer aided) When using the automatic layout wiring according to design etc., it can be realized by following the procedure shown in the flowchart of FIG. That is, in the basic cell of the NAND type gate array, as shown in FIG.
In the portion of the common diffusion layer 43 located between 1 and 42, data (hereinafter, referred to as contact data) for forming the connection hole and the wiring is defined in advance and cell registration is performed (step S11). Layout wiring is executed (step S12).

As described above, by defining the contact data in advance for the common diffusion layer 43, the connection hole 46 and the wiring 47 can be formed in all the common diffusion layers 43 of the transistor without fail. it can. Further, since layout wiring can be performed without performing a logical operation, there is an advantage that it is advantageous in terms of time. By forming the connection hole and the wiring in the common diffusion layer in this manner, the connection hole and the wiring may be formed in the diffusion layer 44 when the gate electrode 41 is used. When using 42, the connection hole and the wiring may be formed in the diffusion layer 45.

On the contrary, when the gate electrode 41 is not used, it is not necessary to use the diffusion layer 44. Therefore, since the connection hole and the wiring are not formed in the diffusion layer 44, the gate electrode 41 is not formed. There is no problem even if the contact gate oxide film is damaged due to the process. Therefore, the contact data defined in advance need only be the common diffusion layer 43 portion. As described above, if the common diffusion layer 43 is limited to only the layout, the layout efficiency is not lowered.

In the case of the automatic layout wiring described above, the connection hole and the wiring are formed in the common diffusion layer of all transistors regardless of the transistors used and the transistors not used. Since there is no problem with the presence or absence of damage due to the process, the connection hole and the wiring may be formed in the common diffusion layer of only the transistor used. The procedure will be described below with reference to the flowchart of FIG.

In FIG. 6, first, automatic layout wiring is performed based on the layout data (step S2).
1) Then, a gate electrode having contact data is selected from all the transistors (step S22).
The gate electrode transistor having the contact data is a required transistor.

Then, a diffusion layer adjacent to the gate electrode having contact data is selected from all the diffusion layers arranged with the gate electrode interposed therebetween (step S23), and then the selected diffusion layer is contacted. It is checked whether or not there is data (step S24). Then, contact data is generated in the diffusion layer having no contact data (step S25).

According to the layout wiring method described above, the connection hole and the wiring are formed only in the common diffusion layer of the transistor used. Therefore, as in the case of the layout wiring method described above, there is an advantage that a connection hole and a wiring are not formed in the common diffusion layer of an unused transistor and the amount of data is small.

In the above embodiment, the case where the present invention is applied to the N-channel transistor of the CMOS-NAND circuit shown in FIG. 7 has been described, but the present invention is not limited to this and the CMOS-NOR circuit shown in FIG. 9 is used. It can be similarly applied to a P-channel transistor. Figure 9
In, the two P-channel transistors Q _p3 and Q _p4 are connected in series with each other, and the source of the P-channel transistor Q _p3 is connected to the power supply (V _DD ). Two N-channel transistors Q _n3 and Q _n4 are connected in parallel with each other between the drain of the P-channel transistor Q _p4 and the ground (V _SS ).

The gates of the P-channel transistor Q _p3 and the N-channel transistor Q _n3 are commonly connected, and the input signal V _in 1 is applied to the common connection point. Also,
Gates of the P-channel transistor Q _p4 and the N-channel transistor Q _n4 are commonly connected, and the input signal V _in 2 is applied to the common connection point. The output signal V _out is derived from the drain end of the P-channel transistor Q _p3 .

In the case of forming this CMOS-NOR circuit, at least one connecting hole and wiring are provided on the common diffusion layer (point B in the figure) between the P-channel transistors Q _p3 and Q _p4 connected in series. By forming the common diffusion layer, it becomes possible to maintain a certain electric potential irrespective of the electric potential of the substrate due to the wiring capacitance thereof, as in the case of the above embodiment. Therefore, since a large voltage is not applied to the gate oxide film in the portion where the common diffusion layer overlaps the gate electrode, the gate oxide film due to charge-up that occurs during wiring processing during the manufacturing process. The damage of can be reduced.

[0031]

As described above, according to the present invention,
In a CMOS negative logic circuit structure including two transistors connected in series with each other via a common diffusion layer, at least one connection hole and at least one wiring are formed in the common diffusion layer. With the wiring capacitance, it is possible to maintain a certain potential regardless of the potential of the substrate. Therefore, since a large voltage is not applied to the gate oxide film in the portion where the common diffusion layer overlaps the gate electrode, damage to the gate oxide film due to charge-up that occurs during wiring processing during the manufacturing process. Can be reduced without lowering the layout efficiency.

In addition, in the CMOS NAND gate type gate array, a gate electrode having contact data is selected from all the transistors, a diffusion layer adjacent to the gate electrode is selected, and the selected diffusion layer is selected. By generating the contact data when the contact data does not exist, the connection hole and the wiring can be formed only in the common diffusion layer of the transistor to be used, so that there is no waste and the data amount is small. Will be completed.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram according to the present invention.

FIG. 4 is a plan pattern view of a basic cell of a gate array according to the present invention.

FIG. 5 is a flowchart showing an example of a processing procedure of a layout wiring method according to the present invention.

FIG. 6 is a flowchart showing another example of the processing procedure of the layout wiring method according to the present invention.

FIG. 7 is a circuit diagram of a CMOS-NAND circuit.

FIG. 8 is an equivalent circuit diagram showing a conventional example.

FIG. 9 is a circuit diagram of a CMOS-NOR circuit.

[Explanation of symbols]

11 n-type semiconductor substrate 14 p ⁺ type common diffusion layer 15, 16 gate electrode 17, 18 P-channel transistor 20 to 22, 32, 33, 36 connection hole 23 to 25, 34, 35, 37 wiring 29 n ⁺ type common diffusion Layer 30, 31 N-channel transistor 38 Gate oxide film

Claims (3)

[Claims] 1. A CMOS negative logic circuit structure including two transistors connected in series with each other through a common diffusion layer, comprising at least one connection hole formed on the common diffusion layer and the connection. And a wiring connected to the common diffusion layer through a hole, a CMOS negative logic circuit structure. 2. In a CMOS negative logic circuit type gate array, data for forming at least one connection hole and wiring is previously defined on a common diffusion layer located between two gate electrodes, and this definition is defined. A layout wiring method, characterized in that a connection hole and a wiring are formed based on the obtained data. 3. In a CMOS negative logic circuit type gate array, a gate electrode having data for forming a connection hole and a wiring is selected from all transistors, and a diffusion layer adjacent to the gate electrode is selected. A layout and wiring method characterized in that when there is no data for forming a connection hole and wiring in the selected diffusion layer, the data is generated.